David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. |
| 3 | * |
| 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 5 | * Copyright (c) 2013 David Gibson, IBM Corporation |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
Peter Maydell | 0d75590 | 2016-01-26 18:16:58 +0000 | [diff] [blame] | 20 | #include "qemu/osdep.h" |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 21 | #include "cpu.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 22 | #include "exec/exec-all.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 23 | #include "exec/helper-proto.h" |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 24 | #include "qemu/error-report.h" |
Markus Armbruster | fad866d | 2019-04-17 21:17:58 +0200 | [diff] [blame] | 25 | #include "qemu/qemu-print.h" |
Vincent Palatin | b394662 | 2017-01-10 11:59:55 +0100 | [diff] [blame] | 26 | #include "sysemu/hw_accel.h" |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 27 | #include "kvm_ppc.h" |
| 28 | #include "mmu-hash64.h" |
Paolo Bonzini | 508127e | 2016-01-07 16:55:28 +0300 | [diff] [blame] | 29 | #include "exec/log.h" |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 30 | #include "hw/hw.h" |
Suraj Jitindar Singh | b289949 | 2017-03-01 17:54:38 +1100 | [diff] [blame] | 31 | #include "mmu-book3s-v3.h" |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 32 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 33 | /* #define DEBUG_SLB */ |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 34 | |
| 35 | #ifdef DEBUG_SLB |
Paolo Bonzini | 48880da | 2015-11-13 13:34:23 +0100 | [diff] [blame] | 36 | # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 37 | #else |
| 38 | # define LOG_SLB(...) do { } while (0) |
| 39 | #endif |
| 40 | |
| 41 | /* |
| 42 | * SLB handling |
| 43 | */ |
| 44 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 45 | static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 46 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 47 | CPUPPCState *env = &cpu->env; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 48 | uint64_t esid_256M, esid_1T; |
| 49 | int n; |
| 50 | |
| 51 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); |
| 52 | |
| 53 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; |
| 54 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; |
| 55 | |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 56 | for (n = 0; n < cpu->hash64_opts->slb_size; n++) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 57 | ppc_slb_t *slb = &env->slb[n]; |
| 58 | |
| 59 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" |
| 60 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 61 | /* |
| 62 | * We check for 1T matches on all MMUs here - if the MMU |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 63 | * doesn't have 1T segment support, we will have prevented 1T |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 64 | * entries from being inserted in the slbmte code. |
| 65 | */ |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 66 | if (((slb->esid == esid_256M) && |
| 67 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) |
| 68 | || ((slb->esid == esid_1T) && |
| 69 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { |
| 70 | return slb; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | return NULL; |
| 75 | } |
| 76 | |
Markus Armbruster | fad866d | 2019-04-17 21:17:58 +0200 | [diff] [blame] | 77 | void dump_slb(PowerPCCPU *cpu) |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 78 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 79 | CPUPPCState *env = &cpu->env; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 80 | int i; |
| 81 | uint64_t slbe, slbv; |
| 82 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 83 | cpu_synchronize_state(CPU(cpu)); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 84 | |
Markus Armbruster | fad866d | 2019-04-17 21:17:58 +0200 | [diff] [blame] | 85 | qemu_printf("SLB\tESID\t\t\tVSID\n"); |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 86 | for (i = 0; i < cpu->hash64_opts->slb_size; i++) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 87 | slbe = env->slb[i].esid; |
| 88 | slbv = env->slb[i].vsid; |
| 89 | if (slbe == 0 && slbv == 0) { |
| 90 | continue; |
| 91 | } |
Markus Armbruster | fad866d | 2019-04-17 21:17:58 +0200 | [diff] [blame] | 92 | qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 93 | i, slbe, slbv); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | void helper_slbia(CPUPPCState *env) |
| 98 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 99 | PowerPCCPU *cpu = env_archcpu(env); |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 100 | int n; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 101 | |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 102 | /* XXX: Warning: slbia never invalidates the first segment */ |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 103 | for (n = 1; n < cpu->hash64_opts->slb_size; n++) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 104 | ppc_slb_t *slb = &env->slb[n]; |
| 105 | |
| 106 | if (slb->esid & SLB_ESID_V) { |
| 107 | slb->esid &= ~SLB_ESID_V; |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 108 | /* |
| 109 | * XXX: given the fact that segment size is 256 MB or 1TB, |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 110 | * and we still don't have a tlb_flush_mask(env, n, mask) |
| 111 | * in QEMU, we just invalidate all TLBs |
| 112 | */ |
Nikunj A Dadhania | a8a6d53 | 2016-09-20 22:04:59 +0530 | [diff] [blame] | 113 | env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 114 | } |
| 115 | } |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Nikunj A Dadhania | a63f1df | 2017-02-09 16:04:01 +0530 | [diff] [blame] | 118 | static void __helper_slbie(CPUPPCState *env, target_ulong addr, |
| 119 | target_ulong global) |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 120 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 121 | PowerPCCPU *cpu = env_archcpu(env); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 122 | ppc_slb_t *slb; |
| 123 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 124 | slb = slb_lookup(cpu, addr); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 125 | if (!slb) { |
| 126 | return; |
| 127 | } |
| 128 | |
| 129 | if (slb->esid & SLB_ESID_V) { |
| 130 | slb->esid &= ~SLB_ESID_V; |
| 131 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 132 | /* |
| 133 | * XXX: given the fact that segment size is 256 MB or 1TB, |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 134 | * and we still don't have a tlb_flush_mask(env, n, mask) |
| 135 | * in QEMU, we just invalidate all TLBs |
| 136 | */ |
Nikunj A Dadhania | a63f1df | 2017-02-09 16:04:01 +0530 | [diff] [blame] | 137 | env->tlb_need_flush |= |
| 138 | (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 139 | } |
| 140 | } |
| 141 | |
Nikunj A Dadhania | a63f1df | 2017-02-09 16:04:01 +0530 | [diff] [blame] | 142 | void helper_slbie(CPUPPCState *env, target_ulong addr) |
| 143 | { |
| 144 | __helper_slbie(env, addr, false); |
| 145 | } |
| 146 | |
| 147 | void helper_slbieg(CPUPPCState *env, target_ulong addr) |
| 148 | { |
| 149 | __helper_slbie(env, addr, true); |
| 150 | } |
| 151 | |
David Gibson | bcd8123 | 2016-01-27 11:07:29 +1100 | [diff] [blame] | 152 | int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, |
| 153 | target_ulong esid, target_ulong vsid) |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 154 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 155 | CPUPPCState *env = &cpu->env; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 156 | ppc_slb_t *slb = &env->slb[slot]; |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 157 | const PPCHash64SegmentPageSizes *sps = NULL; |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 158 | int i; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 159 | |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 160 | if (slot >= cpu->hash64_opts->slb_size) { |
David Gibson | bcd8123 | 2016-01-27 11:07:29 +1100 | [diff] [blame] | 161 | return -1; /* Bad slot number */ |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 162 | } |
David Gibson | bcd8123 | 2016-01-27 11:07:29 +1100 | [diff] [blame] | 163 | if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { |
| 164 | return -1; /* Reserved bits set */ |
| 165 | } |
| 166 | if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 167 | return -1; /* Bad segment size */ |
| 168 | } |
David Gibson | 58969ee | 2018-03-23 14:11:07 +1100 | [diff] [blame] | 169 | if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 170 | return -1; /* 1T segment on MMU that doesn't support it */ |
| 171 | } |
| 172 | |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 173 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 174 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 175 | |
| 176 | if (!sps1->page_shift) { |
| 177 | break; |
| 178 | } |
| 179 | |
| 180 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { |
| 181 | sps = sps1; |
| 182 | break; |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | if (!sps) { |
| 187 | error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu |
| 188 | " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, |
| 189 | slot, esid, vsid); |
| 190 | return -1; |
| 191 | } |
| 192 | |
David Gibson | bcd8123 | 2016-01-27 11:07:29 +1100 | [diff] [blame] | 193 | slb->esid = esid; |
| 194 | slb->vsid = vsid; |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 195 | slb->sps = sps; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 196 | |
Suraj Jitindar Singh | 76134d4 | 2017-01-13 17:28:22 +1100 | [diff] [blame] | 197 | LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx |
| 198 | " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid, |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 199 | slb->esid, slb->vsid); |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 204 | static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 205 | target_ulong *rt) |
| 206 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 207 | CPUPPCState *env = &cpu->env; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 208 | int slot = rb & 0xfff; |
| 209 | ppc_slb_t *slb = &env->slb[slot]; |
| 210 | |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 211 | if (slot >= cpu->hash64_opts->slb_size) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 212 | return -1; |
| 213 | } |
| 214 | |
| 215 | *rt = slb->esid; |
| 216 | return 0; |
| 217 | } |
| 218 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 219 | static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 220 | target_ulong *rt) |
| 221 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 222 | CPUPPCState *env = &cpu->env; |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 223 | int slot = rb & 0xfff; |
| 224 | ppc_slb_t *slb = &env->slb[slot]; |
| 225 | |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 226 | if (slot >= cpu->hash64_opts->slb_size) { |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 227 | return -1; |
| 228 | } |
| 229 | |
| 230 | *rt = slb->vsid; |
| 231 | return 0; |
| 232 | } |
| 233 | |
Benjamin Herrenschmidt | c76c22d | 2016-06-07 12:50:27 +1000 | [diff] [blame] | 234 | static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
| 235 | target_ulong *rt) |
| 236 | { |
| 237 | CPUPPCState *env = &cpu->env; |
| 238 | ppc_slb_t *slb; |
| 239 | |
| 240 | if (!msr_is_64bit(env, env->msr)) { |
| 241 | rb &= 0xffffffff; |
| 242 | } |
| 243 | slb = slb_lookup(cpu, rb); |
| 244 | if (slb == NULL) { |
| 245 | *rt = (target_ulong)-1ul; |
| 246 | } else { |
| 247 | *rt = slb->vsid; |
| 248 | } |
| 249 | return 0; |
| 250 | } |
| 251 | |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 252 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) |
| 253 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 254 | PowerPCCPU *cpu = env_archcpu(env); |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 255 | |
David Gibson | bcd8123 | 2016-01-27 11:07:29 +1100 | [diff] [blame] | 256 | if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { |
Benjamin Herrenschmidt | 0f72b7c | 2016-07-27 16:56:34 +1000 | [diff] [blame] | 257 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 258 | POWERPC_EXCP_INVAL, GETPC()); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 259 | } |
| 260 | } |
| 261 | |
| 262 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) |
| 263 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 264 | PowerPCCPU *cpu = env_archcpu(env); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 265 | target_ulong rt = 0; |
| 266 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 267 | if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { |
Benjamin Herrenschmidt | 0f72b7c | 2016-07-27 16:56:34 +1000 | [diff] [blame] | 268 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 269 | POWERPC_EXCP_INVAL, GETPC()); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 270 | } |
| 271 | return rt; |
| 272 | } |
| 273 | |
Benjamin Herrenschmidt | c76c22d | 2016-06-07 12:50:27 +1000 | [diff] [blame] | 274 | target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) |
| 275 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 276 | PowerPCCPU *cpu = env_archcpu(env); |
Benjamin Herrenschmidt | c76c22d | 2016-06-07 12:50:27 +1000 | [diff] [blame] | 277 | target_ulong rt = 0; |
| 278 | |
| 279 | if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { |
Benjamin Herrenschmidt | 0f72b7c | 2016-07-27 16:56:34 +1000 | [diff] [blame] | 280 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 281 | POWERPC_EXCP_INVAL, GETPC()); |
Benjamin Herrenschmidt | c76c22d | 2016-06-07 12:50:27 +1000 | [diff] [blame] | 282 | } |
| 283 | return rt; |
| 284 | } |
| 285 | |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 286 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) |
| 287 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 288 | PowerPCCPU *cpu = env_archcpu(env); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 289 | target_ulong rt = 0; |
| 290 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 291 | if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { |
Benjamin Herrenschmidt | 0f72b7c | 2016-07-27 16:56:34 +1000 | [diff] [blame] | 292 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 293 | POWERPC_EXCP_INVAL, GETPC()); |
David Gibson | 10b4652 | 2013-03-12 00:31:06 +0000 | [diff] [blame] | 294 | } |
| 295 | return rt; |
| 296 | } |
David Gibson | 9d7c3f4 | 2013-03-12 00:31:07 +0000 | [diff] [blame] | 297 | |
Suraj Jitindar Singh | 07a68f9 | 2017-03-01 18:12:54 +1100 | [diff] [blame] | 298 | /* Check No-Execute or Guarded Storage */ |
| 299 | static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, |
| 300 | ppc_hash_pte64_t pte) |
| 301 | { |
| 302 | /* Exec permissions CANNOT take away read or write permissions */ |
| 303 | return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? |
| 304 | PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 305 | } |
| 306 | |
| 307 | /* Check Basic Storage Protection */ |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 308 | static int ppc_hash64_pte_prot(PowerPCCPU *cpu, |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 309 | ppc_slb_t *slb, ppc_hash_pte64_t pte) |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 310 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 311 | CPUPPCState *env = &cpu->env; |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 312 | unsigned pp, key; |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 313 | /* |
| 314 | * Some pp bit combinations have undefined behaviour, so default |
| 315 | * to no access in those cases |
| 316 | */ |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 317 | int prot = 0; |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 318 | |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 319 | key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) |
| 320 | : (slb->vsid & SLB_VSID_KS)); |
| 321 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); |
| 322 | |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 323 | if (key == 0) { |
| 324 | switch (pp) { |
| 325 | case 0x0: |
| 326 | case 0x1: |
| 327 | case 0x2: |
Suraj Jitindar Singh | 347a5c7 | 2017-03-01 18:12:53 +1100 | [diff] [blame] | 328 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 329 | break; |
| 330 | |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 331 | case 0x3: |
| 332 | case 0x6: |
Suraj Jitindar Singh | 347a5c7 | 2017-03-01 18:12:53 +1100 | [diff] [blame] | 333 | prot = PAGE_READ | PAGE_EXEC; |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 334 | break; |
| 335 | } |
| 336 | } else { |
| 337 | switch (pp) { |
| 338 | case 0x0: |
| 339 | case 0x6: |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 340 | break; |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 341 | |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 342 | case 0x1: |
| 343 | case 0x3: |
Suraj Jitindar Singh | 347a5c7 | 2017-03-01 18:12:53 +1100 | [diff] [blame] | 344 | prot = PAGE_READ | PAGE_EXEC; |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 345 | break; |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 346 | |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 347 | case 0x2: |
Suraj Jitindar Singh | 347a5c7 | 2017-03-01 18:12:53 +1100 | [diff] [blame] | 348 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 349 | break; |
| 350 | } |
| 351 | } |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 352 | |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 353 | return prot; |
David Gibson | 496272a | 2013-03-12 00:31:14 +0000 | [diff] [blame] | 354 | } |
| 355 | |
Suraj Jitindar Singh | a6152b5 | 2017-03-01 18:12:52 +1100 | [diff] [blame] | 356 | /* Check the instruction access permissions specified in the IAMR */ |
| 357 | static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key) |
| 358 | { |
| 359 | CPUPPCState *env = &cpu->env; |
| 360 | int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; |
| 361 | |
| 362 | /* |
| 363 | * An instruction fetch is permitted if the IAMR bit is 0. |
| 364 | * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit |
| 365 | * can only take away EXEC permissions not READ or WRITE permissions. |
| 366 | * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since |
| 367 | * EXEC permissions are allowed. |
| 368 | */ |
| 369 | return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE : |
| 370 | PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 371 | } |
| 372 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 373 | static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 374 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 375 | CPUPPCState *env = &cpu->env; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 376 | int key, amrbits; |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 377 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 378 | |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 379 | /* Only recent MMUs implement Virtual Page Class Key Protection */ |
David Gibson | 58969ee | 2018-03-23 14:11:07 +1100 | [diff] [blame] | 380 | if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 381 | return prot; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | key = HPTE64_R_KEY(pte.pte1); |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 385 | amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 386 | |
| 387 | /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ |
| 388 | /* env->spr[SPR_AMR]); */ |
| 389 | |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 390 | /* |
| 391 | * A store is permitted if the AMR bit is 0. Remove write |
| 392 | * protection if it is set. |
| 393 | */ |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 394 | if (amrbits & 0x2) { |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 395 | prot &= ~PAGE_WRITE; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 396 | } |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 397 | /* |
| 398 | * A load is permitted if the AMR bit is 0. Remove read |
| 399 | * protection if it is set. |
| 400 | */ |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 401 | if (amrbits & 0x1) { |
Cédric Le Goater | 363248e | 2014-02-04 18:21:39 +0100 | [diff] [blame] | 402 | prot &= ~PAGE_READ; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 403 | } |
| 404 | |
Suraj Jitindar Singh | a6152b5 | 2017-03-01 18:12:52 +1100 | [diff] [blame] | 405 | switch (env->mmu_model) { |
| 406 | /* |
| 407 | * MMU version 2.07 and later support IAMR |
| 408 | * Check if the IAMR allows the instruction access - it will return |
| 409 | * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0 |
| 410 | * if it does (and prot will be unchanged indicating execution support). |
| 411 | */ |
| 412 | case POWERPC_MMU_2_07: |
| 413 | case POWERPC_MMU_3_00: |
| 414 | prot &= ppc_hash64_iamr_prot(cpu, key); |
| 415 | break; |
| 416 | default: |
| 417 | break; |
| 418 | } |
| 419 | |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 420 | return prot; |
| 421 | } |
| 422 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 423 | const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, |
| 424 | hwaddr ptex, int n) |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 425 | { |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 426 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
Benjamin Herrenschmidt | 3367c62 | 2019-02-15 18:00:28 +0100 | [diff] [blame] | 427 | hwaddr base; |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 428 | hwaddr plen = n * HASH_PTE_SIZE_64; |
| 429 | const ppc_hash_pte64_t *hptes; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 430 | |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 431 | if (cpu->vhyp) { |
| 432 | PPCVirtualHypervisorClass *vhc = |
| 433 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); |
| 434 | return vhc->map_hptes(cpu->vhyp, ptex, n); |
| 435 | } |
Benjamin Herrenschmidt | 3367c62 | 2019-02-15 18:00:28 +0100 | [diff] [blame] | 436 | base = ppc_hash64_hpt_base(cpu); |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 437 | |
| 438 | if (!base) { |
| 439 | return NULL; |
| 440 | } |
| 441 | |
Peter Maydell | f26404f | 2018-05-31 14:50:52 +0100 | [diff] [blame] | 442 | hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, |
| 443 | MEMTXATTRS_UNSPECIFIED); |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 444 | if (plen < (n * HASH_PTE_SIZE_64)) { |
| 445 | hw_error("%s: Unable to map all requested HPTEs\n", __func__); |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 446 | } |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 447 | return hptes; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 448 | } |
| 449 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 450 | void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, |
| 451 | hwaddr ptex, int n) |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 452 | { |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 453 | if (cpu->vhyp) { |
| 454 | PPCVirtualHypervisorClass *vhc = |
| 455 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); |
| 456 | vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n); |
| 457 | return; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 458 | } |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 459 | |
| 460 | address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64, |
| 461 | false, n * HASH_PTE_SIZE_64); |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 462 | } |
| 463 | |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 464 | static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, |
| 465 | uint64_t pte0, uint64_t pte1) |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 466 | { |
David Gibson | 651060a | 2016-07-05 12:17:56 +1000 | [diff] [blame] | 467 | int i; |
| 468 | |
| 469 | if (!(pte0 & HPTE64_V_LARGE)) { |
| 470 | if (sps->page_shift != 12) { |
| 471 | /* 4kiB page in a non 4kiB segment */ |
| 472 | return 0; |
| 473 | } |
| 474 | /* Normal 4kiB page */ |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 475 | return 12; |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 476 | } |
David Gibson | 651060a | 2016-07-05 12:17:56 +1000 | [diff] [blame] | 477 | |
| 478 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 479 | const PPCHash64PageSize *ps = &sps->enc[i]; |
David Gibson | 651060a | 2016-07-05 12:17:56 +1000 | [diff] [blame] | 480 | uint64_t mask; |
| 481 | |
| 482 | if (!ps->page_shift) { |
| 483 | break; |
| 484 | } |
| 485 | |
| 486 | if (ps->page_shift == 12) { |
| 487 | /* L bit is set so this can't be a 4kiB page */ |
| 488 | continue; |
| 489 | } |
| 490 | |
| 491 | mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; |
| 492 | |
Paolo Bonzini | b56d417 | 2016-07-15 17:22:10 +0200 | [diff] [blame] | 493 | if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) { |
David Gibson | 651060a | 2016-07-05 12:17:56 +1000 | [diff] [blame] | 494 | return ps->page_shift; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | return 0; /* Bad page size encoding */ |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 499 | } |
| 500 | |
Benjamin Herrenschmidt | 3452559 | 2019-02-15 18:00:24 +0100 | [diff] [blame] | 501 | static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1) |
| 502 | { |
| 503 | /* Insert B into pte0 */ |
| 504 | *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) | |
| 505 | ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) << |
| 506 | (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT)); |
| 507 | |
| 508 | /* Remove B from pte1 */ |
| 509 | *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK; |
| 510 | } |
| 511 | |
| 512 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 513 | static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 514 | const PPCHash64SegmentPageSizes *sps, |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 515 | target_ulong ptem, |
David Gibson | 9498686 | 2016-07-05 12:31:57 +1000 | [diff] [blame] | 516 | ppc_hash_pte64_t *pte, unsigned *pshift) |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 517 | { |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 518 | int i; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 519 | const ppc_hash_pte64_t *pteg; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 520 | target_ulong pte0, pte1; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 521 | target_ulong ptex; |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 522 | |
David Gibson | 3677866 | 2017-02-24 16:36:44 +1100 | [diff] [blame] | 523 | ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 524 | pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
| 525 | if (!pteg) { |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 526 | return -1; |
| 527 | } |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 528 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 529 | pte0 = ppc_hash64_hpte0(cpu, pteg, i); |
Benjamin Herrenschmidt | 3054b0c | 2019-02-15 18:00:23 +0100 | [diff] [blame] | 530 | /* |
| 531 | * pte0 contains the valid bit and must be read before pte1, |
| 532 | * otherwise we might see an old pte1 with a new valid bit and |
| 533 | * thus an inconsistent hpte value |
| 534 | */ |
| 535 | smp_rmb(); |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 536 | pte1 = ppc_hash64_hpte1(cpu, pteg, i); |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 537 | |
Benjamin Herrenschmidt | 3452559 | 2019-02-15 18:00:24 +0100 | [diff] [blame] | 538 | /* Convert format if necessary */ |
| 539 | if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) { |
| 540 | ppc64_v3_new_to_old_hpte(&pte0, &pte1); |
| 541 | } |
| 542 | |
David Gibson | 073de86 | 2016-07-05 12:31:48 +1000 | [diff] [blame] | 543 | /* This compares V, B, H (secondary) and the AVPN */ |
| 544 | if (HPTE64_V_COMPARE(pte0, ptem)) { |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 545 | *pshift = hpte_page_shift(sps, pte0, pte1); |
David Gibson | 651060a | 2016-07-05 12:17:56 +1000 | [diff] [blame] | 546 | /* |
| 547 | * If there is no match, ignore the PTE, it could simply |
| 548 | * be for a different segment size encoding and the |
| 549 | * architecture specifies we should not match. Linux will |
| 550 | * potentially leave behind PTEs for the wrong base page |
| 551 | * size when demoting segments. |
| 552 | */ |
David Gibson | 9498686 | 2016-07-05 12:31:57 +1000 | [diff] [blame] | 553 | if (*pshift == 0) { |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 554 | continue; |
| 555 | } |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 556 | /* |
| 557 | * We don't do anything with pshift yet as qemu TLB only |
| 558 | * deals with 4K pages anyway |
Benjamin Herrenschmidt | 4322e8c | 2016-06-28 08:48:34 +0200 | [diff] [blame] | 559 | */ |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 560 | pte->pte0 = pte0; |
| 561 | pte->pte1 = pte1; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 562 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
| 563 | return ptex + i; |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 564 | } |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 565 | } |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 566 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 567 | /* |
| 568 | * We didn't find a valid entry. |
| 569 | */ |
David Gibson | aea390e | 2013-03-12 00:31:28 +0000 | [diff] [blame] | 570 | return -1; |
| 571 | } |
| 572 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 573 | static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 574 | ppc_slb_t *slb, target_ulong eaddr, |
David Gibson | 9498686 | 2016-07-05 12:31:57 +1000 | [diff] [blame] | 575 | ppc_hash_pte64_t *pte, unsigned *pshift) |
David Gibson | c69b615 | 2013-03-12 00:31:08 +0000 | [diff] [blame] | 576 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 577 | CPUPPCState *env = &cpu->env; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 578 | hwaddr hash, ptex; |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 579 | uint64_t vsid, epnmask, epn, ptem; |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 580 | const PPCHash64SegmentPageSizes *sps = slb->sps; |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 581 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 582 | /* |
| 583 | * The SLB store path should prevent any bad page size encodings |
| 584 | * getting in there, so: |
| 585 | */ |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 586 | assert(sps); |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 587 | |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 588 | /* If ISL is set in LPCR we need to clamp the page size to 4K */ |
| 589 | if (env->spr[SPR_LPCR] & LPCR_ISL) { |
| 590 | /* We assume that when using TCG, 4k is first entry of SPS */ |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 591 | sps = &cpu->hash64_opts->sps[0]; |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 592 | assert(sps->page_shift == 12); |
| 593 | } |
| 594 | |
| 595 | epnmask = ~((1ULL << sps->page_shift) - 1); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 596 | |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 597 | if (slb->vsid & SLB_VSID_B) { |
David Gibson | 1814889 | 2013-03-12 00:31:31 +0000 | [diff] [blame] | 598 | /* 1TB segment */ |
| 599 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; |
| 600 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 601 | hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 602 | } else { |
David Gibson | 1814889 | 2013-03-12 00:31:31 +0000 | [diff] [blame] | 603 | /* 256M segment */ |
| 604 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; |
| 605 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; |
Benjamin Herrenschmidt | 2c7ad80 | 2016-07-04 17:44:11 +1000 | [diff] [blame] | 606 | hash = vsid ^ (epn >> sps->page_shift); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 607 | } |
David Gibson | 1814889 | 2013-03-12 00:31:31 +0000 | [diff] [blame] | 608 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
David Gibson | 073de86 | 2016-07-05 12:31:48 +1000 | [diff] [blame] | 609 | ptem |= HPTE64_V_VALID; |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 610 | |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 611 | /* Page address translation */ |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 612 | qemu_log_mask(CPU_LOG_MMU, |
| 613 | "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 614 | " hash " TARGET_FMT_plx "\n", |
David Gibson | 3677866 | 2017-02-24 16:36:44 +1100 | [diff] [blame] | 615 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 616 | |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 617 | /* Primary PTEG lookup */ |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 618 | qemu_log_mask(CPU_LOG_MMU, |
| 619 | "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 620 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
| 621 | " hash=" TARGET_FMT_plx "\n", |
David Gibson | 3677866 | 2017-02-24 16:36:44 +1100 | [diff] [blame] | 622 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), |
| 623 | vsid, ptem, hash); |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 624 | ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 625 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 626 | if (ptex == -1) { |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 627 | /* Secondary PTEG lookup */ |
David Gibson | 073de86 | 2016-07-05 12:31:48 +1000 | [diff] [blame] | 628 | ptem |= HPTE64_V_SECONDARY; |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 629 | qemu_log_mask(CPU_LOG_MMU, |
| 630 | "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 631 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
David Gibson | 3677866 | 2017-02-24 16:36:44 +1100 | [diff] [blame] | 632 | " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), |
| 633 | ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 634 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 635 | ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); |
David Gibson | a1ff751 | 2013-03-12 00:31:29 +0000 | [diff] [blame] | 636 | } |
| 637 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 638 | return ptex; |
David Gibson | c69b615 | 2013-03-12 00:31:08 +0000 | [diff] [blame] | 639 | } |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 640 | |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 641 | unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, |
Cédric Le Goater | 1f0252e | 2016-07-01 09:10:10 +0200 | [diff] [blame] | 642 | uint64_t pte0, uint64_t pte1) |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 643 | { |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 644 | int i; |
| 645 | |
| 646 | if (!(pte0 & HPTE64_V_LARGE)) { |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 647 | return 12; |
| 648 | } |
| 649 | |
| 650 | /* |
| 651 | * The encodings in env->sps need to be carefully chosen so that |
| 652 | * this gives an unambiguous result. |
| 653 | */ |
| 654 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 655 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 656 | unsigned shift; |
| 657 | |
| 658 | if (!sps->page_shift) { |
| 659 | break; |
| 660 | } |
| 661 | |
| 662 | shift = hpte_page_shift(sps, pte0, pte1); |
| 663 | if (shift) { |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 664 | return shift; |
| 665 | } |
| 666 | } |
| 667 | |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 668 | return 0; |
| 669 | } |
| 670 | |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 671 | static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 672 | { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 673 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 674 | bool vpm; |
| 675 | |
| 676 | if (msr_ir) { |
| 677 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); |
| 678 | } else { |
Suraj Jitindar Singh | 5065908 | 2017-02-10 16:25:54 +1100 | [diff] [blame] | 679 | switch (env->mmu_model) { |
| 680 | case POWERPC_MMU_3_00: |
| 681 | /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ |
| 682 | vpm = true; |
| 683 | break; |
| 684 | default: |
| 685 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); |
| 686 | break; |
| 687 | } |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 688 | } |
| 689 | if (vpm && !msr_hv) { |
| 690 | cs->exception_index = POWERPC_EXCP_HISI; |
| 691 | } else { |
| 692 | cs->exception_index = POWERPC_EXCP_ISI; |
| 693 | } |
| 694 | env->error_code = error_code; |
| 695 | } |
| 696 | |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 697 | static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 698 | { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 699 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 700 | bool vpm; |
| 701 | |
| 702 | if (msr_dr) { |
| 703 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); |
| 704 | } else { |
Suraj Jitindar Singh | 5065908 | 2017-02-10 16:25:54 +1100 | [diff] [blame] | 705 | switch (env->mmu_model) { |
| 706 | case POWERPC_MMU_3_00: |
| 707 | /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ |
| 708 | vpm = true; |
| 709 | break; |
| 710 | default: |
| 711 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); |
| 712 | break; |
| 713 | } |
Benjamin Herrenschmidt | 33595dc | 2016-06-21 23:48:50 +0200 | [diff] [blame] | 714 | } |
| 715 | if (vpm && !msr_hv) { |
| 716 | cs->exception_index = POWERPC_EXCP_HDSI; |
| 717 | env->spr[SPR_HDAR] = dar; |
| 718 | env->spr[SPR_HDSISR] = dsisr; |
| 719 | } else { |
| 720 | cs->exception_index = POWERPC_EXCP_DSI; |
| 721 | env->spr[SPR_DAR] = dar; |
| 722 | env->spr[SPR_DSISR] = dsisr; |
| 723 | } |
| 724 | env->error_code = 0; |
| 725 | } |
| 726 | |
| 727 | |
Benjamin Herrenschmidt | a2dd4e8 | 2019-04-11 10:00:01 +0200 | [diff] [blame] | 728 | static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) |
| 729 | { |
| 730 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16; |
| 731 | |
| 732 | if (cpu->vhyp) { |
| 733 | PPCVirtualHypervisorClass *vhc = |
| 734 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); |
| 735 | vhc->hpte_set_r(cpu->vhyp, ptex, pte1); |
| 736 | return; |
| 737 | } |
| 738 | base = ppc_hash64_hpt_base(cpu); |
| 739 | |
| 740 | |
| 741 | /* The HW performs a non-atomic byte update */ |
| 742 | stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01); |
| 743 | } |
| 744 | |
| 745 | static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) |
| 746 | { |
| 747 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15; |
| 748 | |
| 749 | if (cpu->vhyp) { |
| 750 | PPCVirtualHypervisorClass *vhc = |
| 751 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); |
| 752 | vhc->hpte_set_c(cpu->vhyp, ptex, pte1); |
| 753 | return; |
| 754 | } |
| 755 | base = ppc_hash64_hpt_base(cpu); |
| 756 | |
| 757 | /* The HW performs a non-atomic byte update */ |
| 758 | stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); |
| 759 | } |
| 760 | |
Paolo Bonzini | b230560 | 2016-03-15 15:12:16 +0100 | [diff] [blame] | 761 | int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 762 | int rwx, int mmu_idx) |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 763 | { |
Andreas Färber | d0e39c5 | 2013-09-02 14:14:24 +0200 | [diff] [blame] | 764 | CPUState *cs = CPU(cpu); |
| 765 | CPUPPCState *env = &cpu->env; |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 766 | ppc_slb_t *slb; |
David Gibson | be18b2b | 2016-01-27 11:39:15 +1100 | [diff] [blame] | 767 | unsigned apshift; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 768 | hwaddr ptex; |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 769 | ppc_hash_pte64_t pte; |
Suraj Jitindar Singh | 07a68f9 | 2017-03-01 18:12:54 +1100 | [diff] [blame] | 770 | int exec_prot, pp_prot, amr_prot, prot; |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 771 | const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 772 | hwaddr raddr; |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 773 | |
David Gibson | 6a98011 | 2013-03-12 00:31:32 +0000 | [diff] [blame] | 774 | assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
| 775 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 776 | /* |
| 777 | * Note on LPCR usage: 970 uses HID4, but our special variant of |
| 778 | * store_spr copies relevant fields into env->spr[SPR_LPCR]. |
| 779 | * Similarily we filter unimplemented bits when storing into LPCR |
| 780 | * depending on the MMU version. This code can thus just use the |
| 781 | * LPCR "as-is". |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 782 | */ |
| 783 | |
David Gibson | 65d6164 | 2013-03-12 00:31:23 +0000 | [diff] [blame] | 784 | /* 1. Handle real mode accesses */ |
| 785 | if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 786 | /* |
| 787 | * Translation is supposedly "off", but in real mode the top 4 |
| 788 | * effective address bits are (mostly) ignored |
| 789 | */ |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 790 | raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 791 | |
| 792 | /* In HV mode, add HRMOR if top EA bit is clear */ |
| 793 | if (msr_hv || !env->has_hv_mode) { |
| 794 | if (!(eaddr >> 63)) { |
| 795 | raddr |= env->spr[SPR_HRMOR]; |
| 796 | } |
| 797 | } else { |
| 798 | /* Otherwise, check VPM for RMA vs VRMA */ |
| 799 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { |
| 800 | slb = &env->vrma_slb; |
| 801 | if (slb->sps) { |
| 802 | goto skip_slb_search; |
| 803 | } |
| 804 | /* Not much else to do here */ |
| 805 | cs->exception_index = POWERPC_EXCP_MCHECK; |
| 806 | env->error_code = 0; |
| 807 | return 1; |
| 808 | } else if (raddr < env->rmls) { |
| 809 | /* RMA. Check bounds in RMLS */ |
| 810 | raddr |= env->spr[SPR_RMOR]; |
| 811 | } else { |
| 812 | /* The access failed, generate the approriate interrupt */ |
| 813 | if (rwx == 2) { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 814 | ppc_hash64_set_isi(cs, SRR1_PROTFAULT); |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 815 | } else { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 816 | int dsisr = DSISR_PROTFAULT; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 817 | if (rwx == 1) { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 818 | dsisr |= DSISR_ISSTORE; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 819 | } |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 820 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 821 | } |
| 822 | return 1; |
| 823 | } |
| 824 | } |
Andreas Färber | 0c591eb | 2013-09-03 13:59:37 +0200 | [diff] [blame] | 825 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 826 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, |
| 827 | TARGET_PAGE_SIZE); |
David Gibson | 65d6164 | 2013-03-12 00:31:23 +0000 | [diff] [blame] | 828 | return 0; |
| 829 | } |
| 830 | |
David Gibson | bb21804 | 2013-03-12 00:31:26 +0000 | [diff] [blame] | 831 | /* 2. Translation is on, so look up the SLB */ |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 832 | slb = slb_lookup(cpu, eaddr); |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 833 | if (!slb) { |
Suraj Jitindar Singh | b289949 | 2017-03-01 17:54:38 +1100 | [diff] [blame] | 834 | /* No entry found, check if in-memory segment tables are in use */ |
David Gibson | ca79b3b | 2018-03-23 16:42:45 +1100 | [diff] [blame] | 835 | if (ppc64_use_proc_tbl(cpu)) { |
Suraj Jitindar Singh | b289949 | 2017-03-01 17:54:38 +1100 | [diff] [blame] | 836 | /* TODO - Unsupported */ |
| 837 | error_report("Segment Table Support Unimplemented"); |
| 838 | exit(1); |
| 839 | } |
| 840 | /* Segment still not found, generate the appropriate interrupt */ |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 841 | if (rwx == 2) { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 842 | cs->exception_index = POWERPC_EXCP_ISEG; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 843 | env->error_code = 0; |
| 844 | } else { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 845 | cs->exception_index = POWERPC_EXCP_DSEG; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 846 | env->error_code = 0; |
| 847 | env->spr[SPR_DAR] = eaddr; |
| 848 | } |
| 849 | return 1; |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 850 | } |
| 851 | |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 852 | skip_slb_search: |
| 853 | |
David Gibson | bb21804 | 2013-03-12 00:31:26 +0000 | [diff] [blame] | 854 | /* 3. Check for segment level no-execute violation */ |
| 855 | if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 856 | ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 857 | return 1; |
David Gibson | bb21804 | 2013-03-12 00:31:26 +0000 | [diff] [blame] | 858 | } |
| 859 | |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 860 | /* 4. Locate the PTE in the hash table */ |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 861 | ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); |
| 862 | if (ptex == -1) { |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 863 | if (rwx == 2) { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 864 | ppc_hash64_set_isi(cs, SRR1_NOPTE); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 865 | } else { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 866 | int dsisr = DSISR_NOPTE; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 867 | if (rwx == 1) { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 868 | dsisr |= DSISR_ISSTORE; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 869 | } |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 870 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 871 | } |
| 872 | return 1; |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 873 | } |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 874 | qemu_log_mask(CPU_LOG_MMU, |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 875 | "found PTE at index %08" HWADDR_PRIx "\n", ptex); |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 876 | |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 877 | /* 5. Check access permissions */ |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 878 | |
Suraj Jitindar Singh | 07a68f9 | 2017-03-01 18:12:54 +1100 | [diff] [blame] | 879 | exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 880 | pp_prot = ppc_hash64_pte_prot(cpu, slb, pte); |
| 881 | amr_prot = ppc_hash64_amr_prot(cpu, pte); |
Suraj Jitindar Singh | 07a68f9 | 2017-03-01 18:12:54 +1100 | [diff] [blame] | 882 | prot = exec_prot & pp_prot & amr_prot; |
David Gibson | 6a98011 | 2013-03-12 00:31:32 +0000 | [diff] [blame] | 883 | |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 884 | if ((need_prot[rwx] & ~prot) != 0) { |
David Gibson | 6a98011 | 2013-03-12 00:31:32 +0000 | [diff] [blame] | 885 | /* Access right violation */ |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 886 | qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 887 | if (rwx == 2) { |
Suraj Jitindar Singh | a6152b5 | 2017-03-01 18:12:52 +1100 | [diff] [blame] | 888 | int srr1 = 0; |
Suraj Jitindar Singh | 07a68f9 | 2017-03-01 18:12:54 +1100 | [diff] [blame] | 889 | if (PAGE_EXEC & ~exec_prot) { |
| 890 | srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ |
| 891 | } else if (PAGE_EXEC & ~pp_prot) { |
Suraj Jitindar Singh | a6152b5 | 2017-03-01 18:12:52 +1100 | [diff] [blame] | 892 | srr1 |= SRR1_PROTFAULT; /* Access violates access authority */ |
| 893 | } |
| 894 | if (PAGE_EXEC & ~amr_prot) { |
| 895 | srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */ |
| 896 | } |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 897 | ppc_hash64_set_isi(cs, srr1); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 898 | } else { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 899 | int dsisr = 0; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 900 | if (need_prot[rwx] & ~pp_prot) { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 901 | dsisr |= DSISR_PROTFAULT; |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 902 | } |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 903 | if (rwx == 1) { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 904 | dsisr |= DSISR_ISSTORE; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 905 | } |
| 906 | if (need_prot[rwx] & ~amr_prot) { |
Suraj Jitindar Singh | da82c73 | 2017-03-01 18:12:55 +1100 | [diff] [blame] | 907 | dsisr |= DSISR_AMR; |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 908 | } |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 909 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 910 | } |
| 911 | return 1; |
David Gibson | 6a98011 | 2013-03-12 00:31:32 +0000 | [diff] [blame] | 912 | } |
| 913 | |
Antony Pavlov | 339aaf5 | 2014-12-13 19:48:18 +0300 | [diff] [blame] | 914 | qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); |
David Gibson | 87dc3fd | 2013-03-12 00:31:38 +0000 | [diff] [blame] | 915 | |
| 916 | /* 6. Update PTE referenced and changed bits if necessary */ |
| 917 | |
Benjamin Herrenschmidt | a2dd4e8 | 2019-04-11 10:00:01 +0200 | [diff] [blame] | 918 | if (!(pte.pte1 & HPTE64_R_R)) { |
| 919 | ppc_hash64_set_r(cpu, ptex, pte.pte1); |
David Gibson | b344074 | 2013-03-12 00:31:42 +0000 | [diff] [blame] | 920 | } |
Benjamin Herrenschmidt | a2dd4e8 | 2019-04-11 10:00:01 +0200 | [diff] [blame] | 921 | if (!(pte.pte1 & HPTE64_R_C)) { |
| 922 | if (rwx == 1) { |
| 923 | ppc_hash64_set_c(cpu, ptex, pte.pte1); |
| 924 | } else { |
| 925 | /* |
| 926 | * Treat the page as read-only for now, so that a later write |
| 927 | * will pass through this function again to set the C bit |
| 928 | */ |
| 929 | prot &= ~PAGE_WRITE; |
| 930 | } |
David Gibson | 7f3bdc2 | 2013-03-12 00:31:30 +0000 | [diff] [blame] | 931 | } |
| 932 | |
David Gibson | 6d11d99 | 2013-03-12 00:31:43 +0000 | [diff] [blame] | 933 | /* 7. Determine the real address from the PTE */ |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 934 | |
David Gibson | be18b2b | 2016-01-27 11:39:15 +1100 | [diff] [blame] | 935 | raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); |
David Gibson | caa597b | 2013-03-12 00:31:46 +0000 | [diff] [blame] | 936 | |
Andreas Färber | 0c591eb | 2013-09-03 13:59:37 +0200 | [diff] [blame] | 937 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
David Gibson | be18b2b | 2016-01-27 11:39:15 +1100 | [diff] [blame] | 938 | prot, mmu_idx, 1ULL << apshift); |
David Gibson | 6d11d99 | 2013-03-12 00:31:43 +0000 | [diff] [blame] | 939 | |
David Gibson | e01b444 | 2013-03-12 00:31:40 +0000 | [diff] [blame] | 940 | return 0; |
David Gibson | 0480884 | 2013-03-12 00:31:09 +0000 | [diff] [blame] | 941 | } |
David Gibson | 629bd51 | 2013-03-12 00:31:11 +0000 | [diff] [blame] | 942 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 943 | hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) |
David Gibson | f2ad6be | 2013-03-12 00:31:13 +0000 | [diff] [blame] | 944 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 945 | CPUPPCState *env = &cpu->env; |
David Gibson | 5883d8b | 2013-03-12 00:31:45 +0000 | [diff] [blame] | 946 | ppc_slb_t *slb; |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 947 | hwaddr ptex, raddr; |
David Gibson | 5883d8b | 2013-03-12 00:31:45 +0000 | [diff] [blame] | 948 | ppc_hash_pte64_t pte; |
David Gibson | be18b2b | 2016-01-27 11:39:15 +1100 | [diff] [blame] | 949 | unsigned apshift; |
David Gibson | f2ad6be | 2013-03-12 00:31:13 +0000 | [diff] [blame] | 950 | |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 951 | /* Handle real mode */ |
David Gibson | 5883d8b | 2013-03-12 00:31:45 +0000 | [diff] [blame] | 952 | if (msr_dr == 0) { |
| 953 | /* In real mode the top 4 effective address bits are ignored */ |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 954 | raddr = addr & 0x0FFFFFFFFFFFFFFFULL; |
David Gibson | 5883d8b | 2013-03-12 00:31:45 +0000 | [diff] [blame] | 955 | |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 956 | /* In HV mode, add HRMOR if top EA bit is clear */ |
| 957 | if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { |
| 958 | return raddr | env->spr[SPR_HRMOR]; |
| 959 | } |
| 960 | |
| 961 | /* Otherwise, check VPM for RMA vs VRMA */ |
| 962 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { |
| 963 | slb = &env->vrma_slb; |
| 964 | if (!slb->sps) { |
| 965 | return -1; |
| 966 | } |
| 967 | } else if (raddr < env->rmls) { |
| 968 | /* RMA. Check bounds in RMLS */ |
| 969 | return raddr | env->spr[SPR_RMOR]; |
| 970 | } else { |
| 971 | return -1; |
| 972 | } |
| 973 | } else { |
| 974 | slb = slb_lookup(cpu, addr); |
| 975 | if (!slb) { |
| 976 | return -1; |
| 977 | } |
David Gibson | f2ad6be | 2013-03-12 00:31:13 +0000 | [diff] [blame] | 978 | } |
| 979 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 980 | ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); |
| 981 | if (ptex == -1) { |
David Gibson | 5883d8b | 2013-03-12 00:31:45 +0000 | [diff] [blame] | 982 | return -1; |
| 983 | } |
| 984 | |
David Gibson | be18b2b | 2016-01-27 11:39:15 +1100 | [diff] [blame] | 985 | return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) |
David Gibson | cd6a9bb | 2016-01-27 11:52:57 +1100 | [diff] [blame] | 986 | & TARGET_PAGE_MASK; |
David Gibson | f2ad6be | 2013-03-12 00:31:13 +0000 | [diff] [blame] | 987 | } |
Aneesh Kumar K.V | c138593 | 2014-02-20 18:52:38 +0100 | [diff] [blame] | 988 | |
David Gibson | 7222b94 | 2017-02-27 16:03:41 +1100 | [diff] [blame] | 989 | void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 990 | target_ulong pte0, target_ulong pte1) |
| 991 | { |
| 992 | /* |
| 993 | * XXX: given the fact that there are too many segments to |
| 994 | * invalidate, and we still don't have a tlb_flush_mask(env, n, |
| 995 | * mask) in QEMU, we just invalidate all TLBs |
| 996 | */ |
Nikunj A Dadhania | d76ab5e | 2016-09-20 22:05:01 +0530 | [diff] [blame] | 997 | cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 998 | } |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 999 | |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1000 | static void ppc_hash64_update_rmls(PowerPCCPU *cpu) |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1001 | { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 1002 | CPUPPCState *env = &cpu->env; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1003 | uint64_t lpcr = env->spr[SPR_LPCR]; |
| 1004 | |
| 1005 | /* |
| 1006 | * This is the full 4 bits encoding of POWER8. Previous |
| 1007 | * CPUs only support a subset of these but the filtering |
| 1008 | * is done when writing LPCR |
| 1009 | */ |
| 1010 | switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { |
| 1011 | case 0x8: /* 32MB */ |
| 1012 | env->rmls = 0x2000000ull; |
| 1013 | break; |
| 1014 | case 0x3: /* 64MB */ |
| 1015 | env->rmls = 0x4000000ull; |
| 1016 | break; |
| 1017 | case 0x7: /* 128MB */ |
| 1018 | env->rmls = 0x8000000ull; |
| 1019 | break; |
| 1020 | case 0x4: /* 256MB */ |
| 1021 | env->rmls = 0x10000000ull; |
| 1022 | break; |
| 1023 | case 0x2: /* 1GB */ |
| 1024 | env->rmls = 0x40000000ull; |
| 1025 | break; |
| 1026 | case 0x1: /* 16GB */ |
| 1027 | env->rmls = 0x400000000ull; |
| 1028 | break; |
| 1029 | default: |
| 1030 | /* What to do here ??? */ |
| 1031 | env->rmls = 0; |
| 1032 | } |
| 1033 | } |
| 1034 | |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1035 | static void ppc_hash64_update_vrma(PowerPCCPU *cpu) |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1036 | { |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 1037 | CPUPPCState *env = &cpu->env; |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1038 | const PPCHash64SegmentPageSizes *sps = NULL; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1039 | target_ulong esid, vsid, lpcr; |
| 1040 | ppc_slb_t *slb = &env->vrma_slb; |
| 1041 | uint32_t vrmasd; |
| 1042 | int i; |
| 1043 | |
| 1044 | /* First clear it */ |
| 1045 | slb->esid = slb->vsid = 0; |
| 1046 | slb->sps = NULL; |
| 1047 | |
| 1048 | /* Is VRMA enabled ? */ |
| 1049 | lpcr = env->spr[SPR_LPCR]; |
| 1050 | if (!(lpcr & LPCR_VPM0)) { |
| 1051 | return; |
| 1052 | } |
| 1053 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 1054 | /* |
| 1055 | * Make one up. Mostly ignore the ESID which will not be needed |
| 1056 | * for translation |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1057 | */ |
| 1058 | vsid = SLB_VSID_VRMA; |
| 1059 | vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; |
| 1060 | vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); |
| 1061 | esid = SLB_ESID_V; |
| 1062 | |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 1063 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1064 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
Benjamin Herrenschmidt | 912acdf | 2016-07-05 07:37:08 +1000 | [diff] [blame] | 1065 | |
| 1066 | if (!sps1->page_shift) { |
| 1067 | break; |
| 1068 | } |
| 1069 | |
| 1070 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { |
| 1071 | sps = sps1; |
| 1072 | break; |
| 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | if (!sps) { |
| 1077 | error_report("Bad page size encoding esid 0x"TARGET_FMT_lx |
| 1078 | " vsid 0x"TARGET_FMT_lx, esid, vsid); |
| 1079 | return; |
| 1080 | } |
| 1081 | |
| 1082 | slb->vsid = vsid; |
| 1083 | slb->esid = esid; |
| 1084 | slb->sps = sps; |
| 1085 | } |
| 1086 | |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1087 | void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1088 | { |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1089 | CPUPPCState *env = &cpu->env; |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1090 | uint64_t lpcr = 0; |
| 1091 | |
| 1092 | /* Filter out bits */ |
David Gibson | 0941d72 | 2018-03-23 16:48:43 +1100 | [diff] [blame] | 1093 | switch (env->mmu_model) { |
| 1094 | case POWERPC_MMU_64B: /* 970 */ |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1095 | if (val & 0x40) { |
| 1096 | lpcr |= LPCR_LPES0; |
| 1097 | } |
| 1098 | if (val & 0x8000000000000000ull) { |
| 1099 | lpcr |= LPCR_LPES1; |
| 1100 | } |
| 1101 | if (val & 0x20) { |
| 1102 | lpcr |= (0x4ull << LPCR_RMLS_SHIFT); |
| 1103 | } |
| 1104 | if (val & 0x4000000000000000ull) { |
| 1105 | lpcr |= (0x2ull << LPCR_RMLS_SHIFT); |
| 1106 | } |
| 1107 | if (val & 0x2000000000000000ull) { |
| 1108 | lpcr |= (0x1ull << LPCR_RMLS_SHIFT); |
| 1109 | } |
| 1110 | env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; |
| 1111 | |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 1112 | /* |
| 1113 | * XXX We could also write LPID from HID4 here |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1114 | * but since we don't tag any translation on it |
| 1115 | * it doesn't actually matter |
David Gibson | d75cbae | 2019-03-21 22:32:53 +1100 | [diff] [blame] | 1116 | * |
| 1117 | * XXX For proper emulation of 970 we also need |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1118 | * to dig HRMOR out of HID5 |
| 1119 | */ |
| 1120 | break; |
David Gibson | 0941d72 | 2018-03-23 16:48:43 +1100 | [diff] [blame] | 1121 | case POWERPC_MMU_2_03: /* P5p */ |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1122 | lpcr = val & (LPCR_RMLS | LPCR_ILE | |
| 1123 | LPCR_LPES0 | LPCR_LPES1 | |
| 1124 | LPCR_RMI | LPCR_HDICE); |
| 1125 | break; |
David Gibson | 0941d72 | 2018-03-23 16:48:43 +1100 | [diff] [blame] | 1126 | case POWERPC_MMU_2_06: /* P7 */ |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1127 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | |
| 1128 | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | |
| 1129 | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | |
| 1130 | LPCR_MER | LPCR_TC | |
| 1131 | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); |
| 1132 | break; |
David Gibson | 0941d72 | 2018-03-23 16:48:43 +1100 | [diff] [blame] | 1133 | case POWERPC_MMU_2_07: /* P8 */ |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1134 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | |
| 1135 | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | |
| 1136 | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | |
| 1137 | LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | |
| 1138 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); |
| 1139 | break; |
David Gibson | 0941d72 | 2018-03-23 16:48:43 +1100 | [diff] [blame] | 1140 | case POWERPC_MMU_3_00: /* P9 */ |
Suraj Jitindar Singh | 18aa49e | 2017-02-10 16:25:53 +1100 | [diff] [blame] | 1141 | lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | |
| 1142 | (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | |
Suraj Jitindar Singh | a8dafa5 | 2019-03-01 13:43:15 +1100 | [diff] [blame] | 1143 | LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | |
Suraj Jitindar Singh | 18aa49e | 2017-02-10 16:25:53 +1100 | [diff] [blame] | 1144 | (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | |
| 1145 | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | |
| 1146 | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); |
Benjamin Herrenschmidt | 2b9e0a6 | 2019-02-15 18:00:20 +0100 | [diff] [blame] | 1147 | /* |
| 1148 | * If we have a virtual hypervisor, we need to bring back RMLS. It |
| 1149 | * doesn't exist on an actual P9 but that's all we know how to |
| 1150 | * configure with softmmu at the moment |
| 1151 | */ |
| 1152 | if (cpu->vhyp) { |
| 1153 | lpcr |= (val & LPCR_RMLS); |
| 1154 | } |
Suraj Jitindar Singh | 18aa49e | 2017-02-10 16:25:53 +1100 | [diff] [blame] | 1155 | break; |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1156 | default: |
| 1157 | ; |
| 1158 | } |
| 1159 | env->spr[SPR_LPCR] = lpcr; |
David Gibson | 8fe08fa | 2018-03-22 16:49:28 +1100 | [diff] [blame] | 1160 | ppc_hash64_update_rmls(cpu); |
| 1161 | ppc_hash64_update_vrma(cpu); |
Benjamin Herrenschmidt | 4b3fc37 | 2016-06-27 08:55:16 +0200 | [diff] [blame] | 1162 | } |
David Gibson | a059471 | 2018-03-23 13:07:48 +1100 | [diff] [blame] | 1163 | |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1164 | void helper_store_lpcr(CPUPPCState *env, target_ulong val) |
| 1165 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 1166 | PowerPCCPU *cpu = env_archcpu(env); |
David Gibson | 5ad5531 | 2018-04-05 16:43:59 +1000 | [diff] [blame] | 1167 | |
| 1168 | ppc_store_lpcr(cpu, val); |
| 1169 | } |
| 1170 | |
David Gibson | a059471 | 2018-03-23 13:07:48 +1100 | [diff] [blame] | 1171 | void ppc_hash64_init(PowerPCCPU *cpu) |
| 1172 | { |
| 1173 | CPUPPCState *env = &cpu->env; |
| 1174 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 1175 | |
David Gibson | 21e405f | 2018-03-23 13:59:20 +1100 | [diff] [blame] | 1176 | if (!pcc->hash64_opts) { |
| 1177 | assert(!(env->mmu_model & POWERPC_MMU_64)); |
| 1178 | return; |
David Gibson | a059471 | 2018-03-23 13:07:48 +1100 | [diff] [blame] | 1179 | } |
David Gibson | 21e405f | 2018-03-23 13:59:20 +1100 | [diff] [blame] | 1180 | |
| 1181 | cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts)); |
David Gibson | a059471 | 2018-03-23 13:07:48 +1100 | [diff] [blame] | 1182 | } |
| 1183 | |
| 1184 | void ppc_hash64_finalize(PowerPCCPU *cpu) |
| 1185 | { |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1186 | g_free(cpu->hash64_opts); |
David Gibson | a059471 | 2018-03-23 13:07:48 +1100 | [diff] [blame] | 1187 | } |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1188 | |
David Gibson | 21e405f | 2018-03-23 13:59:20 +1100 | [diff] [blame] | 1189 | const PPCHash64Options ppc_hash64_opts_basic = { |
David Gibson | 58969ee | 2018-03-23 14:11:07 +1100 | [diff] [blame] | 1190 | .flags = 0, |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 1191 | .slb_size = 64, |
David Gibson | 21e405f | 2018-03-23 13:59:20 +1100 | [diff] [blame] | 1192 | .sps = { |
| 1193 | { .page_shift = 12, /* 4K */ |
| 1194 | .slb_enc = 0, |
| 1195 | .enc = { { .page_shift = 12, .pte_enc = 0 } } |
| 1196 | }, |
| 1197 | { .page_shift = 24, /* 16M */ |
| 1198 | .slb_enc = 0x100, |
| 1199 | .enc = { { .page_shift = 24, .pte_enc = 0 } } |
| 1200 | }, |
| 1201 | }, |
| 1202 | }; |
| 1203 | |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1204 | const PPCHash64Options ppc_hash64_opts_POWER7 = { |
David Gibson | 26cd35b | 2018-03-23 14:32:48 +1100 | [diff] [blame] | 1205 | .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, |
David Gibson | 67d7d66 | 2018-03-29 18:29:38 +1100 | [diff] [blame] | 1206 | .slb_size = 32, |
David Gibson | b07c59f | 2018-03-23 13:31:52 +1100 | [diff] [blame] | 1207 | .sps = { |
| 1208 | { |
| 1209 | .page_shift = 12, /* 4K */ |
| 1210 | .slb_enc = 0, |
| 1211 | .enc = { { .page_shift = 12, .pte_enc = 0 }, |
| 1212 | { .page_shift = 16, .pte_enc = 0x7 }, |
| 1213 | { .page_shift = 24, .pte_enc = 0x38 }, }, |
| 1214 | }, |
| 1215 | { |
| 1216 | .page_shift = 16, /* 64K */ |
| 1217 | .slb_enc = SLB_VSID_64K, |
| 1218 | .enc = { { .page_shift = 16, .pte_enc = 0x1 }, |
| 1219 | { .page_shift = 24, .pte_enc = 0x8 }, }, |
| 1220 | }, |
| 1221 | { |
| 1222 | .page_shift = 24, /* 16M */ |
| 1223 | .slb_enc = SLB_VSID_16M, |
| 1224 | .enc = { { .page_shift = 24, .pte_enc = 0 }, }, |
| 1225 | }, |
| 1226 | { |
| 1227 | .page_shift = 34, /* 16G */ |
| 1228 | .slb_enc = SLB_VSID_16G, |
| 1229 | .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, |
| 1230 | }, |
| 1231 | } |
| 1232 | }; |
David Gibson | 27f00f0 | 2018-03-26 15:01:22 +1100 | [diff] [blame] | 1233 | |
| 1234 | void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, |
| 1235 | bool (*cb)(void *, uint32_t, uint32_t), |
| 1236 | void *opaque) |
| 1237 | { |
| 1238 | PPCHash64Options *opts = cpu->hash64_opts; |
| 1239 | int i; |
| 1240 | int n = 0; |
| 1241 | bool ci_largepage = false; |
| 1242 | |
| 1243 | assert(opts); |
| 1244 | |
| 1245 | n = 0; |
| 1246 | for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { |
| 1247 | PPCHash64SegmentPageSizes *sps = &opts->sps[i]; |
| 1248 | int j; |
| 1249 | int m = 0; |
| 1250 | |
| 1251 | assert(n <= i); |
| 1252 | |
| 1253 | if (!sps->page_shift) { |
| 1254 | break; |
| 1255 | } |
| 1256 | |
| 1257 | for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { |
| 1258 | PPCHash64PageSize *ps = &sps->enc[j]; |
| 1259 | |
| 1260 | assert(m <= j); |
| 1261 | if (!ps->page_shift) { |
| 1262 | break; |
| 1263 | } |
| 1264 | |
| 1265 | if (cb(opaque, sps->page_shift, ps->page_shift)) { |
| 1266 | if (ps->page_shift >= 16) { |
| 1267 | ci_largepage = true; |
| 1268 | } |
| 1269 | sps->enc[m++] = *ps; |
| 1270 | } |
| 1271 | } |
| 1272 | |
| 1273 | /* Clear rest of the row */ |
| 1274 | for (j = m; j < ARRAY_SIZE(sps->enc); j++) { |
| 1275 | memset(&sps->enc[j], 0, sizeof(sps->enc[j])); |
| 1276 | } |
| 1277 | |
| 1278 | if (m) { |
| 1279 | n++; |
| 1280 | } |
| 1281 | } |
| 1282 | |
| 1283 | /* Clear the rest of the table */ |
| 1284 | for (i = n; i < ARRAY_SIZE(opts->sps); i++) { |
| 1285 | memset(&opts->sps[i], 0, sizeof(opts->sps[i])); |
| 1286 | } |
| 1287 | |
| 1288 | if (!ci_largepage) { |
| 1289 | opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; |
| 1290 | } |
| 1291 | } |