commit 18aa49ecf40b002dcaad9ea5491923358f512e72
author Suraj Jitindar Singh <sjitindarsingh@gmail.com> Fri Feb 10 16:25:53 2017 +1100
committer David Gibson <david@gibson.dropbear.id.au> Wed Feb 22 11:28:28 2017 +1100
tree 6ff763f81592c18436b7bf50be21a6ecfbea1336
parent 86cf1e9fe852e5c322968c2c708a7efa8b7be5d9

target/ppc/POWER9: Adapt LPCR handling for POWER9

The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

target/ppc/mmu-hash64.c

diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 2791f29..c09255d 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1062,6 +1062,14 @@
                       LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
                       LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
         break;
+    case POWERPC_MMU_3_00: /* P9 */
+        lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+                      (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+                      LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
+                      (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+                      LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
+                      LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
+        break;
     default:
         ;
     }