ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory from DTB

This commit adds support for bringing up the SSP and TSP co-processors
on AST2700. The initialization and control logic are performed via SCU
register programming. Memory layout for firmware regions is retrieved
from reserved-memory nodes in the SPL device tree.

Features included:

- Add find_fmc_image() to locate FMC v2 image and extract payload range.
- Load and validate SPL DTB located after FMC payload.
- Parse reserved-memory nodes for SSP, TSP, ATF, OP-TEE, and IPC regions.
- Define struct mem_region and reserved_mem_info for memory layout data.
- Implement ssp_init() and ssp_enable() for SSP SCU setup and launch.
- Implement tsp_init() and tsp_enable() for TSP SCU setup and launch.
- Extend load_other_fit_images() to detect "sspfw" and "tspfw" images.
- Enable SSP/TSP after loading firmware from FIT image.
- Add SCU register definitions in struct ast2700_scu0.

Note: DTB is only used to retrieve memory layout for reserved regions.
The SSP and TSP initialization and activation are done via SCU registers.

Code adapted from:
https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/board/aspeed/ibex_ast2700/ssp_tsp.c

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
8 files changed
tree: a44fdfa838ed794fb004d7b9505771d11af0e2cb
  1. ast27x0/
  2. lib/
  3. npcm7xx/
  4. npcm8xx/
  5. .gitignore
  6. CONTRIBUTING.md
  7. LICENSE
  8. README.md
README.md

Virtual Boot ROM for NPCM and ASPEED SoCs

This repository contains simple Boot ROMs for Nuvoton and ASPEED based BMC images that are intended to be used by QEMU when emulating NPCM and ASPEED based machines.

Subdirectories

npcm7xx: This subdir contains Boot ROM for NPCM7XX, a 32-bit ARM image. npcm8xx: This subdir contains Boot ROM for NPCM8XX, a 64-bit ARM image. ast27x0: This subdir contains Boot ROM for AST27X0, a 64-bit ARM image.