| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2024 NXP |
| */ |
| |
| #ifndef __IMX93_QSB_H |
| #define __IMX93_QSB_H |
| |
| #define CFG_SYS_UBOOT_BASE \ |
| (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| |
| #ifdef CONFIG_SPL_BUILD |
| #define CFG_MALLOC_F_ADDR 0x204D0000 |
| #endif |
| |
| #define CFG_SYS_INIT_RAM_ADDR 0x80000000 |
| #define CFG_SYS_INIT_RAM_SIZE 0x200000 |
| |
| #define CFG_SYS_SDRAM_BASE 0x80000000 |
| #define PHYS_SDRAM 0x80000000 |
| #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ |
| |
| #define WDOG_BASE_ADDR WDG3_BASE_ADDR |
| |
| #endif |
