blob: 19662be6fc6e16ff3f91bb6306329953b29bd921 [file] [log] [blame]
.. SPDX-License-Identifier: GPL-2.0+
ARM64
=====
Summary
-------
The initial arm64 U-Boot port was developed before hardware was available,
so the first supported platforms were the Foundation and Fast Model for ARMv8.
These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
embedded development boards to servers.
Notes
-----
1. U-Boot can run at any exception level it is entered in, it is
recommened to enter it in EL3 if U-Boot takes some responsibilities of a
classical firmware (like initial hardware setup, CPU errata workarounds
or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
that of a boot loader. It can drop to lower exception levels before
entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this
architecture there is no S-EL3.
2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
is used to encode the initial addend of rela to u-boot.bin. After running,
the U-Boot will be relocated to destination again.
3. Earlier Linux kernel versions required the FDT to be placed at a
2 MB boundary and within the same 512 MB section as the kernel image,
resulting in fdt_high to be defined specially.
Since kernel version 4.2 Linux is more relaxed about the DT location, so it
can be placed anywhere in memory.
Please reference linux/Documentation/arm64/booting.txt for detail.
4. Spin-table is used to wake up secondary processors. One location
(or per processor location) is defined to hold the kernel entry point
for secondary processors. It must be ensured that the location is
accessible and zero immediately after secondary processor
enter slave_cpu branch execution in start.S. The location address
is encoded in cpu node of DTS. Linux kernel store the entry point
of secondary processors to it and send event to wakeup secondary
processors.
Please reference linux/Documentation/arm64/booting.txt for detail.
5. Generic board is supported.
6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
aarch32 specific codes.
MMU
---
U-Boot uses a simple page table for MMU setup. It uses the smallest number of bits
possible for the virtual address based on the maximum memory address (see the logic
in ``get_tcr()``). If this is less than 39 bits, the MMU will use only 3 levels for
address translation.
As with all platforms, U-Boot on ARM64 uses a 1:1 mapping of virtual to physical addresses.
In general, the memory map is expected to remain static once the MMU is enabled.
Software pagetable walker
^^^^^^^^^^^^^^^^^^^^^^^^^
It is possible to debug the pagetable generated by U-Boot with the built in
``dump_pagetable()`` and ``walk_pagetable()`` functions (the former being a simple
wrapper for the latter). For example the following can be added to ``setup_all_pgtables()``
after the first call to ``setup_pgtables()``:
.. code-block:: c
dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL));
.. kernel-doc:: arch/arm/cpu/armv8/cache_v8.c
:identifiers: __pagetable_walk pagetable_print_entry
The pagetable walker can be used as follows:
.. kernel-doc:: arch/arm/include/asm/armv8/mmu.h
:identifiers: pte_walker_cb_t walk_pagetable dump_pagetable
This will result in a print like the following:
.. code-block:: text
Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels
[0x17df91000] | Table | |
[0x17df92000] | Table | |
[0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable
[0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable
[0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable
[0x080000000 - 0x140000000] | Block | Normal | Inner-shareable
[0x17df93000] | Table | |
[0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable
[0x17df94000] | Table | |
[0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable
For more information, please refer to the additional function documentation in
``arch/arm/include/asm/armv8/mmu.h``.
Contributors
------------
* Tom Rini <trini@ti.com>
* Scott Wood <scottwood@freescale.com>
* York Sun <yorksun@freescale.com>
* Simon Glass <sjg@chromium.org>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
* Rob Herring <robherring2@gmail.com>
* Sergey Temerkhanov <s.temerkhanov@gmail.com>