| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra124 xHCI controller |
| |
| maintainers: |
| - Thierry Reding <thierry.reding@gmail.com> |
| - Jon Hunter <jonathanh@nvidia.com> |
| |
| description: The Tegra xHCI controller supports both USB2 and USB3 interfaces |
| exposed by the Tegra XUSB pad controller. |
| |
| properties: |
| # required |
| compatible: |
| oneOf: |
| - description: NVIDIA Tegra124 |
| const: nvidia,tegra124-xusb |
| |
| - description: NVIDIA Tegra132 |
| items: |
| - const: nvidia,tegra132-xusb |
| - const: nvidia,tegra124-xusb |
| |
| reg: |
| items: |
| - description: base and length of the xHCI host registers |
| - description: base and length of the XUSB FPCI registers |
| - description: base and length of the XUSB IPFS registers |
| |
| reg-names: |
| items: |
| - const: hcd |
| - const: fpci |
| - const: ipfs |
| |
| interrupts: |
| items: |
| - description: xHCI host interrupt |
| - description: mailbox interrupt |
| |
| clocks: |
| items: |
| - description: XUSB host clock |
| - description: XUSB host source clock |
| - description: XUSB Falcon source clock |
| - description: XUSB SuperSpeed clock |
| - description: XUSB SuperSpeed clock divider |
| - description: XUSB SuperSpeed source clock |
| - description: XUSB HighSpeed clock source |
| - description: XUSB FullSpeed clock source |
| - description: USB PLL |
| - description: reference clock |
| - description: I/O PLL |
| |
| clock-names: |
| items: |
| - const: xusb_host |
| - const: xusb_host_src |
| - const: xusb_falcon_src |
| - const: xusb_ss |
| - const: xusb_ss_div2 |
| - const: xusb_ss_src |
| - const: xusb_hs_src |
| - const: xusb_fs_src |
| - const: pll_u_480m |
| - const: clk_m |
| - const: pll_e |
| |
| resets: |
| items: |
| - description: reset for the XUSB host controller |
| - description: reset for the SuperSpeed logic |
| - description: shared reset for xusb_{ss,hs,fs,falcon,host}_src. |
| |
| reset-names: |
| items: |
| - const: xusb_host |
| - const: xusb_ss |
| - const: xusb_src |
| |
| nvidia,xusb-padctl: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: phandle to the XUSB pad controller that is used to configure |
| the USB pads used by the XHCI controller |
| |
| # optional |
| phys: |
| minItems: 1 |
| maxItems: 7 |
| |
| phy-names: |
| minItems: 1 |
| maxItems: 7 |
| items: |
| enum: |
| - usb2-0 |
| - usb2-1 |
| - usb2-2 |
| - hsic-0 |
| - hsic-1 |
| - usb3-0 |
| - usb3-1 |
| |
| avddio-pex-supply: |
| description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. |
| |
| dvddio-pex-supply: |
| description: PCIe/USB3 digital logic power supply. Must supply 1.05 V. |
| |
| avdd-usb-supply: |
| description: USB controller power supply. Must supply 3.3 V. |
| |
| avdd-pll-utmip-supply: |
| description: UTMI PLL power supply. Must supply 1.8 V. |
| |
| avdd-pll-erefe-supply: |
| description: PLLE reference PLL power supply. Must supply 1.05 V. |
| |
| avdd-usb-ss-pll-supply: |
| description: PCIe/USB3 PLL power supply. Must supply 1.05 V. |
| |
| hvdd-usb-ss-supply: |
| description: High-voltage PCIe/USB3 power supply. Must supply 3.3 V. |
| |
| hvdd-usb-ss-pll-e-supply: |
| description: High-voltage PLLE power supply. Must supply 3.3 V. |
| |
| allOf: |
| - $ref: usb-xhci.yaml |
| |
| unevaluatedProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - reg-names |
| - interrupts |
| - clocks |
| - clock-names |
| - resets |
| - reset-names |
| - nvidia,xusb-padctl |
| - phys |
| - phy-names |
| - avddio-pex-supply |
| - dvddio-pex-supply |
| - avdd-usb-supply |
| - hvdd-usb-ss-supply |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/tegra124-car.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| usb@70090000 { |
| compatible = "nvidia,tegra124-xusb"; |
| reg = <0x70090000 0x8000>, |
| <0x70098000 0x1000>, |
| <0x70099000 0x1000>; |
| reg-names = "hcd", "fpci", "ipfs"; |
| |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, |
| <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, |
| <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, |
| <&tegra_car TEGRA124_CLK_XUSB_SS>, |
| <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, |
| <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, |
| <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, |
| <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, |
| <&tegra_car TEGRA124_CLK_PLL_U_480M>, |
| <&tegra_car TEGRA124_CLK_CLK_M>, |
| <&tegra_car TEGRA124_CLK_PLL_E>; |
| clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", |
| "xusb_ss", "xusb_ss_div2", "xusb_ss_src", |
| "xusb_hs_src", "xusb_fs_src", "pll_u_480m", |
| "clk_m", "pll_e"; |
| resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; |
| reset-names = "xusb_host", "xusb_ss", "xusb_src"; |
| |
| nvidia,xusb-padctl = <&padctl>; |
| |
| phys = <&phy_usb2_1>, <&phy_usb2_2>, <&phy_pcie_0>; |
| phy-names = "usb2-1", "usb2-2", "usb3-0"; |
| |
| avddio-pex-supply = <&vdd_1v05_run>; |
| dvddio-pex-supply = <&vdd_1v05_run>; |
| avdd-usb-supply = <&vdd_3v3_lp0>; |
| avdd-pll-utmip-supply = <&vddio_1v8>; |
| avdd-pll-erefe-supply = <&avdd_1v05_run>; |
| avdd-usb-ss-pll-supply = <&vdd_1v05_run>; |
| hvdd-usb-ss-supply = <&vdd_3v3_lp0>; |
| hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; |
| }; |