| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2018 Intel Corporation |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/reset/altr,rst-mgr-s10.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| compatible = "altr,socfpga-stratix10"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| reg = <0x0>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| reg = <0x1>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| reg = <0x2>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| reg = <0x3>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <0 120 8>, |
| <0 121 8>, |
| <0 122 8>, |
| <0 123 8>; |
| interrupt-affinity = <&cpu0>, |
| <&cpu1>, |
| <&cpu2>, |
| <&cpu3>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| intc: intc@fffc1000 { |
| compatible = "arm,gic-400", "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0xfffc1000 0x0 0x1000>, |
| <0x0 0xfffc2000 0x0 0x2000>, |
| <0x0 0xfffc4000 0x0 0x2000>, |
| <0x0 0xfffc6000 0x0 0x2000>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| device_type = "soc"; |
| interrupt-parent = <&intc>; |
| ranges = <0 0 0 0xffffffff>; |
| bootph-all; |
| |
| clkmgr: clkmgr@ffd10000 { |
| compatible = "altr,clk-mgr"; |
| reg = <0xffd10000 0x1000>; |
| }; |
| |
| gmac0: ethernet@ff800000 { |
| compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
| reg = <0xff800000 0x2000>; |
| interrupts = <0 90 4>; |
| interrupt-names = "macirq"; |
| mac-address = [00 00 00 00 00 00]; |
| resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; |
| reset-names = "stmmaceth"; |
| altr,sysmgr-syscon = <&sysmgr 0x44 0>; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@ff802000 { |
| compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
| reg = <0xff802000 0x2000>; |
| interrupts = <0 91 4>; |
| interrupt-names = "macirq"; |
| mac-address = [00 00 00 00 00 00]; |
| resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; |
| reset-names = "stmmaceth"; |
| altr,sysmgr-syscon = <&sysmgr 0x48 0>; |
| status = "disabled"; |
| }; |
| |
| gmac2: ethernet@ff804000 { |
| compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
| reg = <0xff804000 0x2000>; |
| interrupts = <0 92 4>; |
| interrupt-names = "macirq"; |
| mac-address = [00 00 00 00 00 00]; |
| resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; |
| reset-names = "stmmaceth"; |
| altr,sysmgr-syscon = <&sysmgr 0x4c 0>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@ffc03200 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0xffc03200 0x100>; |
| resets = <&rst GPIO0_RESET>; |
| status = "disabled"; |
| |
| porta: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <24>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <0 110 4>; |
| bank-name = "porta"; |
| }; |
| }; |
| |
| gpio1: gpio@ffc03300 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0xffc03300 0x100>; |
| resets = <&rst GPIO1_RESET>; |
| status = "disabled"; |
| |
| portb: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <24>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <0 111 4>; |
| bank-name = "portb"; |
| }; |
| }; |
| |
| i2c0: i2c@ffc02800 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc02800 0x100>; |
| interrupts = <0 103 4>; |
| resets = <&rst I2C0_RESET>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@ffc02900 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc02900 0x100>; |
| interrupts = <0 104 4>; |
| resets = <&rst I2C1_RESET>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@ffc02a00 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc02a00 0x100>; |
| interrupts = <0 105 4>; |
| resets = <&rst I2C2_RESET>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@ffc02b00 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc02b00 0x100>; |
| interrupts = <0 106 4>; |
| resets = <&rst I2C3_RESET>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@ffc02c00 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc02c00 0x100>; |
| interrupts = <0 107 4>; |
| resets = <&rst I2C4_RESET>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| mmc: dwmmc0@ff808000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "altr,socfpga-dw-mshc"; |
| reg = <0xff808000 0x1000>; |
| interrupts = <0 96 4>; |
| fifo-depth = <0x400>; |
| resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; |
| bootph-all; |
| status = "disabled"; |
| }; |
| |
| ocram: sram@ffe00000 { |
| compatible = "mmio-sram"; |
| reg = <0xffe00000 0x100000>; |
| }; |
| |
| qspi: spi@ff8d2000 { |
| compatible = "cdns,qspi-nor"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xff8d2000 0x100>, |
| <0xff900000 0x100000>; |
| interrupts = <0 3 4>; |
| cdns,fifo-depth = <128>; |
| cdns,fifo-width = <4>; |
| cdns,trigger-address = <0x00000000>; |
| status = "disabled"; |
| }; |
| |
| rst: rstmgr@ffd11000 { |
| #reset-cells = <1>; |
| compatible = "altr,rst-mgr"; |
| reg = <0xffd11000 0x1000>; |
| altr,modrst-offset = <0x20>; |
| bootph-all; |
| }; |
| |
| sdr: sdr@f8000400 { |
| compatible = "altr,sdr-ctl-s10"; |
| reg = <0xf8000400 0x80>, |
| <0xf8010000 0x190>, |
| <0xf8011000 0x500>; |
| resets = <&rst DDRSCH_RESET>; |
| bootph-all; |
| }; |
| |
| spi0: spi@ffda4000 { |
| compatible = "intel,stratix10-spi", |
| "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xffda4000 0x1000>; |
| interrupts = <0 99 4>; |
| resets = <&rst SPIM0_RESET>; |
| reg-io-width = <4>; |
| num-chipselect = <4>; |
| bus-num = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@ffda5000 { |
| compatible = "intel,stratix10-spi", |
| "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xffda5000 0x1000>; |
| interrupts = <0 100 4>; |
| resets = <&rst SPIM1_RESET>; |
| reg-io-width = <4>; |
| num-chipselect = <4>; |
| bus-num = <0>; |
| status = "disabled"; |
| }; |
| |
| sysmgr: sysmgr@ffd12000 { |
| compatible = "altr,sys-mgr", "syscon"; |
| reg = <0xffd12000 0x1000>; |
| }; |
| |
| /* Local timer */ |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 13 0xf08>, |
| <1 14 0xf08>, |
| <1 11 0xf08>, |
| <1 10 0xf08>; |
| }; |
| |
| timer0: timer0@ffc03000 { |
| compatible = "snps,dw-apb-timer"; |
| interrupts = <0 113 4>; |
| reg = <0xffc03000 0x100>; |
| }; |
| |
| timer1: timer1@ffc03100 { |
| compatible = "snps,dw-apb-timer"; |
| interrupts = <0 114 4>; |
| reg = <0xffc03100 0x100>; |
| }; |
| |
| timer2: timer2@ffd00000 { |
| compatible = "snps,dw-apb-timer"; |
| interrupts = <0 115 4>; |
| reg = <0xffd00000 0x100>; |
| }; |
| |
| timer3: timer3@ffd00100 { |
| compatible = "snps,dw-apb-timer"; |
| interrupts = <0 116 4>; |
| reg = <0xffd00100 0x100>; |
| }; |
| |
| uart0: serial0@ffc02000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0xffc02000 0x100>; |
| interrupts = <0 108 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| resets = <&rst UART0_RESET>; |
| clock-frequency = <100000000>; |
| bootph-all; |
| status = "disabled"; |
| }; |
| |
| uart1: serial1@ffc02100 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0xffc02100 0x100>; |
| interrupts = <0 109 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| resets = <&rst UART1_RESET>; |
| status = "disabled"; |
| }; |
| |
| usbphy0: usbphy@0 { |
| #phy-cells = <0>; |
| compatible = "usb-nop-xceiv"; |
| status = "okay"; |
| }; |
| |
| usb0: usb@ffb00000 { |
| compatible = "snps,dwc2"; |
| reg = <0xffb00000 0x40000>; |
| interrupts = <0 93 4>; |
| phys = <&usbphy0>; |
| phy-names = "usb2-phy"; |
| resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; |
| reset-names = "dwc2", "dwc2-ecc"; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@ffb40000 { |
| compatible = "snps,dwc2"; |
| reg = <0xffb40000 0x40000>; |
| interrupts = <0 94 4>; |
| phys = <&usbphy0>; |
| phy-names = "usb2-phy"; |
| resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; |
| reset-names = "dwc2", "dwc2-ecc"; |
| status = "disabled"; |
| }; |
| |
| watchdog0: watchdog@ffd00200 { |
| compatible = "snps,dw-wdt"; |
| reg = <0xffd00200 0x100>; |
| interrupts = <0 117 4>; |
| resets = <&rst WATCHDOG0_RESET>; |
| status = "disabled"; |
| }; |
| |
| watchdog1: watchdog@ffd00300 { |
| compatible = "snps,dw-wdt"; |
| reg = <0xffd00300 0x100>; |
| interrupts = <0 118 4>; |
| resets = <&rst WATCHDOG1_RESET>; |
| status = "disabled"; |
| }; |
| |
| watchdog2: watchdog@ffd00400 { |
| compatible = "snps,dw-wdt"; |
| reg = <0xffd00400 0x100>; |
| interrupts = <0 125 4>; |
| resets = <&rst WATCHDOG2_RESET>; |
| status = "disabled"; |
| }; |
| |
| watchdog3: watchdog@ffd00500 { |
| compatible = "snps,dw-wdt"; |
| reg = <0xffd00500 0x100>; |
| interrupts = <0 126 4>; |
| resets = <&rst WATCHDOG3_RESET>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
