| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * SoM: https://www.ti.com/lit/zip/sprr439 |
| * |
| * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| /dts-v1/; |
| |
| #include "k3-j721s2.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| memory@80000000 { |
| device_type = "memory"; |
| /* 16 GB RAM */ |
| reg = <0x00 0x80000000 0x00 0x80000000>, |
| <0x08 0x80000000 0x03 0x80000000>; |
| }; |
| |
| /* Reserving memory regions still pending */ |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| secure_ddr: optee@9e800000 { |
| reg = <0x00 0x9e800000 0x00 0x01800000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_memory_region: r5f-memory@a2100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_memory_region: r5f-memory@a3100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_memory_region: r5f-memory@a4100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_memory_region: r5f-memory@a5100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_0_dma_memory_region: c71-dma-memory@a6000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_0_memory_region: c71-memory@a6100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_1_dma_memory_region: c71-dma-memory@a7000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_1_memory_region: c71-memory@a7100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| rtos_ipc_memory_region: ipc-memories@a8000000 { |
| reg = <0x00 0xa8000000 0x00 0x01c00000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| }; |
| |
| mux0: mux-controller { |
| compatible = "gpio-mux"; |
| #mux-state-cells = <1>; |
| mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| mux1: mux-controller { |
| compatible = "gpio-mux"; |
| #mux-state-cells = <1>; |
| mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| transceiver0: can-phy0 { |
| /* standby pin has been grounded by default */ |
| compatible = "ti,tcan1042"; |
| #phy-cells = <0>; |
| max-bitrate = <5000000>; |
| }; |
| }; |
| |
| &wkup_pmx0 { |
| mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { |
| pinctrl-single,pins = < |
| J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ |
| J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ |
| J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ |
| J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ |
| J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ |
| J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ |
| J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ |
| J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ |
| J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ |
| J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ |
| J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ |
| J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ |
| >; |
| }; |
| }; |
| |
| &wkup_pmx2 { |
| wkup_i2c0_pins_default: wkup-i2c0-default-pins { |
| pinctrl-single,pins = < |
| J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ |
| J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ |
| >; |
| }; |
| }; |
| |
| &main_pmx0 { |
| main_i2c0_pins_default: main-i2c0-default-pins { |
| pinctrl-single,pins = < |
| J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ |
| J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ |
| >; |
| }; |
| |
| main_mcan16_pins_default: main-mcan16-default-pins { |
| pinctrl-single,pins = < |
| J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ |
| J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ |
| >; |
| }; |
| }; |
| |
| &wkup_i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| eeprom@50 { |
| /* CAV24C256WE-GT3 */ |
| compatible = "atmel,24c256"; |
| reg = <0x50>; |
| }; |
| }; |
| |
| &main_i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| exp_som: gpio@21 { |
| compatible = "ti,tca6408"; |
| reg = <0x21>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", |
| "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", |
| "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", |
| "GPIO_LIN_EN", "CAN_STB"; |
| }; |
| }; |
| |
| &main_mcan16 { |
| status = "okay"; |
| pinctrl-0 = <&main_mcan16_pins_default>; |
| pinctrl-names = "default"; |
| phys = <&transceiver0>; |
| }; |
| |
| &ospi0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| spi-max-frequency = <25000000>; |
| cdns,tshsl-ns = <60>; |
| cdns,tsd2d-ns = <60>; |
| cdns,tchsh-ns = <60>; |
| cdns,tslch-ns = <60>; |
| cdns,read-delay = <4>; |
| }; |
| }; |
| |
| &mailbox0_cluster0 { |
| status = "okay"; |
| interrupts = <436>; |
| mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster1 { |
| status = "okay"; |
| interrupts = <432>; |
| mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster2 { |
| status = "okay"; |
| interrupts = <428>; |
| mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster4 { |
| status = "okay"; |
| interrupts = <420>; |
| mbox_c71_0: mbox-c71-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c71_1: mbox-c71-1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mcu_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; |
| memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| <&mcu_r5fss0_core0_memory_region>; |
| }; |
| |
| &mcu_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; |
| memory-region = <&mcu_r5fss0_core1_dma_memory_region>, |
| <&mcu_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; |
| memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| <&main_r5fss0_core0_memory_region>; |
| }; |
| |
| &main_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; |
| memory-region = <&main_r5fss0_core1_dma_memory_region>, |
| <&main_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss1_core0 { |
| mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; |
| memory-region = <&main_r5fss1_core0_dma_memory_region>, |
| <&main_r5fss1_core0_memory_region>; |
| }; |
| |
| &main_r5fss1_core1 { |
| mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; |
| memory-region = <&main_r5fss1_core1_dma_memory_region>, |
| <&main_r5fss1_core1_memory_region>; |
| }; |
| |
| &c71_0 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; |
| memory-region = <&c71_0_dma_memory_region>, |
| <&c71_0_memory_region>; |
| }; |
| |
| &c71_1 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; |
| memory-region = <&c71_1_dma_memory_region>, |
| <&c71_1_memory_region>; |
| }; |
