| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (C) 2023 PHYTEC Messtechnik GmbH |
| * Christoph Stoidner <c.stoidner@phytec.de> |
| * |
| * Product homepage: |
| * phyBOARD-Segin carrier board is reused for the i.MX93 design. |
| * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ |
| */ |
| |
| #include "imx93-u-boot.dtsi" |
| |
| / { |
| wdt-reboot { |
| compatible = "wdt-reboot"; |
| wdt = <&wdog3>; |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| aliases { |
| ethernet0 = &fec; |
| ethernet1 = &eqos; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| }; |
| }; |
| |
| &{/soc@0} { |
| bootph-all; |
| bootph-pre-ram; |
| }; |
| |
| &aips1 { |
| bootph-pre-ram; |
| bootph-all; |
| }; |
| |
| &aips2 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &aips3 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &iomuxc { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| ®_usdhc2_vmmc { |
| u-boot,off-on-delay-us = <20000>; |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_reg_usdhc2_vmmc { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_uart1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_usdhc1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_usdhc2_cd { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_usdhc2_default { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_usdhc2_100mhz { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &pinctrl_usdhc2_200mhz { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &gpio1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &gpio2 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &gpio3 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &gpio4 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &lpuart1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| /* |
| * Remove once USB support is added to imx93-phyboard-segin.dts upstream. |
| */ |
| &usbotg1 { |
| disable-over-current; |
| dr_mode = "otg"; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| disable-over-current; |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &usdhc2 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| fsl,signal-voltage-switch-extra-delay-ms = <8>; |
| }; |
| |
| &lpi2c1 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &lpi2c2 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &lpi2c3 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| }; |
| |
| &s4muap { |
| bootph-pre-ram; |
| bootph-some-ram; |
| status = "okay"; |
| }; |
| |
| &clk { |
| bootph-all; |
| bootph-pre-ram; |
| /delete-property/ assigned-clocks; |
| /delete-property/ assigned-clock-rates; |
| /delete-property/ assigned-clock-parents; |
| }; |
| |
| &osc_32k { |
| bootph-all; |
| bootph-pre-ram; |
| }; |
| |
| &osc_24m { |
| bootph-all; |
| bootph-pre-ram; |
| }; |
| |
| &clk_ext1 { |
| bootph-all; |
| bootph-pre-ram; |
| }; |
| |
| &wdog3 { |
| bootph-all; |
| bootph-pre-ram; |
| }; |
| |
| /* |
| * The two nodes below won't be needed once nxp,pca9451a |
| * support is added to the Linux kernel. |
| */ |
| &iomuxc { |
| pinctrl_lpi2c3: lpi2c3grp { |
| bootph-pre-ram; |
| fsl,pins = < |
| MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e |
| MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| bootph-pre-ram; |
| fsl,pins = < |
| MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e |
| >; |
| }; |
| }; |
| |
| &lpi2c3 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_lpi2c3>; |
| pinctrl-1 = <&pinctrl_lpi2c3>; |
| status = "okay"; |
| |
| pmic@25 { |
| bootph-pre-ram; |
| bootph-some-ram; |
| compatible = "nxp,pca9451a"; |
| reg = <0x25>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <27 IRQ_TYPE_LEVEL_LOW>; |
| |
| regulators { |
| bootph-pre-ram; |
| bootph-some-ram; |
| buck1: BUCK1 { |
| regulator-name = "VDD_SOC"; |
| regulator-min-microvolt = <610000>; |
| regulator-max-microvolt = <950000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <3125>; |
| }; |
| |
| buck2: BUCK2 { |
| regulator-name = "VDDQ_0V6"; |
| regulator-min-microvolt = <600000>; |
| regulator-max-microvolt = <600000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck4: BUCK4 { |
| regulator-name = "VDD_3V3_BUCK"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck5: BUCK5 { |
| regulator-name = "VDD_1V8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck6: BUCK6 { |
| regulator-name = "VDD_1V1"; |
| regulator-min-microvolt = <1100000>; |
| regulator-max-microvolt = <1100000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1: LDO1 { |
| regulator-name = "PMIC_SNVS_1V8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4: LDO4 { |
| regulator-name = "VDD_0V8"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo5: LDO5 { |
| regulator-name = "NVCC_SD2"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
