| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2019, 2021 NXP |
| */ |
| |
| #include "imx8mp-u-boot.dtsi" |
| |
| / { |
| wdt-reboot { |
| compatible = "wdt-reboot"; |
| wdt = <&wdog1>; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &pinctrl_i2c1 { |
| bootph-all; |
| }; |
| |
| &pinctrl_pmic { |
| bootph-all; |
| }; |
| |
| &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { |
| bootph-all; |
| }; |
| |
| &{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { |
| bootph-all; |
| }; |
| |
| ®_usdhc2_vmmc { |
| u-boot,off-on-delay-us = <20000>; |
| }; |
| |
| ®_usdhc2_vmmc { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_uart2 { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_usdhc2_gpio { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_usdhc2 { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_usdhc3 { |
| bootph-pre-ram; |
| }; |
| |
| &pinctrl_wdog { |
| bootph-pre-ram; |
| }; |
| |
| &gpio1 { |
| bootph-pre-ram; |
| }; |
| |
| &gpio2 { |
| bootph-pre-ram; |
| }; |
| |
| &gpio3 { |
| bootph-pre-ram; |
| }; |
| |
| &gpio4 { |
| bootph-pre-ram; |
| }; |
| |
| &gpio5 { |
| bootph-pre-ram; |
| }; |
| |
| &uart2 { |
| bootph-pre-ram; |
| }; |
| |
| &i2c1 { |
| bootph-all; |
| }; |
| |
| &i2c2 { |
| bootph-pre-ram; |
| }; |
| |
| &i2c3 { |
| bootph-pre-ram; |
| }; |
| |
| &i2c4 { |
| bootph-pre-ram; |
| }; |
| |
| &i2c5 { |
| bootph-pre-ram; |
| }; |
| |
| &i2c6 { |
| bootph-pre-ram; |
| }; |
| |
| &usb_dwc3_0 { |
| dr_mode = "peripheral"; |
| status = "okay"; |
| }; |
| |
| &usb3_0 { |
| status = "okay"; |
| }; |
| |
| &usb3_phy0 { |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| bootph-pre-ram; |
| }; |
| |
| &usdhc2 { |
| bootph-pre-ram; |
| sd-uhs-sdr104; |
| sd-uhs-ddr50; |
| }; |
| |
| &usdhc3 { |
| bootph-pre-ram; |
| mmc-hs400-1_8v; |
| mmc-hs400-enhanced-strobe; |
| }; |
| |
| &wdog1 { |
| bootph-pre-ram; |
| }; |
