| /* |
| * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC |
| * |
| * Copyright (C) 2012 Atmel, |
| * 2012 Hong Xu <hong.xu@atmel.com> |
| * |
| * Licensed under GPLv2 or later. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/dma/at91.h> |
| #include <dt-bindings/pinctrl/at91.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/at91.h> |
| |
| / { |
| model = "Atmel AT91SAM9N12 SoC"; |
| compatible = "atmel,at91sam9n12"; |
| interrupt-parent = <&aic>; |
| |
| aliases { |
| serial0 = &dbgu; |
| serial1 = &usart0; |
| serial2 = &usart1; |
| serial3 = &usart2; |
| serial4 = &usart3; |
| gpio0 = &pioA; |
| gpio1 = &pioB; |
| gpio2 = &pioC; |
| gpio3 = &pioD; |
| tcb0 = &tcb0; |
| tcb1 = &tcb1; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| ssc0 = &ssc0; |
| pwm0 = &pwm0; |
| spi0 = &spi0; |
| }; |
| cpus { |
| cpu { |
| compatible = "arm,arm926ej-s"; |
| device_type = "cpu"; |
| }; |
| }; |
| |
| memory { |
| reg = <0x20000000 0x10000000>; |
| }; |
| |
| clocks { |
| slow_xtal: slow_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| main_xtal: main_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| }; |
| |
| sram: sram@00300000 { |
| compatible = "mmio-sram"; |
| reg = <0x00300000 0x8000>; |
| }; |
| |
| ahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| bootph-all; |
| |
| apb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| bootph-all; |
| |
| aic: interrupt-controller@fffff000 { |
| #interrupt-cells = <3>; |
| compatible = "atmel,at91rm9200-aic"; |
| interrupt-controller; |
| reg = <0xfffff000 0x200>; |
| atmel,external-irqs = <31>; |
| }; |
| |
| ramc0: ramc@ffffe800 { |
| compatible = "atmel,at91sam9g45-ddramc"; |
| reg = <0xffffe800 0x200>; |
| clocks = <&ddrck>; |
| clock-names = "ddrck"; |
| }; |
| |
| pmc: pmc@fffffc00 { |
| compatible = "atmel,at91sam9n12-pmc", "syscon"; |
| reg = <0xfffffc00 0x200>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| interrupt-controller; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| bootph-all; |
| |
| main_rc_osc: main_rc_osc { |
| compatible = "atmel,at91sam9x5-clk-main-rc-osc"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; |
| clock-frequency = <12000000>; |
| clock-accuracy = <50000000>; |
| }; |
| |
| main_osc: main_osc { |
| compatible = "atmel,at91rm9200-clk-main-osc"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_MOSCS>; |
| clocks = <&main_xtal>; |
| }; |
| |
| main: mainck { |
| compatible = "atmel,at91sam9x5-clk-main"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; |
| clocks = <&main_rc_osc>, <&main_osc>; |
| }; |
| |
| plla: pllack@0 { |
| compatible = "atmel,at91rm9200-clk-pll"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_LOCKA>; |
| clocks = <&main>; |
| reg = <0>; |
| atmel,clk-input-range = <2000000 32000000>; |
| #atmel,pll-clk-output-range-cells = <4>; |
| atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, |
| <695000000 750000000 1 0>, |
| <645000000 700000000 2 0>, |
| <595000000 650000000 3 0>, |
| <545000000 600000000 0 1>, |
| <495000000 555000000 1 1>, |
| <445000000 500000000 2 1>, |
| <400000000 450000000 3 1>; |
| }; |
| |
| plladiv: plladivck { |
| compatible = "atmel,at91sam9x5-clk-plldiv"; |
| #clock-cells = <0>; |
| clocks = <&plla>; |
| }; |
| |
| pllb: pllbck@1 { |
| compatible = "atmel,at91rm9200-clk-pll"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_LOCKB>; |
| clocks = <&main>; |
| reg = <1>; |
| atmel,clk-input-range = <2000000 32000000>; |
| #atmel,pll-clk-output-range-cells = <3>; |
| atmel,pll-clk-output-ranges = <30000000 100000000 0>; |
| }; |
| |
| mck: masterck { |
| compatible = "atmel,at91sam9x5-clk-master"; |
| #clock-cells = <0>; |
| interrupts-extended = <&pmc AT91_PMC_MCKRDY>; |
| clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; |
| atmel,clk-output-range = <0 133333333>; |
| atmel,clk-divisors = <1 2 4 3>; |
| atmel,master-clk-have-div3-pres; |
| bootph-all; |
| }; |
| |
| usb: usbck { |
| compatible = "atmel,at91sam9n12-clk-usb"; |
| #clock-cells = <0>; |
| clocks = <&pllb>; |
| }; |
| |
| prog: progck { |
| compatible = "atmel,at91sam9x5-clk-programmable"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupt-parent = <&pmc>; |
| clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; |
| |
| prog0: prog@0 { |
| #clock-cells = <0>; |
| reg = <0>; |
| interrupts = <AT91_PMC_PCKRDY(0)>; |
| }; |
| |
| prog1: prog@1 { |
| #clock-cells = <0>; |
| reg = <1>; |
| interrupts = <AT91_PMC_PCKRDY(1)>; |
| }; |
| }; |
| |
| systemck { |
| compatible = "atmel,at91rm9200-clk-system"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ddrck: ddrck@2 { |
| #clock-cells = <0>; |
| reg = <2>; |
| clocks = <&mck>; |
| }; |
| |
| lcdck: lcdck@3 { |
| #clock-cells = <0>; |
| reg = <3>; |
| clocks = <&mck>; |
| }; |
| |
| uhpck: uhpck@6 { |
| #clock-cells = <0>; |
| reg = <6>; |
| clocks = <&usb>; |
| }; |
| |
| udpck: udpck@7 { |
| #clock-cells = <0>; |
| reg = <7>; |
| clocks = <&usb>; |
| }; |
| |
| pck0: pck0@8 { |
| #clock-cells = <0>; |
| reg = <8>; |
| clocks = <&prog0>; |
| }; |
| |
| pck1: pck1@9 { |
| #clock-cells = <0>; |
| reg = <9>; |
| clocks = <&prog1>; |
| }; |
| }; |
| |
| periphck { |
| compatible = "atmel,at91sam9x5-clk-peripheral"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&mck>; |
| bootph-all; |
| |
| pioAB_clk: pioAB_clk@2 { |
| #clock-cells = <0>; |
| reg = <2>; |
| bootph-all; |
| }; |
| |
| pioCD_clk: pioCD_clk@3 { |
| #clock-cells = <0>; |
| reg = <3>; |
| bootph-all; |
| }; |
| |
| fuse_clk: fuse_clk@4 { |
| #clock-cells = <0>; |
| reg = <4>; |
| }; |
| |
| usart0_clk: usart0_clk@5 { |
| #clock-cells = <0>; |
| reg = <5>; |
| }; |
| |
| usart1_clk: usart1_clk@6 { |
| #clock-cells = <0>; |
| reg = <6>; |
| }; |
| |
| usart2_clk: usart2_clk@7 { |
| #clock-cells = <0>; |
| reg = <7>; |
| }; |
| |
| usart3_clk: usart3_clk@8 { |
| #clock-cells = <0>; |
| reg = <8>; |
| }; |
| |
| twi0_clk: twi0_clk@9 { |
| reg = <9>; |
| #clock-cells = <0>; |
| }; |
| |
| twi1_clk: twi1_clk@10 { |
| #clock-cells = <0>; |
| reg = <10>; |
| }; |
| |
| mci0_clk: mci0_clk@12 { |
| #clock-cells = <0>; |
| reg = <12>; |
| }; |
| |
| spi0_clk: spi0_clk@13 { |
| #clock-cells = <0>; |
| reg = <13>; |
| }; |
| |
| spi1_clk: spi1_clk@14 { |
| #clock-cells = <0>; |
| reg = <14>; |
| }; |
| |
| uart0_clk: uart0_clk@15 { |
| #clock-cells = <0>; |
| reg = <15>; |
| }; |
| |
| uart1_clk: uart1_clk@16 { |
| #clock-cells = <0>; |
| reg = <16>; |
| }; |
| |
| tcb_clk: tcb_clk@17 { |
| #clock-cells = <0>; |
| reg = <17>; |
| }; |
| |
| pwm_clk: pwm_clk@18 { |
| #clock-cells = <0>; |
| reg = <18>; |
| }; |
| |
| adc_clk: adc_clk@19 { |
| #clock-cells = <0>; |
| reg = <19>; |
| }; |
| |
| dma0_clk: dma0_clk@20 { |
| #clock-cells = <0>; |
| reg = <20>; |
| }; |
| |
| uhphs_clk: uhphs_clk@22 { |
| #clock-cells = <0>; |
| reg = <22>; |
| }; |
| |
| udphs_clk: udphs_clk@23 { |
| #clock-cells = <0>; |
| reg = <23>; |
| }; |
| |
| lcdc_clk: lcdc_clk@25 { |
| #clock-cells = <0>; |
| reg = <25>; |
| }; |
| |
| sha_clk: sha_clk@27 { |
| #clock-cells = <0>; |
| reg = <27>; |
| }; |
| |
| ssc0_clk: ssc0_clk@28 { |
| #clock-cells = <0>; |
| reg = <28>; |
| }; |
| |
| aes_clk: aes_clk@29 { |
| #clock-cells = <0>; |
| reg = <29>; |
| }; |
| |
| trng_clk: trng_clk@30 { |
| #clock-cells = <0>; |
| reg = <30>; |
| }; |
| }; |
| }; |
| |
| rstc@fffffe00 { |
| compatible = "atmel,at91sam9g45-rstc"; |
| reg = <0xfffffe00 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| pit: timer@fffffe30 { |
| compatible = "atmel,at91sam9260-pit"; |
| reg = <0xfffffe30 0xf>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&mck>; |
| }; |
| |
| shdwc@fffffe10 { |
| compatible = "atmel,at91sam9x5-shdwc"; |
| reg = <0xfffffe10 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| sckc@fffffe50 { |
| compatible = "atmel,at91sam9x5-sckc"; |
| reg = <0xfffffe50 0x4>; |
| |
| slow_osc: slow_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| #clock-cells = <0>; |
| clocks = <&slow_xtal>; |
| }; |
| |
| slow_rc_osc: slow_rc_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-accuracy = <50000000>; |
| }; |
| |
| clk32k: slck { |
| compatible = "atmel,at91sam9x5-clk-slow"; |
| #clock-cells = <0>; |
| clocks = <&slow_rc_osc>, <&slow_osc>; |
| }; |
| }; |
| |
| mmc0: mmc@f0008000 { |
| compatible = "atmel,hsmci"; |
| reg = <0xf0008000 0x600>; |
| interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| dma-names = "rxtx"; |
| clocks = <&mci0_clk>; |
| clock-names = "mci_clk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| tcb0: timer@f8008000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xf8008000 0x100>; |
| interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&tcb_clk>, <&clk32k>; |
| clock-names = "t0_clk", "slow_clk"; |
| }; |
| |
| tcb1: timer@f800c000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xf800c000 0x100>; |
| interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&tcb_clk>, <&clk32k>; |
| clock-names = "t0_clk", "slow_clk"; |
| }; |
| |
| hlcdc: hlcdc@f8038000 { |
| compatible = "atmel,at91sam9n12-hlcdc"; |
| reg = <0xf8038000 0x2000>; |
| interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; |
| clock-names = "periph_clk", "sys_clk", "slow_clk"; |
| status = "disabled"; |
| |
| hlcdc-display-controller { |
| compatible = "atmel,hlcdc-display-controller"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| }; |
| |
| hlcdc_pwm: hlcdc-pwm { |
| compatible = "atmel,hlcdc-pwm"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcd_pwm>; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| dma: dma-controller@ffffec00 { |
| compatible = "atmel,at91sam9g45-dma"; |
| reg = <0xffffec00 0x200>; |
| interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| #dma-cells = <2>; |
| clocks = <&dma0_clk>; |
| clock-names = "dma_clk"; |
| }; |
| |
| pinctrl@fffff400 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
| ranges = <0xfffff400 0xfffff400 0x800>; |
| reg = <0xfffff400 0x200 |
| 0xfffff600 0x200 |
| 0xfffff800 0x200 |
| 0xfffffa00 0x200 |
| >; |
| |
| atmel,mux-mask = < |
| /* A B C */ |
| 0xffffffff 0xffe07983 0x00000000 /* pioA */ |
| 0x00040000 0x00047e0f 0x00000000 /* pioB */ |
| 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ |
| 0x003fffff 0x003f8000 0x00000000 /* pioD */ |
| >; |
| bootph-all; |
| |
| /* shared pinctrl settings */ |
| dbgu { |
| bootph-all; |
| pinctrl_dbgu: dbgu-0 { |
| atmel,pins = |
| <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| lcd { |
| pinctrl_lcd_base: lcd-base-0 { |
| atmel,pins = |
| <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ |
| AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ |
| AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ |
| AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ |
| AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ |
| }; |
| |
| pinctrl_lcd_pwm: lcd-pwm-0 { |
| atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ |
| }; |
| |
| pinctrl_lcd_rgb888: lcd-rgb-3 { |
| atmel,pins = |
| <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ |
| AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ |
| AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ |
| AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ |
| AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ |
| AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ |
| AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ |
| AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ |
| AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ |
| AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ |
| AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ |
| AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ |
| AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ |
| AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ |
| AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ |
| AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ |
| AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ |
| }; |
| }; |
| |
| usart0 { |
| pinctrl_usart0: usart0-0 { |
| atmel,pins = |
| <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ |
| }; |
| |
| pinctrl_usart0_rts: usart0_rts-0 { |
| atmel,pins = |
| <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
| }; |
| |
| pinctrl_usart0_cts: usart0_cts-0 { |
| atmel,pins = |
| <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
| }; |
| }; |
| |
| usart1 { |
| pinctrl_usart1: usart1-0 { |
| atmel,pins = |
| <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
| }; |
| }; |
| |
| usart2 { |
| pinctrl_usart2: usart2-0 { |
| atmel,pins = |
| <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ |
| }; |
| |
| pinctrl_usart2_rts: usart2_rts-0 { |
| atmel,pins = |
| <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| }; |
| |
| pinctrl_usart2_cts: usart2_cts-0 { |
| atmel,pins = |
| <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| }; |
| }; |
| |
| usart3 { |
| pinctrl_usart3: usart3-0 { |
| atmel,pins = |
| <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ |
| AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ |
| }; |
| |
| pinctrl_usart3_rts: usart3_rts-0 { |
| atmel,pins = |
| <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
| }; |
| |
| pinctrl_usart3_cts: usart3_cts-0 { |
| atmel,pins = |
| <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
| }; |
| }; |
| |
| uart0 { |
| pinctrl_uart0: uart0-0 { |
| atmel,pins = |
| <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ |
| AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ |
| }; |
| }; |
| |
| uart1 { |
| pinctrl_uart1: uart1-0 { |
| atmel,pins = |
| <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ |
| AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ |
| }; |
| }; |
| |
| nand { |
| pinctrl_nand: nand-0 { |
| atmel,pins = |
| <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ |
| AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ |
| }; |
| }; |
| |
| mmc0 { |
| pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| atmel,pins = |
| <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
| }; |
| |
| pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| atmel,pins = |
| <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
| }; |
| |
| pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| atmel,pins = |
| <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ |
| AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ |
| }; |
| }; |
| |
| ssc0 { |
| pinctrl_ssc0_tx: ssc0_tx-0 { |
| atmel,pins = |
| <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
| }; |
| |
| pinctrl_ssc0_rx: ssc0_rx-0 { |
| atmel,pins = |
| <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| }; |
| }; |
| |
| spi0 { |
| pinctrl_spi0: spi0-0 { |
| atmel,pins = |
| <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
| }; |
| }; |
| |
| spi1 { |
| pinctrl_spi1: spi1-0 { |
| atmel,pins = |
| <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
| }; |
| }; |
| |
| i2c0 { |
| pinctrl_i2c0: i2c0-0 { |
| atmel,pins = |
| <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE |
| AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| i2c1 { |
| pinctrl_i2c1: i2c1-0 { |
| atmel,pins = |
| <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE |
| AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| tcb0 { |
| pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tclk1: tcb0_tclk1-0 { |
| atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tclk2: tcb0_tclk2-0 { |
| atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tioa0: tcb0_tioa0-0 { |
| atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tioa1: tcb0_tioa1-0 { |
| atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tioa2: tcb0_tioa2-0 { |
| atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tiob0: tcb0_tiob0-0 { |
| atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tiob1: tcb0_tiob1-0 { |
| atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb0_tiob2: tcb0_tiob2-0 { |
| atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| tcb1 { |
| pinctrl_tcb1_tclk0: tcb1_tclk0-0 { |
| atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tclk1: tcb1_tclk1-0 { |
| atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tclk2: tcb1_tclk2-0 { |
| atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tioa0: tcb1_tioa0-0 { |
| atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tioa1: tcb1_tioa1-0 { |
| atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tioa2: tcb1_tioa2-0 { |
| atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tiob0: tcb1_tiob0-0 { |
| atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tiob1: tcb1_tiob1-0 { |
| atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| |
| pinctrl_tcb1_tiob2: tcb1_tiob2-0 { |
| atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| }; |
| }; |
| }; |
| |
| pioA: gpio@fffff400 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff400 0x200>; |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioAB_clk>; |
| bootph-all; |
| }; |
| |
| pioB: gpio@fffff600 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff600 0x200>; |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioAB_clk>; |
| bootph-all; |
| }; |
| |
| pioC: gpio@fffff800 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff800 0x200>; |
| interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioCD_clk>; |
| bootph-all; |
| }; |
| |
| pioD: gpio@fffffa00 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffffa00 0x200>; |
| interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioCD_clk>; |
| bootph-all; |
| }; |
| |
| dbgu: serial@fffff200 { |
| compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
| reg = <0xfffff200 0x200>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dbgu>; |
| clocks = <&mck>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| ssc0: ssc@f0010000 { |
| compatible = "atmel,at91sam9g45-ssc"; |
| reg = <0xf0010000 0x4000>; |
| interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, |
| <&dma 0 AT91_DMA_CFG_PER_ID(22)>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| clocks = <&ssc0_clk>; |
| clock-names = "pclk"; |
| status = "disabled"; |
| }; |
| |
| usart0: serial@f801c000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf801c000 0x4000>; |
| interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart0>; |
| clocks = <&usart0_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@f8020000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8020000 0x4000>; |
| interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart1>; |
| clocks = <&usart1_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@f8024000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8024000 0x4000>; |
| interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart2>; |
| clocks = <&usart2_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@f8028000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8028000 0x4000>; |
| interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart3>; |
| clocks = <&usart3_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@f8010000 { |
| compatible = "atmel,at91sam9x5-i2c"; |
| reg = <0xf8010000 0x100>; |
| interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, |
| <&dma 1 AT91_DMA_CFG_PER_ID(14)>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0>; |
| clocks = <&twi0_clk>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@f8014000 { |
| compatible = "atmel,at91sam9x5-i2c"; |
| reg = <0xf8014000 0x100>; |
| interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, |
| <&dma 1 AT91_DMA_CFG_PER_ID(16)>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| clocks = <&twi1_clk>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@f0000000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,at91rm9200-spi"; |
| reg = <0xf0000000 0x100>; |
| interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, |
| <&dma 1 AT91_DMA_CFG_PER_ID(2)>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi0>; |
| clocks = <&spi0_clk>; |
| clock-names = "spi_clk"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@f0004000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,at91rm9200-spi"; |
| reg = <0xf0004000 0x100>; |
| interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, |
| <&dma 1 AT91_DMA_CFG_PER_ID(4)>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| clocks = <&spi1_clk>; |
| clock-names = "spi_clk"; |
| status = "disabled"; |
| }; |
| |
| watchdog@fffffe40 { |
| compatible = "atmel,at91sam9260-wdt"; |
| reg = <0xfffffe40 0x10>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&clk32k>; |
| atmel,watchdog-type = "hardware"; |
| atmel,reset-type = "all"; |
| atmel,dbg-halt; |
| status = "disabled"; |
| }; |
| |
| rtc@fffffeb0 { |
| compatible = "atmel,at91rm9200-rtc"; |
| reg = <0xfffffeb0 0x40>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&clk32k>; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@f8034000 { |
| compatible = "atmel,at91sam9rl-pwm"; |
| reg = <0xf8034000 0x300>; |
| interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; |
| #pwm-cells = <3>; |
| clocks = <&pwm_clk>; |
| status = "disabled"; |
| }; |
| |
| usb1: gadget@f803c000 { |
| compatible = "atmel,at91sam9260-udc"; |
| reg = <0xf803c000 0x4000>; |
| interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; |
| clocks = <&udphs_clk>, <&udpck>; |
| clock-names = "pclk", "hclk"; |
| status = "disabled"; |
| }; |
| }; |
| |
| nand0: nand@40000000 { |
| compatible = "atmel,at91rm9200-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = < 0x40000000 0x10000000 |
| 0xffffe000 0x00000600 |
| 0xffffe600 0x00000200 |
| 0x00108000 0x00018000 |
| >; |
| atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
| atmel,nand-addr-offset = <21>; |
| atmel,nand-cmd-offset = <22>; |
| atmel,nand-has-dma; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_nand>; |
| gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| &pioD 4 GPIO_ACTIVE_HIGH |
| 0 |
| >; |
| status = "disabled"; |
| }; |
| |
| usb0: ohci@00500000 { |
| compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| reg = <0x00500000 0x00100000>; |
| interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; |
| clock-names = "ohci_clk", "hclk", "uhpck"; |
| status = "disabled"; |
| }; |
| }; |
| |
| i2c-gpio-0 { |
| compatible = "i2c-gpio"; |
| gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
| >; |
| i2c-gpio,sda-open-drain; |
| i2c-gpio,scl-open-drain; |
| i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
