| /* |
| * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /* |
| * VScom OnRISC |
| * http://www.vscom.de |
| */ |
| |
| /dts-v1/; |
| |
| #include "am33xx.dtsi" |
| #include <dt-bindings/pwm/pwm.h> |
| |
| / { |
| model = "OnRISC Baltos"; |
| compatible = "vscom,onrisc", "ti,am33xx"; |
| |
| chosen { |
| stdout-path = &uart0; |
| }; |
| |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&vdd1_reg>; |
| }; |
| }; |
| |
| vbat: fixedregulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vbat"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| }; |
| }; |
| |
| &am33xx_pinmux { |
| mmc1_pins: pinmux_mmc1_pins { |
| pinctrl-single,pins = < |
| 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ |
| 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ |
| 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ |
| 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ |
| 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ |
| 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ |
| >; |
| }; |
| |
| i2c1_pins: pinmux_i2c1_pins { |
| pinctrl-single,pins = < |
| 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ |
| 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ |
| >; |
| }; |
| |
| tps65910_pins: pinmux_tps65910_pins { |
| pinctrl-single,pins = < |
| 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ |
| >; |
| |
| }; |
| tca6416_pins: pinmux_tca6416_pins { |
| pinctrl-single,pins = < |
| AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ |
| >; |
| }; |
| |
| uart0_pins: pinmux_uart0_pins { |
| pinctrl-single,pins = < |
| 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| >; |
| }; |
| |
| cpsw_default: cpsw_default { |
| pinctrl-single,pins = < |
| /* Slave 1 */ |
| 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ |
| 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ |
| 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ |
| 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ |
| 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ |
| 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ |
| 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ |
| |
| |
| /* Slave 2 */ |
| 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ |
| 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ |
| 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ |
| 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ |
| 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ |
| 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ |
| 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ |
| 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ |
| 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ |
| 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ |
| 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ |
| 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ |
| >; |
| }; |
| |
| cpsw_sleep: cpsw_sleep { |
| pinctrl-single,pins = < |
| /* Slave 1 reset value */ |
| 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| |
| /* Slave 2 reset value*/ |
| 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| >; |
| }; |
| |
| davinci_mdio_default: davinci_mdio_default { |
| pinctrl-single,pins = < |
| /* MDIO */ |
| 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| >; |
| }; |
| |
| davinci_mdio_sleep: davinci_mdio_sleep { |
| pinctrl-single,pins = < |
| /* MDIO reset value */ |
| 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| >; |
| }; |
| |
| nandflash_pins_s0: nandflash_pins_s0 { |
| pinctrl-single,pins = < |
| 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
| 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
| 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
| 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
| 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
| 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
| 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
| 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
| 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
| 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ |
| 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
| 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
| 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
| 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
| 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
| >; |
| }; |
| }; |
| |
| &elm { |
| status = "okay"; |
| }; |
| |
| &gpmc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&nandflash_pins_s0>; |
| ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ |
| status = "okay"; |
| |
| nand@0,0 { |
| reg = <0 0 0>; /* CS0, offset 0 */ |
| nand-bus-width = <8>; |
| ti,nand-ecc-opt = "bch8"; |
| ti,nand-xfer-type = "polled"; |
| |
| gpmc,device-nand = "true"; |
| gpmc,device-width = <1>; |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <44>; |
| gpmc,cs-wr-off-ns = <44>; |
| gpmc,adv-on-ns = <6>; |
| gpmc,adv-rd-off-ns = <34>; |
| gpmc,adv-wr-off-ns = <44>; |
| gpmc,we-on-ns = <0>; |
| gpmc,we-off-ns = <40>; |
| gpmc,oe-on-ns = <0>; |
| gpmc,oe-off-ns = <54>; |
| gpmc,access-ns = <64>; |
| gpmc,rd-cycle-ns = <82>; |
| gpmc,wr-cycle-ns = <82>; |
| gpmc,wait-on-read = "true"; |
| gpmc,wait-on-write = "true"; |
| gpmc,bus-turnaround-ns = <0>; |
| gpmc,cycle2cycle-delay-ns = <0>; |
| gpmc,clk-activation-ns = <0>; |
| gpmc,wait-monitoring-ns = <0>; |
| gpmc,wr-access-ns = <40>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| elm_id = <&elm>; |
| |
| boot@0 { |
| label = "SPL"; |
| reg = <0x0 0x20000>; |
| }; |
| boot@20000{ |
| label = "SPL.backup1"; |
| reg = <0x20000 0x20000>; |
| }; |
| boot@40000 { |
| label = "SPL.backup2"; |
| reg = <0x40000 0x20000>; |
| }; |
| boot@60000 { |
| label = "SPL.backup3"; |
| reg = <0x60000 0x20000>; |
| }; |
| boot@80000 { |
| label = "u-boot"; |
| reg = <0x80000 0x1e0000>; |
| }; |
| boot@260000 { |
| label = "UBI"; |
| reg = <0x260000 0xfda0000>; |
| }; |
| }; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| |
| status = "okay"; |
| clock-frequency = <1000>; |
| |
| tps: tps@2d { |
| reg = <0x2d>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <28 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&tps65910_pins>; |
| }; |
| |
| at24@50 { |
| compatible = "at24,24c02"; |
| pagesize = <8>; |
| reg = <0x50>; |
| }; |
| |
| tca6416: gpio@20 { |
| compatible = "ti,tca6416"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gpio0>; |
| interrupts = <20 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&tca6416_pins>; |
| }; |
| }; |
| |
| &usb { |
| status = "okay"; |
| }; |
| |
| &usb_ctrl_mod { |
| status = "okay"; |
| }; |
| |
| &usb0_phy { |
| status = "okay"; |
| }; |
| |
| &usb1_phy { |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| status = "okay"; |
| dr_mode = "host"; |
| }; |
| |
| &usb1 { |
| status = "okay"; |
| dr_mode = "host"; |
| }; |
| |
| &cppi41dma { |
| status = "okay"; |
| }; |
| |
| /include/ "tps65910.dtsi" |
| |
| &tps { |
| vcc1-supply = <&vbat>; |
| vcc2-supply = <&vbat>; |
| vcc3-supply = <&vbat>; |
| vcc4-supply = <&vbat>; |
| vcc5-supply = <&vbat>; |
| vcc6-supply = <&vbat>; |
| vcc7-supply = <&vbat>; |
| vccio-supply = <&vbat>; |
| |
| ti,en-ck32k-xtal = <1>; |
| |
| regulators { |
| vrtc_reg: regulator@0 { |
| regulator-always-on; |
| }; |
| |
| vio_reg: regulator@1 { |
| regulator-always-on; |
| }; |
| |
| vdd1_reg: regulator@2 { |
| /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1312500>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd2_reg: regulator@3 { |
| /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1150000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd3_reg: regulator@4 { |
| regulator-always-on; |
| }; |
| |
| vdig1_reg: regulator@5 { |
| regulator-always-on; |
| }; |
| |
| vdig2_reg: regulator@6 { |
| regulator-always-on; |
| }; |
| |
| vpll_reg: regulator@7 { |
| regulator-always-on; |
| }; |
| |
| vdac_reg: regulator@8 { |
| regulator-always-on; |
| }; |
| |
| vaux1_reg: regulator@9 { |
| regulator-always-on; |
| }; |
| |
| vaux2_reg: regulator@10 { |
| regulator-always-on; |
| }; |
| |
| vaux33_reg: regulator@11 { |
| regulator-always-on; |
| }; |
| |
| vmmc_reg: regulator@12 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| &mac { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&cpsw_default>; |
| pinctrl-1 = <&cpsw_sleep>; |
| dual_emac = <1>; |
| |
| status = "okay"; |
| }; |
| |
| &davinci_mdio { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&davinci_mdio_default>; |
| pinctrl-1 = <&davinci_mdio_sleep>; |
| |
| status = "okay"; |
| |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| |
| phy1: ethernet-phy@7 { |
| reg = <7>; |
| eee-broken-100tx; |
| eee-broken-1000t; |
| }; |
| }; |
| |
| &cpsw_emac0 { |
| phy-handle = <&phy0>; |
| phy-mode = "rmii"; |
| dual_emac_res_vlan = <1>; |
| }; |
| |
| &cpsw_emac1 { |
| phy-handle = <&phy1>; |
| phy-mode = "rgmii-txid"; |
| dual_emac_res_vlan = <2>; |
| }; |
| |
| &phy_sel { |
| rmii-clock-ext = <1>; |
| }; |
| |
| &mmc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| vmmc-supply = <&vmmc_reg>; |
| status = "okay"; |
| }; |
| |
| &gpio0 { |
| ti,no-reset-on-init; |
| }; |
