| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright (C) 2018 Rockchip Electronics Co., Ltd |
| */ |
| |
| #ifndef _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H |
| #define _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H |
| |
| #define PHY_DDR3_RON_RTT_DISABLE (0) |
| #define PHY_DDR3_RON_RTT_451ohm (1) |
| #define PHY_DDR3_RON_RTT_225ohm (2) |
| #define PHY_DDR3_RON_RTT_150ohm (3) |
| #define PHY_DDR3_RON_RTT_112ohm (4) |
| #define PHY_DDR3_RON_RTT_90ohm (5) |
| #define PHY_DDR3_RON_RTT_75ohm (6) |
| #define PHY_DDR3_RON_RTT_64ohm (7) |
| #define PHY_DDR3_RON_RTT_56ohm (16) |
| #define PHY_DDR3_RON_RTT_50ohm (17) |
| #define PHY_DDR3_RON_RTT_45ohm (18) |
| #define PHY_DDR3_RON_RTT_41ohm (19) |
| #define PHY_DDR3_RON_RTT_37ohm (20) |
| #define PHY_DDR3_RON_RTT_34ohm (21) |
| #define PHY_DDR3_RON_RTT_33ohm (22) |
| #define PHY_DDR3_RON_RTT_30ohm (23) |
| #define PHY_DDR3_RON_RTT_28ohm (24) |
| #define PHY_DDR3_RON_RTT_26ohm (25) |
| #define PHY_DDR3_RON_RTT_25ohm (26) |
| #define PHY_DDR3_RON_RTT_23ohm (27) |
| #define PHY_DDR3_RON_RTT_22ohm (28) |
| #define PHY_DDR3_RON_RTT_21ohm (29) |
| #define PHY_DDR3_RON_RTT_20ohm (30) |
| #define PHY_DDR3_RON_RTT_19ohm (31) |
| |
| #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) |
| #define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) |
| #define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) |
| #define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) |
| #define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) |
| #define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) |
| #define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) |
| #define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) |
| #define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) |
| #define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) |
| #define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) |
| #define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) |
| #define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) |
| #define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) |
| #define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) |
| #define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) |
| #define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) |
| #define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) |
| #define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) |
| #define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) |
| #define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) |
| #define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) |
| #define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) |
| #define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) |
| |
| #endif |
