| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2022 MediaTek Inc. |
| * Author: Sam Shih <sam.shih@mediatek.com> |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/mt7981-clk.h> |
| #include <dt-bindings/reset/mt7629-reset.h> |
| #include <dt-bindings/pinctrl/mt65xx.h> |
| |
| / { |
| compatible = "mediatek,mt7981"; |
| interrupt-parent = <&gic>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| mediatek,hwver = <&hwver>; |
| }; |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| mediatek,hwver = <&hwver>; |
| }; |
| }; |
| |
| gpt_clk: gpt_dummy20m { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| bootph-all; |
| }; |
| |
| hwver: hwver { |
| compatible = "mediatek,hwver", "syscon"; |
| reg = <0x8000000 0x1000>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| clock-frequency = <13000000>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| arm,cpu-registers-not-fw-configured; |
| }; |
| |
| timer0: timer@10008000 { |
| compatible = "mediatek,mt7986-timer"; |
| reg = <0x10008000 0x1000>; |
| interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gpt_clk>; |
| clock-names = "gpt-clk"; |
| bootph-all; |
| }; |
| |
| watchdog: watchdog@1001c000 { |
| compatible = "mediatek,mt7986-wdt"; |
| reg = <0x1001c000 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0x0c000000 0x40000>, /* GICD */ |
| <0x0c080000 0x200000>; /* GICR */ |
| |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| fixed_plls: apmixedsys@1001e000 { |
| compatible = "mediatek,mt7981-fixed-plls"; |
| reg = <0x1001e000 0x1000>; |
| #clock-cells = <1>; |
| bootph-all; |
| }; |
| |
| topckgen: topckgen@1001b000 { |
| compatible = "mediatek,mt7981-topckgen"; |
| reg = <0x1001b000 0x1000>; |
| clock-parent = <&fixed_plls>; |
| #clock-cells = <1>; |
| bootph-all; |
| }; |
| |
| infracfg_ao: infracfg_ao@10001000 { |
| compatible = "mediatek,mt7981-infracfg_ao"; |
| reg = <0x10001000 0x80>; |
| clock-parent = <&infracfg>; |
| #clock-cells = <1>; |
| bootph-all; |
| }; |
| |
| infracfg: infracfg@10001000 { |
| compatible = "mediatek,mt7981-infracfg"; |
| reg = <0x10001000 0x30>; |
| clock-parent = <&topckgen>; |
| #clock-cells = <1>; |
| bootph-all; |
| }; |
| |
| pinctrl: pinctrl@11d00000 { |
| compatible = "mediatek,mt7981-pinctrl"; |
| reg = <0x11d00000 0x1000>, |
| <0x11c00000 0x1000>, |
| <0x11c10000 0x1000>, |
| <0x11d20000 0x1000>, |
| <0x11e00000 0x1000>, |
| <0x11e20000 0x1000>, |
| <0x11f00000 0x1000>, |
| <0x11f10000 0x1000>, |
| <0x1000b000 0x1000>; |
| reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", |
| "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", |
| "iocfg_tm_base", "iocfg_tl_base", "eint"; |
| gpio: gpio-controller { |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| pwm: pwm@10048000 { |
| compatible = "mediatek,mt7981-pwm"; |
| reg = <0x10048000 0x1000>; |
| #clock-cells = <1>; |
| #pwm-cells = <2>; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CK_INFRA_PWM>, |
| <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| <&infracfg_ao CK_INFRA_PWM1_CK>, |
| <&infracfg_ao CK_INFRA_PWM2_CK>, |
| /* FIXME */ |
| <&infracfg_ao CK_INFRA_PWM2_CK>; |
| assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11002000 0x400>; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART0_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| mediatek,force-highspeed; |
| status = "disabled"; |
| bootph-all; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11003000 0x400>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART1_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| mediatek,force-highspeed; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11004000 0x400>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART2_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| mediatek,force-highspeed; |
| status = "disabled"; |
| }; |
| |
| snand: snand@11005000 { |
| compatible = "mediatek,mt7986-snand"; |
| reg = <0x11005000 0x1000>, |
| <0x11006000 0x1000>; |
| reg-names = "nfi", "ecc"; |
| clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| <&infracfg_ao CK_INFRA_NFI1_CK>, |
| <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
| assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| <&topckgen CK_TOP_NFI1X_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| <&topckgen CK_TOP_CB_M_D8>; |
| status = "disabled"; |
| }; |
| |
| ethsys: syscon@15000000 { |
| compatible = "mediatek,mt7981-ethsys", "syscon"; |
| reg = <0x15000000 0x1000>; |
| clock-parent = <&topckgen>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| eth: ethernet@15100000 { |
| compatible = "mediatek,mt7981-eth", "syscon"; |
| reg = <0x15100000 0x20000>; |
| resets = <ðsys ETHSYS_FE_RST>; |
| reset-names = "fe"; |
| mediatek,ethsys = <ðsys>; |
| mediatek,sgmiisys = <&sgmiisys0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sgmiisys0: syscon@10060000 { |
| compatible = "mediatek,mt7986-sgmiisys", "syscon"; |
| reg = <0x10060000 0x1000>; |
| pn_swap; |
| #clock-cells = <1>; |
| }; |
| |
| sgmiisys1: syscon@10070000 { |
| compatible = "mediatek,mt7986-sgmiisys", "syscon"; |
| reg = <0x10070000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,ipm-spi"; |
| reg = <0x1100a000 0x100>; |
| clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, |
| <&topckgen CK_TOP_SPI_SEL>; |
| assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, |
| <&infracfg CK_INFRA_SPI0_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_INFRA_ISPI0>; |
| clock-names = "sel-clk", "spi-clk"; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@1100b000 { |
| compatible = "mediatek,ipm-spi"; |
| reg = <0x1100b000 0x100>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11009000 { |
| compatible = "mediatek,ipm-spi"; |
| reg = <0x11009000 0x100>; |
| clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, |
| <&topckgen CK_TOP_SPI_SEL>; |
| assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, |
| <&infracfg CK_INFRA_SPI0_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_INFRA_ISPI0>; |
| clock-names = "sel-clk", "spi-clk"; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt7981-mmc"; |
| reg = <0x11230000 0x1000>, |
| <0x11C20000 0x1000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CK_TOP_EMMC_400M>, |
| <&topckgen CK_TOP_EMMC_208M>, |
| <&infracfg_ao CK_INFRA_MSDC_CK>; |
| assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>, |
| <&topckgen CK_TOP_EMMC_208M_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>, |
| <&topckgen CK_TOP_CB_M_D2>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| }; |
