| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| /dts-v1/; |
| |
| #include "k3-j721e.dtsi" |
| #include "k3-j721e-ddr-sk-lp4-4266.dtsi" |
| #include "k3-j721e-ddr.dtsi" |
| |
| / { |
| model = "Texas Instruments J721E SK R5"; |
| |
| aliases { |
| remoteproc0 = &sysctrler; |
| remoteproc1 = &a72_0; |
| }; |
| |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| tick-timer = &timer1; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* 4G RAM */ |
| reg = <0x00000000 0x80000000 0x00000000 0x80000000>, |
| <0x00000008 0x80000000 0x00000000 0x80000000>; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| secure_ddr: optee@9e800000 { |
| reg = <0x00 0x9e800000 0x00 0x01800000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_memory_region: r5f-memory@a2100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_memory_region: r5f-memory@a3100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_memory_region: r5f-memory@a4100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_memory_region: r5f-memory@a5100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_1_dma_memory_region: c66-dma-memory@a6000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_0_memory_region: c66-memory@a6100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_0_dma_memory_region: c66-dma-memory@a7000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_1_memory_region: c66-memory@a7100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_0_dma_memory_region: c71-dma-memory@a8000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_0_memory_region: c71-memory@a8100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| rtos_ipc_memory_region: ipc-memories@aa000000 { |
| reg = <0x00 0xaa000000 0x00 0x01c00000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| }; |
| |
| a72_0: a72@0 { |
| compatible = "ti,am654-rproc"; |
| reg = <0x0 0x00a90000 0x0 0x10>; |
| power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, |
| <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, |
| <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; |
| resets = <&k3_reset 202 0>; |
| clocks = <&k3_clks 61 1>; |
| assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; |
| assigned-clock-rates = <2000000000>, <200000000>; |
| ti,sci = <&dmsc>; |
| ti,sci-proc-id = <32>; |
| ti,sci-host-id = <10>; |
| bootph-pre-ram; |
| }; |
| |
| clk_200mhz: dummy_clock_200mhz { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <200000000>; |
| bootph-pre-ram; |
| }; |
| |
| clk_19_2mhz: dummy_clock_19_2mhz { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &cbass_mcu_wakeup { |
| mcu_secproxy: secproxy@28380000 { |
| bootph-pre-ram; |
| compatible = "ti,am654-secure-proxy"; |
| reg = <0x0 0x2a380000 0x0 0x80000>, |
| <0x0 0x2a400000 0x0 0x80000>, |
| <0x0 0x2a480000 0x0 0x80000>; |
| reg-names = "rt", "scfg", "target_data"; |
| #mbox-cells = <1>; |
| }; |
| |
| sysctrler: sysctrler { |
| bootph-pre-ram; |
| compatible = "ti,am654-system-controller"; |
| mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; |
| mbox-names = "tx", "rx"; |
| }; |
| |
| wkup_vtm0: wkup_vtm@42040000 { |
| compatible = "ti,am654-vtm", "ti,j721e-avs"; |
| reg = <0x0 0x42040000 0x0 0x330>; |
| power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| dm_tifs: dm-tifs { |
| compatible = "ti,j721e-dm-sci"; |
| ti,host-id = <3>; |
| ti,secure-host; |
| mbox-names = "rx", "tx"; |
| mboxes= <&mcu_secproxy 21>, |
| <&mcu_secproxy 23>; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &cbass_main { |
| main_esm: esm@700000 { |
| compatible = "ti,j721e-esm"; |
| reg = <0x0 0x700000 0x0 0x1000>; |
| ti,esm-pins = <344>, <345>; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &dmsc { |
| mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; |
| mbox-names = "tx", "rx", "notify"; |
| ti,host-id = <4>; |
| ti,secure-host; |
| }; |
| |
| &wkup_pmx0 { |
| wkup_uart0_pins_default: wkup_uart0_pins_default { |
| bootph-pre-ram; |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ |
| J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ |
| >; |
| }; |
| |
| mcu_uart0_pins_default: mcu_uart0_pins_default { |
| bootph-pre-ram; |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ |
| J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ |
| J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ |
| J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ |
| >; |
| }; |
| |
| wkup_i2c0_pins_default: wkup-i2c0-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ |
| J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ |
| >; |
| }; |
| |
| mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ |
| J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ |
| J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ |
| J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ |
| J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ |
| J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ |
| J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ |
| J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ |
| J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ |
| J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ |
| J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ |
| >; |
| }; |
| |
| mcu_i2c0_pins_default: mcu_i2c0_pins_default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */ |
| J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */ |
| >; |
| }; |
| }; |
| |
| &main_pmx0 { |
| main_uart0_pins_default: main_uart0_pins_default { |
| bootph-pre-ram; |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ |
| J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ |
| J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ |
| J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ |
| >; |
| }; |
| |
| main_usbss0_pins_default: main_usbss0_pins_default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ |
| J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ |
| >; |
| }; |
| |
| main_usbss1_pins_default: main-usbss1-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ |
| >; |
| }; |
| |
| main_mmc1_pins_default: main_mmc1_pins_default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ |
| J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ |
| J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ |
| J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ |
| J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ |
| J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ |
| J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ |
| J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ |
| >; |
| }; |
| |
| main_i2c0_pins_default: main-i2c0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ |
| J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ |
| >; |
| }; |
| |
| main_i2c1_pins_default: main-i2c1-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ |
| J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ |
| >; |
| }; |
| |
| main_i2c2_pins_default: main-i2c2-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */ |
| J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */ |
| >; |
| }; |
| |
| main_i2c3_pins_default: main-i2c3-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ |
| J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ |
| >; |
| }; |
| |
| main_i2c5_pins_default: main-i2c5-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ |
| J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ |
| >; |
| }; |
| }; |
| |
| &wkup_uart0 { |
| bootph-pre-ram; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_uart0_pins_default>; |
| status = "okay"; |
| }; |
| |
| &mcu_uart0 { |
| /delete-property/ power-domains; |
| /delete-property/ clocks; |
| /delete-property/ clock-names; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_uart0_pins_default>; |
| status = "okay"; |
| clock-frequency = <48000000>; |
| }; |
| |
| &main_uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_uart0_pins_default>; |
| status = "okay"; |
| power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; |
| }; |
| |
| &main_sdhci0 { |
| status = "disabled"; |
| }; |
| |
| &main_sdhci1 { |
| /delete-property/ power-domains; |
| /delete-property/ assigned-clocks; |
| /delete-property/ assigned-clock-parents; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_mmc1_pins_default>; |
| clock-names = "clk_xin"; |
| clocks = <&clk_200mhz>; |
| ti,driver-strength-ohm = <50>; |
| }; |
| |
| &wkup_i2c0 { |
| bootph-pre-ram; |
| tps659412: tps659412@48 { |
| reg = <0x48>; |
| compatible = "ti,tps659412"; |
| bootph-pre-ram; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| regulators: regulators { |
| bootph-pre-ram; |
| /* 3 Phase Buck */ |
| buck123_reg: buck123 { |
| /* VDD_CPU */ |
| regulator-name = "buck123"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-always-on; |
| regulator-boot-on; |
| bootph-pre-ram; |
| }; |
| }; |
| }; |
| }; |
| |
| &wkup_vtm0 { |
| vdd-supply-2 = <&buck123_reg>; |
| bootph-pre-ram; |
| }; |
| |
| &usbss0 { |
| /delete-property/ power-domains; |
| /delete-property/ assigned-clocks; |
| /delete-property/ assigned-clock-parents; |
| clocks = <&clk_19_2mhz>; |
| clock-names = "usb2_refclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_usbss0_pins_default>; |
| ti,vbus-divider; |
| }; |
| |
| &usbss1 { |
| /delete-property/ power-domains; |
| /delete-property/ assigned-clocks; |
| /delete-property/ assigned-clock-parents; |
| clocks = <&clk_19_2mhz>; |
| clock-names = "usb2_refclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_usbss1_pins_default>; |
| }; |
| |
| &main_i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| }; |
| |
| &ospi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
| |
| reg = <0x0 0x47040000 0x0 0x100>, |
| <0x0 0x50000000 0x0 0x8000000>; |
| |
| flash@0{ |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| spi-max-frequency = <25000000>; |
| cdns,tshsl-ns = <60>; |
| cdns,tsd2d-ns = <60>; |
| cdns,tchsh-ns = <60>; |
| cdns,tslch-ns = <60>; |
| cdns,read-delay = <4>; |
| cdns,phy-mode; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| &ospi1 { |
| status = "disabled"; |
| }; |
| |
| &mcu_ringacc { |
| ti,sci = <&dm_tifs>; |
| }; |
| |
| &mcu_udmap { |
| ti,sci = <&dm_tifs>; |
| }; |
| |
| &mailbox0_cluster0 { |
| interrupts = <436>; |
| |
| mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster1 { |
| interrupts = <432>; |
| |
| mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster2 { |
| interrupts = <428>; |
| |
| mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster3 { |
| interrupts = <424>; |
| |
| mbox_c66_0: mbox-c66-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c66_1: mbox-c66-1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster4 { |
| interrupts = <420>; |
| |
| mbox_c71_0: mbox-c71-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster5 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster6 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster7 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster8 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster9 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster10 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster11 { |
| status = "disabled"; |
| }; |
| |
| &mcu_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; |
| memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| <&mcu_r5fss0_core0_memory_region>; |
| }; |
| |
| &mcu_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; |
| memory-region = <&mcu_r5fss0_core1_dma_memory_region>, |
| <&mcu_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; |
| memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| <&main_r5fss0_core0_memory_region>; |
| }; |
| |
| &main_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; |
| memory-region = <&main_r5fss0_core1_dma_memory_region>, |
| <&main_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss1_core0 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; |
| memory-region = <&main_r5fss1_core0_dma_memory_region>, |
| <&main_r5fss1_core0_memory_region>; |
| }; |
| |
| &main_r5fss1_core1 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; |
| memory-region = <&main_r5fss1_core1_dma_memory_region>, |
| <&main_r5fss1_core1_memory_region>; |
| }; |
| |
| &c66_0 { |
| mboxes = <&mailbox0_cluster3 &mbox_c66_0>; |
| memory-region = <&c66_0_dma_memory_region>, |
| <&c66_0_memory_region>; |
| }; |
| |
| &c66_1 { |
| mboxes = <&mailbox0_cluster3 &mbox_c66_1>; |
| memory-region = <&c66_1_dma_memory_region>, |
| <&c66_1_memory_region>; |
| }; |
| |
| &c71_0 { |
| mboxes = <&mailbox0_cluster4 &mbox_c71_0>; |
| memory-region = <&c71_0_dma_memory_region>, |
| <&c71_0_memory_region>; |
| }; |
| |
| /* EEPROM might be read before SYSFW is available */ |
| &wkup_i2c0 { |
| /delete-property/ power-domains; |
| }; |
