| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 |
| * Copyright (c) Siemens AG, 2022 |
| * |
| * Authors: |
| * Chao Zeng <chao.zeng@siemens.com> |
| * Jan Kiszka <jan.kiszka@siemens.com> |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| &serdes0 { |
| assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; |
| }; |
| |
| &pcie0_rc { |
| status = "disabled"; |
| }; |
| |
| &pcie1_rc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&minipcie_pins_default>; |
| |
| num-lanes = <1>; |
| phys = <&serdes1 PHY_TYPE_PCIE 0>; |
| phy-names = "pcie-phy0"; |
| reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &dwc3_0 { |
| assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ |
| <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ |
| phys = <&serdes0 PHY_TYPE_USB3 0>; |
| phy-names = "usb3-phy"; |
| }; |
| |
| &usb0 { |
| maximum-speed = "super-speed"; |
| snps,dis-u1-entry-quirk; |
| snps,dis-u2-entry-quirk; |
| }; |
