| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2021 Linaro |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| |
| #include "imx8mm-pinfunc.h" |
| |
| &ecspi1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| fsl,spi-num-chipselects = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &ecspi2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| fsl,spi-num-chipselects = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; |
| cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &ecspi3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| fsl,spi-num-chipselects = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; |
| cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_ecspi1: ecspi1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 |
| MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 |
| MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 |
| >; |
| }; |
| |
| pinctrl_ecspi1_cs: ecspi1cs { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 |
| >; |
| }; |
| |
| pinctrl_ecspi2: ecspi2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x02 |
| MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x02 |
| MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x102 |
| >; |
| }; |
| |
| pinctrl_ecspi2_cs: ecspi2_csgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 |
| >; |
| }; |
| |
| pinctrl_ecspi3: ecspi3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x02 |
| MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x02 |
| MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x102 |
| >; |
| }; |
| |
| pinctrl_ecspi3_cs: ecspi3_csgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000 |
| >; |
| }; |
| }; |
