libpore/p9_cpu_reg_restore_instruction.H

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/* $Source: src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H $ */
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///
/// @file   p9_cpu_reg_restore_instruction.H
/// @brief  enumerates all the opcodes used for SPR restoration.
///
// *HWP HW Owner    :  Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner    :  Prem Shanker Jha <premjha2@in.ibm.com>
// *HWP Team        :  PM
// *HWP Level       :  2
// *HWP Consumed by :  HB:HYP

#ifndef __REG_RESTORE_INSTRUCTION_H
#define __REG_RESTORE_INSTRUCTION_H

#include <stdint.h>

#ifdef __cplusplus
extern "C" {

namespace stopImageSection
{
#endif

/**
 * @brief enumerates opcodes for few instructions.
 */
enum
{
    ORI_OPCODE          =   24,
    RFI_OPCODE          =   19,
    RFI_CONST           =   50,
    MFMSR_CONST         =   83,
    ORIS_OPCODE         =   25,
    OPCODE_31           =   31,
    XOR_CONST           =   316,
    RLDICR_OPCODE       =   30,
    RLDICR_CONST        =   1,
    MTSPR_CONST1        =   467,
    MTMSRD_CONST1       =   178,
    MFSPR_CONST         =   339,
    OPCODE_18           =   18,
    SELF_SAVE_FUNC_ADD  =   0x2300,
    SELF_SAVE_OFFSET    =   0x180,
};

#define MR_R0_TO_R10            0x7c0a0378UL //mr r10 r0
#define MR_R0_TO_R21            0x7c150378UL //mr r21 r0
#define MR_R0_TO_R9             0x7c090378UL //mr r9 r0
#define URMOR_CORRECTION        0x7d397ba6UL
#define BLR_INST                0x4e800020UL
#define MTSPR_BASE_OPCODE       0x7c0003a6UL
#define ATTN_OPCODE             0x00000200UL
#define SKIP_SPR_REST_INST      0x4800001cUL //b . +0x01c
#define MFLR_R30                0x7fc802a6UL
#define SKIP_SPR_SELF_SAVE      0x3bff0020UL //addi r31 r31 0x20
#define MTLR_INST               0x7fc803a6UL //mtlr r30

#ifdef __cplusplus
} // namespace stopImageSection ends

} // extern "C"
#endif //__cplusplus

#endif //__REG_RESTORE_INSTRUCTION_H