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| <section id="skiboot-5-5-0-rc2"> |
| <span id="id1"></span><h1>skiboot-5.5.0-rc2<a class="headerlink" href="#skiboot-5-5-0-rc2" title="Link to this heading">¶</a></h1> |
| <p>skiboot-5.5.0-rc2 was released on Monday April 3rd 2017. It is the second |
| release candidate of skiboot 5.5, which will become the new stable release |
| of skiboot following the 5.4 release, first released November 11th 2016.</p> |
| <p>skiboot-5.5.0-rc2 contains all bug fixes as of <a class="reference internal" href="skiboot-5.4.3.html#skiboot-5-4-3"><span class="std std-ref">skiboot-5.4.3</span></a> |
| and <a class="reference internal" href="skiboot-5.1.19.html#skiboot-5-1-19"><span class="std std-ref">skiboot-5.1.19</span></a> (the currently maintained stable releases).</p> |
| <p>For how the skiboot stable releases work, see <a class="reference internal" href="../process/stable-skiboot-rules.html#stable-rules"><span class="std std-ref">Skiboot stable tree rules and releases</span></a> for details.</p> |
| <p>The current plan is to cut the final 5.5.0 by April 8th, with skiboot 5.5.0 |
| being for all POWER8 and POWER9 platforms in op-build v1.16 (Due April 12th). |
| This is a short cycle as this release is mainly targetted towards POWER9 |
| bringup efforts.</p> |
| <p>Following skiboot-5.5.0, we will move to a regular six week release cycle, |
| similar to op-build, but slightly offset to allow for a short stabilisation |
| period. Expected release dates and contents are tracked using GitHub milestone |
| and issues: <a class="reference external" href="https://github.com/open-power/skiboot/milestones">https://github.com/open-power/skiboot/milestones</a></p> |
| <p>Over <a class="reference internal" href="skiboot-5.5.0-rc1.html#skiboot-5-5-0-rc1"><span class="std std-ref">skiboot-5.5.0-rc1</span></a>, we have the following changes:</p> |
| <section id="nvlink2"> |
| <h2>NVLINK2<a class="headerlink" href="#nvlink2" title="Link to this heading">¶</a></h2> |
| <ul> |
| <li><p>Introduce NPU2 support</p> |
| <p>NVLink2 is a new feature introduced on POWER9 systems. It is an |
| evolution of of the NVLink1 feature included in POWER8+ systems but |
| adds several new features including support for GPU address |
| translation using the Nest MMU and cache coherence.</p> |
| <p>Similar to NVLink1 the functionality is exposed to the OS as a series |
| of virtual PCIe devices. However the actual hardware interfaces are |
| significantly different which limits the amount of common code that |
| can be shared between implementations in the firmware.</p> |
| <p>This patch adds basic hardware initialisation and exposure of the |
| virtual NVLink2 PCIe devices to the running OS.</p> |
| </li> |
| <li><p>npu2: Add OPAL calls for nvlink2 address translation services (see <a class="reference internal" href="../opal-api/opal-npu2-146-147-148.html#opal-npu2"><span class="std std-ref">OPAL NPU2 calls</span></a>)</p> |
| <p>Adds three OPAL calls for interacting with NPU2 devices: |
| <a class="reference internal" href="../opal-api/opal-npu2-146-147-148.html#opal-npu-init-context"><span class="std std-ref">OPAL_NPU_INIT_CONTEXT</span></a>, <a class="reference internal" href="../opal-api/opal-npu2-146-147-148.html#opal-npu-destroy-context"><span class="std std-ref">OPAL_NPU_DESTROY_CONTEXT</span></a> and |
| <a class="reference internal" href="../opal-api/opal-npu2-146-147-148.html#opal-npu-map-lpar"><span class="std std-ref">OPAL_NPU_MAP_LPAR</span></a>.</p> |
| <p>These are used to setup and configure address translation services |
| (ATS) for a process/partition on a given NVLink2 device.</p> |
| </li> |
| </ul> |
| </section> |
| <section id="power9"> |
| <h2>POWER9<a class="headerlink" href="#power9" title="Link to this heading">¶</a></h2> |
| <ul> |
| <li><p>hdata/memory: ignore homer and occ reserved ranges</p> |
| <p>We populate these from the HOMER BARs in the PBA directly. There’s no |
| need to take the hostboot supplied values so just ignore the |
| corresponding reserved ranges.</p> |
| </li> |
| <li><p>hdata/vpd: Parse the OpenPOWER OPFR record</p> |
| <p>Parse the OpenPOWER FRU VPD (OPFR) record on OpenPOWER instead |
| of the VINI records.</p> |
| </li> |
| <li><p>hdata/vpd: Parse additional VINI records</p> |
| <p>These records provide hardware version details, CCIN extension information, |
| card type details and hardware characteristics of the FRU</p> |
| </li> |
| <li><p>hdata/cpu: account for p9 shared caches</p> |
| <p>On P9 the L2 and L3 caches are shared between pairs of SMT=4 cores. |
| Currently this is not accounted for when creating caches nodes in |
| the device tree. This patch adds additional checking so that a |
| cache node is only created for the first core in the pair and |
| the second core will reference the cache correctly.</p> |
| </li> |
| <li><p>hdata: print backtraces on HDAT errors</p></li> |
| <li><p>hdat: ignore zero length reserves</p> |
| <p>Hostboot can export reserved regions with a length of zero and these |
| should be ignored rather than being turned into reserved range. While |
| we’re here fix a memory leak by moving the “too large” region check |
| to before we allocate space for the label.</p> |
| </li> |
| <li><p>SLW: Add init for power9 power management</p> |
| <p>This patch adds new function to init core for power9 power management. |
| SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into |
| idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each |
| core during init. (This init are not required for MAMBO)</p> |
| </li> |
| </ul> |
| </section> |
| <section id="pci"> |
| <h2>PCI<a class="headerlink" href="#pci" title="Link to this heading">¶</a></h2> |
| <ul> |
| <li><p>hw/phb3: Adjust ECRC on root port dynamically</p> |
| <p>The Samsung NVMe adapter is lost when it’s connected to PMC 8546 PCIe |
| switch, until ECRC is disabled on the root port. We found similar issue |
| prevously when Broadcom adapter is connected to same part of PCIe switch |
| and it was fixed by commit 60ce59ccd0e9 (“hw/phb3: Disable ECRC on Broadcom |
| adapter behind PMC switch”). Unfortunately, the commit doesn’t fix |
| the Samsung NVMe adapter lost issue.</p> |
| <p>This fixes the issues by disable ECRC generation/check on root port |
| when PMC 8546 PCIe switch ports are found. This can be extended for |
| other PCIe switches or endpoints in future: Each PHB maintains the |
| count of PCI devices (PMC 8546 PCIe switch ports currently) which |
| require to disable ECRC on root port. The ECRC functionality is |
| enabled when first PMC 8546 switch port is probed and disabled when |
| last PMC 8546 switch port is destroyed (in PCI hot remove scenario). |
| Except PHB’s reinitialization after complete reset, the ECRC on |
| root port is untouched.</p> |
| </li> |
| <li><p>core/pci: Fix lost NVMe adapter behind PMC 8546 switch</p> |
| <p>The NVMe adapter in below PCI topology is lost. The root cause is |
| the presence bit on its PCI slot is missed, but the PCIe link has |
| been up. The PCI core doesn’t probe the adapter behind the slot, |
| leading to lost NVMe adapter in the particular case.</p> |
| <ul class="simple"> |
| <li><p>PHB3 root port</p></li> |
| <li><p>PLX switch 8748 (10b5:8748)</p></li> |
| <li><p>PLX swich 9733 (10b5:9733)</p></li> |
| <li><p>PMC 8546 swtich (11f8:8546)</p></li> |
| <li><p>NVMe adapter (1c58:0023)</p></li> |
| </ul> |
| <p>This fixes the issue by overriding the PCI slot presence bit with |
| PCIe link state bit.</p> |
| </li> |
| <li><p>hw/phb4: Locate AER capability position if necessary</p></li> |
| <li><p>core/pci: Disable surprise hotplug on root port</p></li> |
| <li><p>core/pci: Ignore PCI slot capability on root port</p> |
| <p>We are creating PCI slot on root port, where the PCI slot isn’t |
| supported from hardware. For this case, we shouldn’t read the PCI |
| slot capability from hardware. When bogus data returned from the |
| hardware, we will attempt to the PCI slot’s power state or enable |
| surprise hotplug functionality. All of them can’t be accomplished |
| without hardware support.</p> |
| <p>This leaves the PCI slot’s capability list 0 if PCICAP_EXP_CAP_SLOT |
| isn’t set in hardware (pcie_cap + 0x2). Otherwise, the PCI slot’s |
| capability list is retrieved from hardware (pcie_cap + 0x14).</p> |
| </li> |
| <li><p>phb4: Default to PCIe GEN2 on DD1</p> |
| <p>Default to PCIe GEN2 link speeds on DD1 for stability.</p> |
| <p>Can be overridden using nvram pcie-max-link-speed=4 parameter.</p> |
| </li> |
| <li><p>phb3/4: Set max link speed via nvram</p> |
| <p>This adds an nvram parameter pcie-max-link-speed to configure the max |
| speed of the pcie link. This can be set from the petitboot prompt |
| using:</p> |
| <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">nvram</span> <span class="o">-</span><span class="n">p</span> <span class="n">ibm</span><span class="p">,</span><span class="n">skiboot</span> <span class="o">--</span><span class="n">update</span><span class="o">-</span><span class="n">config</span> <span class="n">pcie</span><span class="o">-</span><span class="nb">max</span><span class="o">-</span><span class="n">link</span><span class="o">-</span><span class="n">speed</span><span class="o">=</span><span class="mi">4</span> |
| </pre></div> |
| </div> |
| <p>This takes preference over anything set in the device tree and is |
| global to all PHBs.</p> |
| </li> |
| </ul> |
| </section> |
| <section id="tests"> |
| <h2>Tests<a class="headerlink" href="#tests" title="Link to this heading">¶</a></h2> |
| <ul> |
| <li><p>Mambo/Qemu boot tests: expect (and fail) on checkstop</p> |
| <p>This allows us to fail a lot faster if we checkstop</p> |
| </li> |
| </ul> |
| </section> |
| </section> |
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| <h3><a href="../index.html">Table of Contents</a></h3> |
| <ul> |
| <li><a class="reference internal" href="#">skiboot-5.5.0-rc2</a><ul> |
| <li><a class="reference internal" href="#nvlink2">NVLINK2</a></li> |
| <li><a class="reference internal" href="#power9">POWER9</a></li> |
| <li><a class="reference internal" href="#pci">PCI</a></li> |
| <li><a class="reference internal" href="#tests">Tests</a></li> |
| </ul> |
| </li> |
| </ul> |
| |
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