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| <tr><td class="title">LCOV - code coverage report</td></tr> |
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| <td width="10%" class="headerItem">Current view:</td> |
| <td width="10%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">include</a> - processor.h<span style="font-size: 80%;"> (source / <a href="processor.h.func-c.html">functions</a>)</span></td> |
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| <td width="5%"></td> |
| <td width="5%" class="headerCovTableHead">Coverage</td> |
| <td width="5%" class="headerCovTableHead" title="Covered + Uncovered code">Total</td> |
| <td width="5%" class="headerCovTableHead" title="Exercised code only">Hit</td> |
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| <td class="headerItem">Test:</td> |
| <td class="headerValue">skiboot.info</td> |
| <td></td> |
| <td class="headerItem">Lines:</td> |
| <td class="headerCovTableEntryLo">33.3 %</td> |
| <td class="headerCovTableEntry">12</td> |
| <td class="headerCovTableEntry">4</td> |
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| <tr> |
| <td class="headerItem">Test Date:</td> |
| <td class="headerValue">2025-06-27 16:54:26</td> |
| <td></td> |
| <td class="headerItem">Functions:</td> |
| <td class="headerCovTableEntryLo">50.0 %</td> |
| <td class="headerCovTableEntry">2</td> |
| <td class="headerCovTableEntry">1</td> |
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| <td class="headerItem">Branches:</td> |
| <td class="headerCovTableEntryHi">-</td> |
| <td class="headerCovTableEntry">0</td> |
| <td class="headerCovTableEntry">0</td> |
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| <pre class="sourceHeading"> Branch data Line data Source code</pre> |
| <pre class="source"> |
| <span id="L1"><span class="lineNum"> 1</span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</span> |
| <span id="L2"><span class="lineNum"> 2</span> : : /* Copyright 2013-2019 IBM Corp. */</span> |
| <span id="L3"><span class="lineNum"> 3</span> : : </span> |
| <span id="L4"><span class="lineNum"> 4</span> : : #ifndef __PROCESSOR_H</span> |
| <span id="L5"><span class="lineNum"> 5</span> : : #define __PROCESSOR_H</span> |
| <span id="L6"><span class="lineNum"> 6</span> : : </span> |
| <span id="L7"><span class="lineNum"> 7</span> : : #include <bitutils.h></span> |
| <span id="L8"><span class="lineNum"> 8</span> : : </span> |
| <span id="L9"><span class="lineNum"> 9</span> : : /* MSR bits */</span> |
| <span id="L10"><span class="lineNum"> 10</span> : : #define MSR_SF PPC_BIT(0) /* 64-bit mode */</span> |
| <span id="L11"><span class="lineNum"> 11</span> : : #define MSR_HV PPC_BIT(3) /* Hypervisor mode */</span> |
| <span id="L12"><span class="lineNum"> 12</span> : : #define MSR_VEC PPC_BIT(38) /* VMX enable */</span> |
| <span id="L13"><span class="lineNum"> 13</span> : : #define MSR_VSX PPC_BIT(40) /* VSX enable */</span> |
| <span id="L14"><span class="lineNum"> 14</span> : : #define MSR_S PPC_BIT(41) /* Secure mode */</span> |
| <span id="L15"><span class="lineNum"> 15</span> : : #define MSR_EE PPC_BIT(48) /* External Int. Enable */</span> |
| <span id="L16"><span class="lineNum"> 16</span> : : #define MSR_PR PPC_BIT(49) /* Problem state */</span> |
| <span id="L17"><span class="lineNum"> 17</span> : : #define MSR_FP PPC_BIT(50) /* Floating Point Enable */</span> |
| <span id="L18"><span class="lineNum"> 18</span> : : #define MSR_ME PPC_BIT(51) /* Machine Check Enable */</span> |
| <span id="L19"><span class="lineNum"> 19</span> : : #define MSR_FE0 PPC_BIT(52) /* FP Exception 0 */</span> |
| <span id="L20"><span class="lineNum"> 20</span> : : #define MSR_SE PPC_BIT(53) /* Step enable */</span> |
| <span id="L21"><span class="lineNum"> 21</span> : : #define MSR_BE PPC_BIT(54) /* Branch trace enable */</span> |
| <span id="L22"><span class="lineNum"> 22</span> : : #define MSR_FE1 PPC_BIT(55) /* FP Exception 1 */</span> |
| <span id="L23"><span class="lineNum"> 23</span> : : #define MSR_IR PPC_BIT(58) /* Instructions reloc */</span> |
| <span id="L24"><span class="lineNum"> 24</span> : : #define MSR_DR PPC_BIT(59) /* Data reloc */</span> |
| <span id="L25"><span class="lineNum"> 25</span> : : #define MSR_PMM PPC_BIT(61) /* Perf Monitor */</span> |
| <span id="L26"><span class="lineNum"> 26</span> : : #define MSR_RI PPC_BIT(62) /* Recoverable Interrupt */</span> |
| <span id="L27"><span class="lineNum"> 27</span> : : #define MSR_LE PPC_BIT(63) /* Little Endian */</span> |
| <span id="L28"><span class="lineNum"> 28</span> : : </span> |
| <span id="L29"><span class="lineNum"> 29</span> : : /* PIR */</span> |
| <span id="L30"><span class="lineNum"> 30</span> : : #define SPR_PIR_P10_MASK 0x7fff /* Mask of implemented bits */</span> |
| <span id="L31"><span class="lineNum"> 31</span> : : #define SPR_PIR_P9_MASK 0x7fff /* Mask of implemented bits */</span> |
| <span id="L32"><span class="lineNum"> 32</span> : : #define SPR_PIR_P8_MASK 0x1fff /* Mask of implemented bits */</span> |
| <span id="L33"><span class="lineNum"> 33</span> : : </span> |
| <span id="L34"><span class="lineNum"> 34</span> : : /* SPR register definitions */</span> |
| <span id="L35"><span class="lineNum"> 35</span> : : #define SPR_DSCR 0x011 /* RW: Data stream control reg */</span> |
| <span id="L36"><span class="lineNum"> 36</span> : : #define SPR_DSISR 0x012 /* RW: Data storage interrupt status reg */</span> |
| <span id="L37"><span class="lineNum"> 37</span> : : #define SPR_DAR 0x013 /* RW: Data address reg */</span> |
| <span id="L38"><span class="lineNum"> 38</span> : : #define SPR_DEC 0x016 /* RW: Decrement Register */</span> |
| <span id="L39"><span class="lineNum"> 39</span> : : #define SPR_SDR1 0x019</span> |
| <span id="L40"><span class="lineNum"> 40</span> : : #define SPR_SRR0 0x01a /* RW: Exception save/restore reg 0 */</span> |
| <span id="L41"><span class="lineNum"> 41</span> : : #define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */</span> |
| <span id="L42"><span class="lineNum"> 42</span> : : #define SPR_CFAR 0x01c /* RW: Come From Address Register */</span> |
| <span id="L43"><span class="lineNum"> 43</span> : : #define SPR_AMR 0x01d /* RW: Authority Mask Register */</span> |
| <span id="L44"><span class="lineNum"> 44</span> : : #define SPR_IAMR 0x03d /* RW: Instruction Authority Mask Register */</span> |
| <span id="L45"><span class="lineNum"> 45</span> : : #define SPR_RPR 0x0ba /* RW: Relative Priority Register */</span> |
| <span id="L46"><span class="lineNum"> 46</span> : : #define SPR_TBRL 0x10c /* RO: Timebase low */</span> |
| <span id="L47"><span class="lineNum"> 47</span> : : #define SPR_TBRU 0x10d /* RO: Timebase high */</span> |
| <span id="L48"><span class="lineNum"> 48</span> : : #define SPR_SPRC 0x114 /* RW: Access to uArch SPRs (ex SCOMC) */</span> |
| <span id="L49"><span class="lineNum"> 49</span> : : #define SPR_SPRD 0x115 /* RW: Access to uArch SPRs (ex SCOMD) */</span> |
| <span id="L50"><span class="lineNum"> 50</span> : : #define SPR_SCOMC 0x114 /* RW: SCOM Control - old name of SPRC */</span> |
| <span id="L51"><span class="lineNum"> 51</span> : : #define SPR_SCOMD 0x115 /* RW: SCOM Data - old name of SPRD */</span> |
| <span id="L52"><span class="lineNum"> 52</span> : : #define SPR_TBWL 0x11c /* RW: Timebase low */</span> |
| <span id="L53"><span class="lineNum"> 53</span> : : #define SPR_TBWU 0x11d /* RW: Timebase high */</span> |
| <span id="L54"><span class="lineNum"> 54</span> : : #define SPR_TBU40 0x11e /* RW: Timebase Upper 40 bit */</span> |
| <span id="L55"><span class="lineNum"> 55</span> : : #define SPR_PVR 0x11f /* RO: Processor version register */</span> |
| <span id="L56"><span class="lineNum"> 56</span> : : #define SPR_HSPRG0 0x130 /* RW: Hypervisor scratch 0 */</span> |
| <span id="L57"><span class="lineNum"> 57</span> : : #define SPR_HSPRG1 0x131 /* RW: Hypervisor scratch 1 */</span> |
| <span id="L58"><span class="lineNum"> 58</span> : : #define SPR_SPURR 0x134 /* RW: Scaled Processor Utilization Resource */</span> |
| <span id="L59"><span class="lineNum"> 59</span> : : #define SPR_PURR 0x135 /* RW: Processor Utilization Resource reg */</span> |
| <span id="L60"><span class="lineNum"> 60</span> : : #define SPR_HDEC 0x136 /* RW: Hypervisor Decrementer */</span> |
| <span id="L61"><span class="lineNum"> 61</span> : : #define SPR_HRMOR 0x139 /* RW: Hypervisor Real Mode Offset reg */</span> |
| <span id="L62"><span class="lineNum"> 62</span> : : #define SPR_HSRR0 0x13a /* RW: HV Exception save/restore reg 0 */</span> |
| <span id="L63"><span class="lineNum"> 63</span> : : #define SPR_HSRR1 0x13b /* RW: HV Exception save/restore reg 1 */</span> |
| <span id="L64"><span class="lineNum"> 64</span> : : #define SPR_TFMR 0x13d</span> |
| <span id="L65"><span class="lineNum"> 65</span> : : #define SPR_LPCR 0x13e</span> |
| <span id="L66"><span class="lineNum"> 66</span> : : #define SPR_HMER 0x150 /* Hypervisor Maintenance Exception */</span> |
| <span id="L67"><span class="lineNum"> 67</span> : : #define SPR_HMEER 0x151 /* HMER interrupt enable mask */</span> |
| <span id="L68"><span class="lineNum"> 68</span> : : #define SPR_PCR 0x152</span> |
| <span id="L69"><span class="lineNum"> 69</span> : : #define SPR_AMOR 0x15d</span> |
| <span id="L70"><span class="lineNum"> 70</span> : : #define SPR_USRR0 0x1fa /* RW: Ultravisor Save/Restore Register 0 */</span> |
| <span id="L71"><span class="lineNum"> 71</span> : : #define SPR_USRR1 0x1fb /* RW: Ultravisor Save/Restore Register 1 */</span> |
| <span id="L72"><span class="lineNum"> 72</span> : : #define SPR_SMFCTRL 0x1ff /* RW: Secure Memory Facility Control */</span> |
| <span id="L73"><span class="lineNum"> 73</span> : : #define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */</span> |
| <span id="L74"><span class="lineNum"> 74</span> : : #define SPR_PPR32 0x382</span> |
| <span id="L75"><span class="lineNum"> 75</span> : : #define SPR_TSCR 0x399</span> |
| <span id="L76"><span class="lineNum"> 76</span> : : #define SPR_HID0 0x3f0</span> |
| <span id="L77"><span class="lineNum"> 77</span> : : #define SPR_HID1 0x3f1</span> |
| <span id="L78"><span class="lineNum"> 78</span> : : #define SPR_HID2 0x3f8</span> |
| <span id="L79"><span class="lineNum"> 79</span> : : #define SPR_HID4 0x3f4</span> |
| <span id="L80"><span class="lineNum"> 80</span> : : #define SPR_HID5 0x3f6</span> |
| <span id="L81"><span class="lineNum"> 81</span> : : #define SPR_PIR 0x3ff /* RO: Processor Identification */</span> |
| <span id="L82"><span class="lineNum"> 82</span> : : </span> |
| <span id="L83"><span class="lineNum"> 83</span> : : /* Bits in SRR1 */</span> |
| <span id="L84"><span class="lineNum"> 84</span> : : </span> |
| <span id="L85"><span class="lineNum"> 85</span> : : #define SPR_SRR1_PM_WAKE_MASK 0x3c0000 /* PM wake reason for P8/9 */</span> |
| <span id="L86"><span class="lineNum"> 86</span> : : #define SPR_SRR1_PM_WAKE_SRESET 0x100000</span> |
| <span id="L87"><span class="lineNum"> 87</span> : : #define SPR_SRR1_PM_WAKE_MCE 0x3c0000 /* Use reserved value for MCE */</span> |
| <span id="L88"><span class="lineNum"> 88</span> : : </span> |
| <span id="L89"><span class="lineNum"> 89</span> : : /* Bits in LPCR */</span> |
| <span id="L90"><span class="lineNum"> 90</span> : : </span> |
| <span id="L91"><span class="lineNum"> 91</span> : : /* Powersave Exit Cause Enable is different on each generation */</span> |
| <span id="L92"><span class="lineNum"> 92</span> : : #define SPR_LPCR_P8_PECE PPC_BITMASK(47,51)</span> |
| <span id="L93"><span class="lineNum"> 93</span> : : #define SPR_LPCR_P8_PECE0 PPC_BIT(47) /* Wake on priv doorbell */</span> |
| <span id="L94"><span class="lineNum"> 94</span> : : #define SPR_LPCR_P8_PECE1 PPC_BIT(48) /* Wake on hv doorbell */</span> |
| <span id="L95"><span class="lineNum"> 95</span> : : #define SPR_LPCR_P8_PECE2 PPC_BIT(49) /* Wake on external interrupts */</span> |
| <span id="L96"><span class="lineNum"> 96</span> : : #define SPR_LPCR_P8_PECE3 PPC_BIT(50) /* Wake on decrementer */</span> |
| <span id="L97"><span class="lineNum"> 97</span> : : #define SPR_LPCR_P8_PECE4 PPC_BIT(51) /* Wake on MCs, HMIs, etc... */</span> |
| <span id="L98"><span class="lineNum"> 98</span> : : </span> |
| <span id="L99"><span class="lineNum"> 99</span> : : #define SPR_LPCR_P9_PECE (PPC_BITMASK(47,51) | PPC_BITMASK(17,17))</span> |
| <span id="L100"><span class="lineNum"> 100</span> : : #define SPR_LPCR_P9_PECEU0 PPC_BIT(17) /* Wake on HVI */</span> |
| <span id="L101"><span class="lineNum"> 101</span> : : #define SPR_LPCR_P9_PECEL0 PPC_BIT(47) /* Wake on priv doorbell */</span> |
| <span id="L102"><span class="lineNum"> 102</span> : : #define SPR_LPCR_P9_PECEL1 PPC_BIT(48) /* Wake on hv doorbell */</span> |
| <span id="L103"><span class="lineNum"> 103</span> : : #define SPR_LPCR_P9_PECEL2 PPC_BIT(49) /* Wake on external interrupts */</span> |
| <span id="L104"><span class="lineNum"> 104</span> : : #define SPR_LPCR_P9_PECEL3 PPC_BIT(50) /* Wake on decrementer */</span> |
| <span id="L105"><span class="lineNum"> 105</span> : : #define SPR_LPCR_P9_PECEL4 PPC_BIT(51) /* Wake on MCs, HMIs, etc... */</span> |
| <span id="L106"><span class="lineNum"> 106</span> : : #define SPR_LPCR_P9_LD PPC_BIT(46) /* Large decrementer mode bit */</span> |
| <span id="L107"><span class="lineNum"> 107</span> : : </span> |
| <span id="L108"><span class="lineNum"> 108</span> : : </span> |
| <span id="L109"><span class="lineNum"> 109</span> : : /* Bits in TFMR - control bits */</span> |
| <span id="L110"><span class="lineNum"> 110</span> : : #define SPR_TFMR_MAX_CYC_BET_STEPS PPC_BITMASK(0,7)</span> |
| <span id="L111"><span class="lineNum"> 111</span> : : #define SPR_TFMR_N_CLKS_PER_STEP PPC_BITMASK(8,9)</span> |
| <span id="L112"><span class="lineNum"> 112</span> : : #define SPR_TFMR_MASK_HMI PPC_BIT(10)</span> |
| <span id="L113"><span class="lineNum"> 113</span> : : #define SPR_TFMR_SYNC_BIT_SEL PPC_BITMASK(11,13)</span> |
| <span id="L114"><span class="lineNum"> 114</span> : : #define SPR_TFMR_TB_ECLIPZ PPC_BIT(14)</span> |
| <span id="L115"><span class="lineNum"> 115</span> : : #define SPR_TFMR_LOAD_TOD_MOD PPC_BIT(16)</span> |
| <span id="L116"><span class="lineNum"> 116</span> : : #define SPR_TFMR_MOVE_CHIP_TOD_TO_TB PPC_BIT(18)</span> |
| <span id="L117"><span class="lineNum"> 117</span> : : #define SPR_TFMR_CLEAR_TB_ERRORS PPC_BIT(24)</span> |
| <span id="L118"><span class="lineNum"> 118</span> : : /* Bits in TFMR - thread indep. status bits */</span> |
| <span id="L119"><span class="lineNum"> 119</span> : : #define SPR_TFMR_TFAC_XFER_ERROR PPC_BIT(25)</span> |
| <span id="L120"><span class="lineNum"> 120</span> : : #define SPR_TFMR_HDEC_PARITY_ERROR PPC_BIT(26)</span> |
| <span id="L121"><span class="lineNum"> 121</span> : : #define SPR_TFMR_TBST_CORRUPT PPC_BIT(27)</span> |
| <span id="L122"><span class="lineNum"> 122</span> : : #define SPR_TFMR_TBST_ENCODED PPC_BITMASK(28,31)</span> |
| <span id="L123"><span class="lineNum"> 123</span> : : #define SPR_TFMR_TBST_LAST PPC_BITMASK(32,35)</span> |
| <span id="L124"><span class="lineNum"> 124</span> : : #define SPR_TFMR_TB_ENABLED PPC_BIT(40)</span> |
| <span id="L125"><span class="lineNum"> 125</span> : : #define SPR_TFMR_TB_VALID PPC_BIT(41)</span> |
| <span id="L126"><span class="lineNum"> 126</span> : : #define SPR_TFMR_TB_SYNC_OCCURED PPC_BIT(42)</span> |
| <span id="L127"><span class="lineNum"> 127</span> : : #define SPR_TFMR_TB_MISSING_SYNC PPC_BIT(43)</span> |
| <span id="L128"><span class="lineNum"> 128</span> : : #define SPR_TFMR_TB_MISSING_STEP PPC_BIT(44)</span> |
| <span id="L129"><span class="lineNum"> 129</span> : : #define SPR_TFMR_TB_RESIDUE_ERR PPC_BIT(45)</span> |
| <span id="L130"><span class="lineNum"> 130</span> : : #define SPR_TFMR_FW_CONTROL_ERR PPC_BIT(46)</span> |
| <span id="L131"><span class="lineNum"> 131</span> : : #define SPR_TFMR_CHIP_TOD_STATUS PPC_BITMASK(47,50)</span> |
| <span id="L132"><span class="lineNum"> 132</span> : : #define SPR_TFMR_CHIP_TOD_INTERRUPT PPC_BIT(51)</span> |
| <span id="L133"><span class="lineNum"> 133</span> : : #define SPR_TFMR_CHIP_TOD_TIMEOUT PPC_BIT(54)</span> |
| <span id="L134"><span class="lineNum"> 134</span> : : #define SPR_TFMR_CHIP_TOD_PARITY_ERR PPC_BIT(56)</span> |
| <span id="L135"><span class="lineNum"> 135</span> : : /* Bits in TFMR - thread specific. status bits */</span> |
| <span id="L136"><span class="lineNum"> 136</span> : : #define SPR_TFMR_PURR_PARITY_ERR PPC_BIT(57)</span> |
| <span id="L137"><span class="lineNum"> 137</span> : : #define SPR_TFMR_SPURR_PARITY_ERR PPC_BIT(58)</span> |
| <span id="L138"><span class="lineNum"> 138</span> : : #define SPR_TFMR_DEC_PARITY_ERR PPC_BIT(59)</span> |
| <span id="L139"><span class="lineNum"> 139</span> : : #define SPR_TFMR_TFMR_CORRUPT PPC_BIT(60)</span> |
| <span id="L140"><span class="lineNum"> 140</span> : : #define SPR_TFMR_PURR_OVERFLOW PPC_BIT(61)</span> |
| <span id="L141"><span class="lineNum"> 141</span> : : #define SPR_TFMR_SPURR_OVERFLOW PPC_BIT(62)</span> |
| <span id="L142"><span class="lineNum"> 142</span> : : </span> |
| <span id="L143"><span class="lineNum"> 143</span> : : /* Bits in HMER/HMEER */</span> |
| <span id="L144"><span class="lineNum"> 144</span> : : #define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0)</span> |
| <span id="L145"><span class="lineNum"> 145</span> : : #define SPR_HMER_PROC_RECV_DONE PPC_BIT(2)</span> |
| <span id="L146"><span class="lineNum"> 146</span> : : #define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) /* Not P10 */</span> |
| <span id="L147"><span class="lineNum"> 147</span> : : #define SPR_HMER_TFAC_ERROR PPC_BIT(4)</span> |
| <span id="L148"><span class="lineNum"> 148</span> : : #define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) /* P9 */</span> |
| <span id="L149"><span class="lineNum"> 149</span> : : #define SPR_HMER_TFAC_SHADOW_XFER_ERROR PPC_BIT(5) /* P10 */</span> |
| <span id="L150"><span class="lineNum"> 150</span> : : #define SPR_HMER_SPURR_SCALE_LIMIT PPC_BIT(6) /* P10 */</span> |
| <span id="L151"><span class="lineNum"> 151</span> : : #define SPR_HMER_XSCOM_FAIL PPC_BIT(8)</span> |
| <span id="L152"><span class="lineNum"> 152</span> : : #define SPR_HMER_XSCOM_DONE PPC_BIT(9)</span> |
| <span id="L153"><span class="lineNum"> 153</span> : : #define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11)</span> |
| <span id="L154"><span class="lineNum"> 154</span> : : #define SPR_HMER_WARN_RISE PPC_BIT(14) /* Not P10 */</span> |
| <span id="L155"><span class="lineNum"> 155</span> : : #define SPR_HMER_WARN_FALL PPC_BIT(15) /* Not P10 */</span> |
| <span id="L156"><span class="lineNum"> 156</span> : : #define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16)</span> |
| <span id="L157"><span class="lineNum"> 157</span> : : #define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) /* Not P10 */</span> |
| <span id="L158"><span class="lineNum"> 158</span> : : #define SPR_HMER_THD_WAKE_BLOCKED_TM_SUSPEND PPC_BIT(17) /* Not P10 */</span> |
| <span id="L159"><span class="lineNum"> 159</span> : : #define SPR_HMER_P10_TRIG_FIR_HMI PPC_BIT(18)</span> |
| <span id="L160"><span class="lineNum"> 160</span> : : #define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) /* Not P10 */</span> |
| <span id="L161"><span class="lineNum"> 161</span> : : #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23)</span> |
| <span id="L162"><span class="lineNum"> 162</span> : : </span> |
| <span id="L163"><span class="lineNum"> 163</span> : : /*</span> |
| <span id="L164"><span class="lineNum"> 164</span> : : * HMEER: initial bits for HMI interrupt enable mask.</span> |
| <span id="L165"><span class="lineNum"> 165</span> : : * Per Dave Larson, never enable 8,9,21-23</span> |
| <span id="L166"><span class="lineNum"> 166</span> : : */</span> |
| <span id="L167"><span class="lineNum"> 167</span> : : #define SPR_HMEER_HMI_ENABLE_MASK (SPR_HMER_MALFUNCTION_ALERT |\</span> |
| <span id="L168"><span class="lineNum"> 168</span> : : SPR_HMER_HYP_RESOURCE_ERR |\</span> |
| <span id="L169"><span class="lineNum"> 169</span> : : SPR_HMER_PROC_RECV_DONE |\</span> |
| <span id="L170"><span class="lineNum"> 170</span> : : SPR_HMER_PROC_RECV_ERROR_MASKED |\</span> |
| <span id="L171"><span class="lineNum"> 171</span> : : SPR_HMER_TFAC_ERROR |\</span> |
| <span id="L172"><span class="lineNum"> 172</span> : : SPR_HMER_TFMR_PARITY_ERROR |\</span> |
| <span id="L173"><span class="lineNum"> 173</span> : : SPR_HMER_PROC_RECV_AGAIN)</span> |
| <span id="L174"><span class="lineNum"> 174</span> : : </span> |
| <span id="L175"><span class="lineNum"> 175</span> : : #define SPR_HMEER_P10_HMI_ENABLE_MASK (SPR_HMER_MALFUNCTION_ALERT |\</span> |
| <span id="L176"><span class="lineNum"> 176</span> : : SPR_HMER_PROC_RECV_DONE |\</span> |
| <span id="L177"><span class="lineNum"> 177</span> : : SPR_HMER_TFAC_ERROR |\</span> |
| <span id="L178"><span class="lineNum"> 178</span> : : SPR_HMER_TFAC_SHADOW_XFER_ERROR |\</span> |
| <span id="L179"><span class="lineNum"> 179</span> : : SPR_HMER_SPURR_SCALE_LIMIT |\</span> |
| <span id="L180"><span class="lineNum"> 180</span> : : SPR_HMER_PROC_RECV_AGAIN)</span> |
| <span id="L181"><span class="lineNum"> 181</span> : : </span> |
| <span id="L182"><span class="lineNum"> 182</span> : : /* Bits in HID0 */</span> |
| <span id="L183"><span class="lineNum"> 183</span> : : #define SPR_HID0_POWER8_4LPARMODE PPC_BIT(2)</span> |
| <span id="L184"><span class="lineNum"> 184</span> : : #define SPR_HID0_POWER8_2LPARMODE PPC_BIT(6)</span> |
| <span id="L185"><span class="lineNum"> 185</span> : : #define SPR_HID0_POWER8_DYNLPARDIS PPC_BIT(15)</span> |
| <span id="L186"><span class="lineNum"> 186</span> : : #define SPR_HID0_POWER8_HILE PPC_BIT(19)</span> |
| <span id="L187"><span class="lineNum"> 187</span> : : #define SPR_HID0_POWER9_HILE PPC_BIT(4)</span> |
| <span id="L188"><span class="lineNum"> 188</span> : : #define SPR_HID0_POWER10_HILE PPC_BIT(4)</span> |
| <span id="L189"><span class="lineNum"> 189</span> : : #define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31)</span> |
| <span id="L190"><span class="lineNum"> 190</span> : : #define SPR_HID0_POWER9_ENABLE_ATTN PPC_BIT(3)</span> |
| <span id="L191"><span class="lineNum"> 191</span> : : #define SPR_HID0_POWER10_ENABLE_ATTN PPC_BIT(3)</span> |
| <span id="L192"><span class="lineNum"> 192</span> : : #define SPR_HID0_POWER9_FLUSH_ICACHE PPC_BIT(2)</span> |
| <span id="L193"><span class="lineNum"> 193</span> : : #define SPR_HID0_POWER10_FLUSH_ICACHE PPC_BIT(2)</span> |
| <span id="L194"><span class="lineNum"> 194</span> : : #define SPR_HID0_POWER9_RADIX PPC_BIT(8)</span> |
| <span id="L195"><span class="lineNum"> 195</span> : : </span> |
| <span id="L196"><span class="lineNum"> 196</span> : : /* PVR bits */</span> |
| <span id="L197"><span class="lineNum"> 197</span> : : #define SPR_PVR_TYPE 0xffff0000</span> |
| <span id="L198"><span class="lineNum"> 198</span> : : #define SPR_PVR_CHIP_TYPE 0x0000f000</span> |
| <span id="L199"><span class="lineNum"> 199</span> : : #define SPR_PVR_VERS_MAJ 0x00000f00</span> |
| <span id="L200"><span class="lineNum"> 200</span> : : #define SPR_PVR_VERS_MIN 0x000000ff</span> |
| <span id="L201"><span class="lineNum"> 201</span> : : </span> |
| <span id="L202"><span class="lineNum"> 202</span> : : #define PVR_TYPE(_pvr) GETFIELD(SPR_PVR_TYPE, _pvr)</span> |
| <span id="L203"><span class="lineNum"> 203</span> : : #define PVR_CHIP_TYPE(_pvr) GETFIELD(SPR_PVR_CHIP_TYPE, _pvr)</span> |
| <span id="L204"><span class="lineNum"> 204</span> : : #define PVR_VERS_MAJ(_pvr) GETFIELD(SPR_PVR_VERS_MAJ, _pvr)</span> |
| <span id="L205"><span class="lineNum"> 205</span> : : #define PVR_VERS_MIN(_pvr) GETFIELD(SPR_PVR_VERS_MIN, _pvr)</span> |
| <span id="L206"><span class="lineNum"> 206</span> : : </span> |
| <span id="L207"><span class="lineNum"> 207</span> : : /* PVR definitions */</span> |
| <span id="L208"><span class="lineNum"> 208</span> : : #define PVR_TYPE_P8E 0x004b /* Murano */</span> |
| <span id="L209"><span class="lineNum"> 209</span> : : #define PVR_TYPE_P8 0x004d /* Venice */</span> |
| <span id="L210"><span class="lineNum"> 210</span> : : #define PVR_TYPE_P8NVL 0x004c /* Naples */</span> |
| <span id="L211"><span class="lineNum"> 211</span> : : #define PVR_TYPE_P9 0x004e</span> |
| <span id="L212"><span class="lineNum"> 212</span> : : #define PVR_TYPE_P9P 0x004f /* Axone */</span> |
| <span id="L213"><span class="lineNum"> 213</span> : : #define PVR_TYPE_P10 0x0080</span> |
| <span id="L214"><span class="lineNum"> 214</span> : : #define PVR_TYPE_P11 0x0082</span> |
| <span id="L215"><span class="lineNum"> 215</span> : : </span> |
| <span id="L216"><span class="lineNum"> 216</span> : : #ifdef __ASSEMBLY__</span> |
| <span id="L217"><span class="lineNum"> 217</span> : : </span> |
| <span id="L218"><span class="lineNum"> 218</span> : : /* Thread priority control opcodes */</span> |
| <span id="L219"><span class="lineNum"> 219</span> : : #define smt_low or 1,1,1</span> |
| <span id="L220"><span class="lineNum"> 220</span> : : #define smt_medium or 2,2,2</span> |
| <span id="L221"><span class="lineNum"> 221</span> : : #define smt_high or 3,3,3</span> |
| <span id="L222"><span class="lineNum"> 222</span> : : #define smt_medium_high or 5,5,5</span> |
| <span id="L223"><span class="lineNum"> 223</span> : : #define smt_medium_low or 6,6,6</span> |
| <span id="L224"><span class="lineNum"> 224</span> : : #define smt_extra_high or 7,7,7</span> |
| <span id="L225"><span class="lineNum"> 225</span> : : #define smt_very_low or 31,31,31</span> |
| <span id="L226"><span class="lineNum"> 226</span> : : #define smt_lowest smt_low ; smt_very_low</span> |
| <span id="L227"><span class="lineNum"> 227</span> : : </span> |
| <span id="L228"><span class="lineNum"> 228</span> : : #else /* __ASSEMBLY__ */</span> |
| <span id="L229"><span class="lineNum"> 229</span> : : </span> |
| <span id="L230"><span class="lineNum"> 230</span> : : #include <ccan/str/str.h></span> |
| <span id="L231"><span class="lineNum"> 231</span> : : #include <compiler.h></span> |
| <span id="L232"><span class="lineNum"> 232</span> : : #include <stdbool.h></span> |
| <span id="L233"><span class="lineNum"> 233</span> : : #include <stdint.h></span> |
| <span id="L234"><span class="lineNum"> 234</span> : : </span> |
| <span id="L235"><span class="lineNum"> 235</span> : : #define PPC_INST_NOP 0x60000000UL</span> |
| <span id="L236"><span class="lineNum"> 236</span> : : #define PPC_INST_TRAP 0x7fe00008UL</span> |
| <span id="L237"><span class="lineNum"> 237</span> : : </span> |
| <span id="L238"><span class="lineNum"> 238</span> : : #define RB(b) (((b) & 0x1f) << 11)</span> |
| <span id="L239"><span class="lineNum"> 239</span> : : #define MSGSND(b) stringify(.long 0x7c00019c | RB(b))</span> |
| <span id="L240"><span class="lineNum"> 240</span> : : #define MSGCLR(b) stringify(.long 0x7c0001dc | RB(b))</span> |
| <span id="L241"><span class="lineNum"> 241</span> : : #define MSGSYNC stringify(.long 0x7c0006ec)</span> |
| <span id="L242"><span class="lineNum"> 242</span> : : </span> |
| <span id="L243"><span class="lineNum"> 243</span> :<span class="tlaGNC tlaBgGNC"> 4 : static inline bool is_power9n(uint32_t version)</span></span> |
| <span id="L244"><span class="lineNum"> 244</span> : : {</span> |
| <span id="L245"><span class="lineNum"> 245</span> :<span class="tlaGNC"> 4 : if (PVR_TYPE(version) != PVR_TYPE_P9)</span></span> |
| <span id="L246"><span class="lineNum"> 246</span> :<span class="tlaUNC tlaBgUNC"> 0 : return false;</span></span> |
| <span id="L247"><span class="lineNum"> 247</span> : : /*</span> |
| <span id="L248"><span class="lineNum"> 248</span> : : * Bit 13 tells us:</span> |
| <span id="L249"><span class="lineNum"> 249</span> : : * 0 = Scale out (aka Nimbus)</span> |
| <span id="L250"><span class="lineNum"> 250</span> : : * 1 = Scale up (aka Cumulus)</span> |
| <span id="L251"><span class="lineNum"> 251</span> : : */</span> |
| <span id="L252"><span class="lineNum"> 252</span> :<span class="tlaGNC tlaBgGNC"> 4 : if ((version >> 13) & 1)</span></span> |
| <span id="L253"><span class="lineNum"> 253</span> :<span class="tlaUNC tlaBgUNC"> 0 : return false;</span></span> |
| <span id="L254"><span class="lineNum"> 254</span> :<span class="tlaGNC tlaBgGNC"> 4 : return true;</span></span> |
| <span id="L255"><span class="lineNum"> 255</span> : : }</span> |
| <span id="L256"><span class="lineNum"> 256</span> : : </span> |
| <span id="L257"><span class="lineNum"> 257</span> : : static inline bool is_fused_core(uint32_t version)</span> |
| <span id="L258"><span class="lineNum"> 258</span> : : {</span> |
| <span id="L259"><span class="lineNum"> 259</span> : : if (PVR_TYPE(version) == PVR_TYPE_P9) {</span> |
| <span id="L260"><span class="lineNum"> 260</span> : : switch(PVR_CHIP_TYPE(version)) {</span> |
| <span id="L261"><span class="lineNum"> 261</span> : : case 0:</span> |
| <span id="L262"><span class="lineNum"> 262</span> : : case 2:</span> |
| <span id="L263"><span class="lineNum"> 263</span> : : return true;</span> |
| <span id="L264"><span class="lineNum"> 264</span> : : default:</span> |
| <span id="L265"><span class="lineNum"> 265</span> : : return false;</span> |
| <span id="L266"><span class="lineNum"> 266</span> : : }</span> |
| <span id="L267"><span class="lineNum"> 267</span> : : </span> |
| <span id="L268"><span class="lineNum"> 268</span> : : } else if(PVR_TYPE(version) == PVR_TYPE_P10) {</span> |
| <span id="L269"><span class="lineNum"> 269</span> : : if(PVR_CHIP_TYPE(version) & 0x01)</span> |
| <span id="L270"><span class="lineNum"> 270</span> : : return false;</span> |
| <span id="L271"><span class="lineNum"> 271</span> : : else</span> |
| <span id="L272"><span class="lineNum"> 272</span> : : return true;</span> |
| <span id="L273"><span class="lineNum"> 273</span> : : } else if (PVR_TYPE(version) == PVR_TYPE_P11) {</span> |
| <span id="L274"><span class="lineNum"> 274</span> : : if (PVR_CHIP_TYPE(version) & 0x01)</span> |
| <span id="L275"><span class="lineNum"> 275</span> : : return false;</span> |
| <span id="L276"><span class="lineNum"> 276</span> : : else</span> |
| <span id="L277"><span class="lineNum"> 277</span> : : return true;</span> |
| <span id="L278"><span class="lineNum"> 278</span> : : } else</span> |
| <span id="L279"><span class="lineNum"> 279</span> : : return false;</span> |
| <span id="L280"><span class="lineNum"> 280</span> : : }</span> |
| <span id="L281"><span class="lineNum"> 281</span> : : </span> |
| <span id="L282"><span class="lineNum"> 282</span> :<span class="tlaUNC tlaBgUNC"> 0 : static inline bool is_power9c(uint32_t version) </span></span> |
| <span id="L283"><span class="lineNum"> 283</span> : : {</span> |
| <span id="L284"><span class="lineNum"> 284</span> : : </span> |
| <span id="L285"><span class="lineNum"> 285</span> :<span class="tlaUNC"> 0 : if (PVR_TYPE(version) != PVR_TYPE_P9)</span></span> |
| <span id="L286"><span class="lineNum"> 286</span> :<span class="tlaUNC"> 0 : return false;</span></span> |
| <span id="L287"><span class="lineNum"> 287</span> : : /*</span> |
| <span id="L288"><span class="lineNum"> 288</span> : : * Bit 13 tells us:</span> |
| <span id="L289"><span class="lineNum"> 289</span> : : * 0 = Scale out (aka Nimbus)</span> |
| <span id="L290"><span class="lineNum"> 290</span> : : * 1 = Scale up (aka Cumulus)</span> |
| <span id="L291"><span class="lineNum"> 291</span> : : */</span> |
| <span id="L292"><span class="lineNum"> 292</span> :<span class="tlaUNC"> 0 : if (!((version >> 13) & 1))</span></span> |
| <span id="L293"><span class="lineNum"> 293</span> :<span class="tlaUNC"> 0 : return false;</span></span> |
| <span id="L294"><span class="lineNum"> 294</span> :<span class="tlaUNC"> 0 : return true;</span></span> |
| <span id="L295"><span class="lineNum"> 295</span> : : }</span> |
| <span id="L296"><span class="lineNum"> 296</span> : : </span> |
| <span id="L297"><span class="lineNum"> 297</span> : : #ifndef __TEST__</span> |
| <span id="L298"><span class="lineNum"> 298</span> : : </span> |
| <span id="L299"><span class="lineNum"> 299</span> : : /* POWER9 and above only */</span> |
| <span id="L300"><span class="lineNum"> 300</span> : : static inline void flush_erat(void)</span> |
| <span id="L301"><span class="lineNum"> 301</span> : : {</span> |
| <span id="L302"><span class="lineNum"> 302</span> : : asm volatile("slbia 7");</span> |
| <span id="L303"><span class="lineNum"> 303</span> : : }</span> |
| <span id="L304"><span class="lineNum"> 304</span> : : </span> |
| <span id="L305"><span class="lineNum"> 305</span> : : /*</span> |
| <span id="L306"><span class="lineNum"> 306</span> : : * SMT priority</span> |
| <span id="L307"><span class="lineNum"> 307</span> : : */</span> |
| <span id="L308"><span class="lineNum"> 308</span> : : </span> |
| <span id="L309"><span class="lineNum"> 309</span> : : static inline void smt_low(void) { asm volatile("or 1,1,1"); }</span> |
| <span id="L310"><span class="lineNum"> 310</span> : : static inline void smt_medium(void) { asm volatile("or 2,2,2"); }</span> |
| <span id="L311"><span class="lineNum"> 311</span> : : static inline void smt_high(void) { asm volatile("or 3,3,3"); }</span> |
| <span id="L312"><span class="lineNum"> 312</span> : : static inline void smt_medium_high(void){ asm volatile("or 5,5,5"); }</span> |
| <span id="L313"><span class="lineNum"> 313</span> : : static inline void smt_medium_low(void) { asm volatile("or 6,6,6"); }</span> |
| <span id="L314"><span class="lineNum"> 314</span> : : static inline void smt_extra_high(void) { asm volatile("or 7,7,7"); }</span> |
| <span id="L315"><span class="lineNum"> 315</span> : : static inline void smt_very_low(void) { asm volatile("or 31,31,31"); }</span> |
| <span id="L316"><span class="lineNum"> 316</span> : : static inline void smt_lowest(void) { smt_low(); smt_very_low(); }</span> |
| <span id="L317"><span class="lineNum"> 317</span> : : </span> |
| <span id="L318"><span class="lineNum"> 318</span> : : /*</span> |
| <span id="L319"><span class="lineNum"> 319</span> : : * SPR access functions</span> |
| <span id="L320"><span class="lineNum"> 320</span> : : */</span> |
| <span id="L321"><span class="lineNum"> 321</span> : : </span> |
| <span id="L322"><span class="lineNum"> 322</span> : : static inline unsigned long mfmsr(void)</span> |
| <span id="L323"><span class="lineNum"> 323</span> : : {</span> |
| <span id="L324"><span class="lineNum"> 324</span> : : unsigned long val;</span> |
| <span id="L325"><span class="lineNum"> 325</span> : : </span> |
| <span id="L326"><span class="lineNum"> 326</span> : : asm volatile("mfmsr %0" : "=r"(val) : : "memory");</span> |
| <span id="L327"><span class="lineNum"> 327</span> : : return val;</span> |
| <span id="L328"><span class="lineNum"> 328</span> : : }</span> |
| <span id="L329"><span class="lineNum"> 329</span> : : </span> |
| <span id="L330"><span class="lineNum"> 330</span> : : static inline void mtmsr(unsigned long val)</span> |
| <span id="L331"><span class="lineNum"> 331</span> : : {</span> |
| <span id="L332"><span class="lineNum"> 332</span> : : asm volatile("mtmsr %0" : : "r"(val) : "memory");</span> |
| <span id="L333"><span class="lineNum"> 333</span> : : }</span> |
| <span id="L334"><span class="lineNum"> 334</span> : : </span> |
| <span id="L335"><span class="lineNum"> 335</span> : : static inline void mtmsrd(unsigned long val, int l)</span> |
| <span id="L336"><span class="lineNum"> 336</span> : : {</span> |
| <span id="L337"><span class="lineNum"> 337</span> : : asm volatile("mtmsrd %0,%1" : : "r"(val), "i"(l) : "memory");</span> |
| <span id="L338"><span class="lineNum"> 338</span> : : }</span> |
| <span id="L339"><span class="lineNum"> 339</span> : : </span> |
| <span id="L340"><span class="lineNum"> 340</span> : : static inline __attribute__((always_inline))</span> |
| <span id="L341"><span class="lineNum"> 341</span> : : unsigned long mfspr(const unsigned int spr)</span> |
| <span id="L342"><span class="lineNum"> 342</span> : : {</span> |
| <span id="L343"><span class="lineNum"> 343</span> : : unsigned long val;</span> |
| <span id="L344"><span class="lineNum"> 344</span> : : </span> |
| <span id="L345"><span class="lineNum"> 345</span> : : asm volatile("mfspr %0,%1" : "=r"(val) : "i"(spr) : "memory");</span> |
| <span id="L346"><span class="lineNum"> 346</span> : : return val;</span> |
| <span id="L347"><span class="lineNum"> 347</span> : : }</span> |
| <span id="L348"><span class="lineNum"> 348</span> : : </span> |
| <span id="L349"><span class="lineNum"> 349</span> : : static inline __attribute__((always_inline))</span> |
| <span id="L350"><span class="lineNum"> 350</span> : : void mtspr(const unsigned int spr, unsigned long val)</span> |
| <span id="L351"><span class="lineNum"> 351</span> : : {</span> |
| <span id="L352"><span class="lineNum"> 352</span> : : asm volatile("mtspr %0,%1" : : "i"(spr), "r"(val) : "memory");</span> |
| <span id="L353"><span class="lineNum"> 353</span> : : }</span> |
| <span id="L354"><span class="lineNum"> 354</span> : : </span> |
| <span id="L355"><span class="lineNum"> 355</span> : : /* Helpers for special sequences needed by some registers */</span> |
| <span id="L356"><span class="lineNum"> 356</span> : : extern void set_hid0(unsigned long hid0);</span> |
| <span id="L357"><span class="lineNum"> 357</span> : : extern void trigger_attn(void);</span> |
| <span id="L358"><span class="lineNum"> 358</span> : : </span> |
| <span id="L359"><span class="lineNum"> 359</span> : : /*</span> |
| <span id="L360"><span class="lineNum"> 360</span> : : * Barriers</span> |
| <span id="L361"><span class="lineNum"> 361</span> : : */</span> |
| <span id="L362"><span class="lineNum"> 362</span> : : </span> |
| <span id="L363"><span class="lineNum"> 363</span> : : static inline void eieio(void)</span> |
| <span id="L364"><span class="lineNum"> 364</span> : : {</span> |
| <span id="L365"><span class="lineNum"> 365</span> : : asm volatile("eieio" : : : "memory");</span> |
| <span id="L366"><span class="lineNum"> 366</span> : : }</span> |
| <span id="L367"><span class="lineNum"> 367</span> : : </span> |
| <span id="L368"><span class="lineNum"> 368</span> : : static inline void sync(void)</span> |
| <span id="L369"><span class="lineNum"> 369</span> : : {</span> |
| <span id="L370"><span class="lineNum"> 370</span> : : asm volatile("sync" : : : "memory");</span> |
| <span id="L371"><span class="lineNum"> 371</span> : : }</span> |
| <span id="L372"><span class="lineNum"> 372</span> : : </span> |
| <span id="L373"><span class="lineNum"> 373</span> : : static inline void lwsync(void)</span> |
| <span id="L374"><span class="lineNum"> 374</span> : : {</span> |
| <span id="L375"><span class="lineNum"> 375</span> : : asm volatile("lwsync" : : : "memory");</span> |
| <span id="L376"><span class="lineNum"> 376</span> : : }</span> |
| <span id="L377"><span class="lineNum"> 377</span> : : </span> |
| <span id="L378"><span class="lineNum"> 378</span> : : static inline void isync(void)</span> |
| <span id="L379"><span class="lineNum"> 379</span> : : {</span> |
| <span id="L380"><span class="lineNum"> 380</span> : : asm volatile("isync" : : : "memory");</span> |
| <span id="L381"><span class="lineNum"> 381</span> : : }</span> |
| <span id="L382"><span class="lineNum"> 382</span> : : </span> |
| <span id="L383"><span class="lineNum"> 383</span> : : </span> |
| <span id="L384"><span class="lineNum"> 384</span> : : /*</span> |
| <span id="L385"><span class="lineNum"> 385</span> : : * Cache sync</span> |
| <span id="L386"><span class="lineNum"> 386</span> : : */</span> |
| <span id="L387"><span class="lineNum"> 387</span> : : static inline void sync_icache(void)</span> |
| <span id="L388"><span class="lineNum"> 388</span> : : {</span> |
| <span id="L389"><span class="lineNum"> 389</span> : : asm volatile("sync; icbi 0,%0; sync; isync" : : "r" (0) : "memory");</span> |
| <span id="L390"><span class="lineNum"> 390</span> : : }</span> |
| <span id="L391"><span class="lineNum"> 391</span> : : </span> |
| <span id="L392"><span class="lineNum"> 392</span> : : /*</span> |
| <span id="L393"><span class="lineNum"> 393</span> : : * Doorbells</span> |
| <span id="L394"><span class="lineNum"> 394</span> : : */</span> |
| <span id="L395"><span class="lineNum"> 395</span> : : static inline void msgclr(void)</span> |
| <span id="L396"><span class="lineNum"> 396</span> : : {</span> |
| <span id="L397"><span class="lineNum"> 397</span> : : uint64_t rb = (0x05 << (63-36));</span> |
| <span id="L398"><span class="lineNum"> 398</span> : : asm volatile(MSGCLR(%0) : : "r"(rb));</span> |
| <span id="L399"><span class="lineNum"> 399</span> : : }</span> |
| <span id="L400"><span class="lineNum"> 400</span> : : </span> |
| <span id="L401"><span class="lineNum"> 401</span> : : static inline void p9_dbell_receive(void)</span> |
| <span id="L402"><span class="lineNum"> 402</span> : : {</span> |
| <span id="L403"><span class="lineNum"> 403</span> : : uint64_t rb = (0x05 << (63-36));</span> |
| <span id="L404"><span class="lineNum"> 404</span> : : asm volatile(MSGCLR(%0) ";"</span> |
| <span id="L405"><span class="lineNum"> 405</span> : : MSGSYNC ";"</span> |
| <span id="L406"><span class="lineNum"> 406</span> : : "lwsync"</span> |
| <span id="L407"><span class="lineNum"> 407</span> : : : : "r"(rb));</span> |
| <span id="L408"><span class="lineNum"> 408</span> : : }</span> |
| <span id="L409"><span class="lineNum"> 409</span> : : </span> |
| <span id="L410"><span class="lineNum"> 410</span> : : static inline void p9_dbell_send(uint32_t pir)</span> |
| <span id="L411"><span class="lineNum"> 411</span> : : {</span> |
| <span id="L412"><span class="lineNum"> 412</span> : : uint64_t rb = (0x05 << (63-36)) | pir;</span> |
| <span id="L413"><span class="lineNum"> 413</span> : : asm volatile("sync ;"</span> |
| <span id="L414"><span class="lineNum"> 414</span> : : MSGSND(%0)</span> |
| <span id="L415"><span class="lineNum"> 415</span> : : : : "r"(rb));</span> |
| <span id="L416"><span class="lineNum"> 416</span> : : }</span> |
| <span id="L417"><span class="lineNum"> 417</span> : : </span> |
| <span id="L418"><span class="lineNum"> 418</span> : : /*</span> |
| <span id="L419"><span class="lineNum"> 419</span> : : * Byteswap load/stores</span> |
| <span id="L420"><span class="lineNum"> 420</span> : : */</span> |
| <span id="L421"><span class="lineNum"> 421</span> : : </span> |
| <span id="L422"><span class="lineNum"> 422</span> : : static inline uint16_t ld_le16(const uint16_t *addr)</span> |
| <span id="L423"><span class="lineNum"> 423</span> : : {</span> |
| <span id="L424"><span class="lineNum"> 424</span> : : uint16_t val;</span> |
| <span id="L425"><span class="lineNum"> 425</span> : : asm volatile("lhbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));</span> |
| <span id="L426"><span class="lineNum"> 426</span> : : return val;</span> |
| <span id="L427"><span class="lineNum"> 427</span> : : }</span> |
| <span id="L428"><span class="lineNum"> 428</span> : : </span> |
| <span id="L429"><span class="lineNum"> 429</span> : : static inline uint32_t ld_le32(const uint32_t *addr)</span> |
| <span id="L430"><span class="lineNum"> 430</span> : : {</span> |
| <span id="L431"><span class="lineNum"> 431</span> : : uint32_t val;</span> |
| <span id="L432"><span class="lineNum"> 432</span> : : asm volatile("lwbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));</span> |
| <span id="L433"><span class="lineNum"> 433</span> : : return val;</span> |
| <span id="L434"><span class="lineNum"> 434</span> : : }</span> |
| <span id="L435"><span class="lineNum"> 435</span> : : </span> |
| <span id="L436"><span class="lineNum"> 436</span> : : static inline void st_le16(uint16_t *addr, uint16_t val)</span> |
| <span id="L437"><span class="lineNum"> 437</span> : : {</span> |
| <span id="L438"><span class="lineNum"> 438</span> : : asm volatile("sthbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));</span> |
| <span id="L439"><span class="lineNum"> 439</span> : : }</span> |
| <span id="L440"><span class="lineNum"> 440</span> : : </span> |
| <span id="L441"><span class="lineNum"> 441</span> : : static inline void st_le32(uint32_t *addr, uint32_t val)</span> |
| <span id="L442"><span class="lineNum"> 442</span> : : {</span> |
| <span id="L443"><span class="lineNum"> 443</span> : : asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));</span> |
| <span id="L444"><span class="lineNum"> 444</span> : : }</span> |
| <span id="L445"><span class="lineNum"> 445</span> : : </span> |
| <span id="L446"><span class="lineNum"> 446</span> : : #endif /* __TEST__ */</span> |
| <span id="L447"><span class="lineNum"> 447</span> : : </span> |
| <span id="L448"><span class="lineNum"> 448</span> : : #endif /* __ASSEMBLY__ */</span> |
| <span id="L449"><span class="lineNum"> 449</span> : : </span> |
| <span id="L450"><span class="lineNum"> 450</span> : : #endif /* __PROCESSOR_H */</span> |
| </pre> |
| </td> |
| </tr> |
| </table> |
| <br> |
| |
| <table width="100%" border=0 cellspacing=0 cellpadding=0> |
| <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr> |
| <tr><td class="versionInfo">Generated by: <a href="https://github.com//linux-test-project/lcov" target="_parent">LCOV version 2.0-1</a></td></tr> |
| </table> |
| <br> |
| |
| </body> |
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