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| <pre class="sourceHeading"> Branch data Line data Source code</pre> |
| <pre class="source"> |
| <span id="L1"><span class="lineNum"> 1</span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</span> |
| <span id="L2"><span class="lineNum"> 2</span> : : /* Copyright 2013-2019 IBM Corp. */</span> |
| <span id="L3"><span class="lineNum"> 3</span> : : </span> |
| <span id="L4"><span class="lineNum"> 4</span> : : #ifndef __CHIP_H</span> |
| <span id="L5"><span class="lineNum"> 5</span> : : #define __CHIP_H</span> |
| <span id="L6"><span class="lineNum"> 6</span> : : </span> |
| <span id="L7"><span class="lineNum"> 7</span> : : #include <stdint.h></span> |
| <span id="L8"><span class="lineNum"> 8</span> : : #include <lock.h></span> |
| <span id="L9"><span class="lineNum"> 9</span> : : </span> |
| <span id="L10"><span class="lineNum"> 10</span> : : #include <ccan/list/list.h></span> |
| <span id="L11"><span class="lineNum"> 11</span> : : </span> |
| <span id="L12"><span class="lineNum"> 12</span> : : /*</span> |
| <span id="L13"><span class="lineNum"> 13</span> : : * Note on chip IDs:</span> |
| <span id="L14"><span class="lineNum"> 14</span> : : *</span> |
| <span id="L15"><span class="lineNum"> 15</span> : : * We carry a "chip_id" around, in the cpu_thread, but also as</span> |
| <span id="L16"><span class="lineNum"> 16</span> : : * ibm,chip-id properties.</span> |
| <span id="L17"><span class="lineNum"> 17</span> : : *</span> |
| <span id="L18"><span class="lineNum"> 18</span> : : * This ID is the HW fabric ID of a chip based on the XSCOM numbering,</span> |
| <span id="L19"><span class="lineNum"> 19</span> : : * also known as "GCID" (Global Chip ID).</span> |
| <span id="L20"><span class="lineNum"> 20</span> : : *</span> |
| <span id="L21"><span class="lineNum"> 21</span> : : * The format of this number is different between chip generations and care must</span> |
| <span id="L22"><span class="lineNum"> 22</span> : : * be taken when trying to convert between this chip ID and some other</span> |
| <span id="L23"><span class="lineNum"> 23</span> : : * representation such as PIR values, interrupt-server numbers etc... :</span> |
| <span id="L24"><span class="lineNum"> 24</span> : : *</span> |
| <span id="L25"><span class="lineNum"> 25</span> : : */</span> |
| <span id="L26"><span class="lineNum"> 26</span> : : </span> |
| <span id="L27"><span class="lineNum"> 27</span> : : /*</span> |
| <span id="L28"><span class="lineNum"> 28</span> : : * P8 GCID</span> |
| <span id="L29"><span class="lineNum"> 29</span> : : * -------</span> |
| <span id="L30"><span class="lineNum"> 30</span> : : *</span> |
| <span id="L31"><span class="lineNum"> 31</span> : : * Global chip ID is a 6 bit number:</span> |
| <span id="L32"><span class="lineNum"> 32</span> : : *</span> |
| <span id="L33"><span class="lineNum"> 33</span> : : * NodeID ChipID</span> |
| <span id="L34"><span class="lineNum"> 34</span> : : * | | |</span> |
| <span id="L35"><span class="lineNum"> 35</span> : : * |___|___|___|___|___|___|</span> |
| <span id="L36"><span class="lineNum"> 36</span> : : *</span> |
| <span id="L37"><span class="lineNum"> 37</span> : : * The the ChipID is 3 bits long, the GCID is the same as the high bits of PIR</span> |
| <span id="L38"><span class="lineNum"> 38</span> : : */</span> |
| <span id="L39"><span class="lineNum"> 39</span> : : #define P8_PIR2GCID(pir) (((pir) >> 7) & 0x3f)</span> |
| <span id="L40"><span class="lineNum"> 40</span> : : </span> |
| <span id="L41"><span class="lineNum"> 41</span> : : #define P8_PIR2COREID(pir) (((pir) >> 3) & 0xf)</span> |
| <span id="L42"><span class="lineNum"> 42</span> : : </span> |
| <span id="L43"><span class="lineNum"> 43</span> : : #define P8_PIR2THREADID(pir) ((pir) & 0x7)</span> |
| <span id="L44"><span class="lineNum"> 44</span> : : </span> |
| <span id="L45"><span class="lineNum"> 45</span> : : /*</span> |
| <span id="L46"><span class="lineNum"> 46</span> : : * P9 GCID</span> |
| <span id="L47"><span class="lineNum"> 47</span> : : * -------</span> |
| <span id="L48"><span class="lineNum"> 48</span> : : *</span> |
| <span id="L49"><span class="lineNum"> 49</span> : : * Global chip ID is a 7 bit number:</span> |
| <span id="L50"><span class="lineNum"> 50</span> : : *</span> |
| <span id="L51"><span class="lineNum"> 51</span> : : * NodeID ChipID</span> |
| <span id="L52"><span class="lineNum"> 52</span> : : * | | |</span> |
| <span id="L53"><span class="lineNum"> 53</span> : : * |___|___|___|___|___|___|___|</span> |
| <span id="L54"><span class="lineNum"> 54</span> : : *</span> |
| <span id="L55"><span class="lineNum"> 55</span> : : * Bit 56 is unused according to the manual by we add it to the coreid here,</span> |
| <span id="L56"><span class="lineNum"> 56</span> : : * thus we have a 6-bit core number.</span> |
| <span id="L57"><span class="lineNum"> 57</span> : : *</span> |
| <span id="L58"><span class="lineNum"> 58</span> : : * Note: XIVE Only supports 4-bit chip numbers ...</span> |
| <span id="L59"><span class="lineNum"> 59</span> : : *</span> |
| <span id="L60"><span class="lineNum"> 60</span> : : * Upper PIR Bits</span> |
| <span id="L61"><span class="lineNum"> 61</span> : : * --------------</span> |
| <span id="L62"><span class="lineNum"> 62</span> : : *</span> |
| <span id="L63"><span class="lineNum"> 63</span> : : * Normal-Core Mode:</span> |
| <span id="L64"><span class="lineNum"> 64</span> : : * 57:61 CoreID</span> |
| <span id="L65"><span class="lineNum"> 65</span> : : * 62:63 ThreadID</span> |
| <span id="L66"><span class="lineNum"> 66</span> : : *</span> |
| <span id="L67"><span class="lineNum"> 67</span> : : * Fused-Core Mode:</span> |
| <span id="L68"><span class="lineNum"> 68</span> : : * 57:59 FusedQuadID</span> |
| <span id="L69"><span class="lineNum"> 69</span> : : * 60 FusedCoreID</span> |
| <span id="L70"><span class="lineNum"> 70</span> : : * 61:63 FusedThreadID</span> |
| <span id="L71"><span class="lineNum"> 71</span> : : *</span> |
| <span id="L72"><span class="lineNum"> 72</span> : : * FusedCoreID 0 contains normal-core chiplet 0 and 1</span> |
| <span id="L73"><span class="lineNum"> 73</span> : : * FusedCoreID 1 contains normal-core chiplet 2 and 3</span> |
| <span id="L74"><span class="lineNum"> 74</span> : : *</span> |
| <span id="L75"><span class="lineNum"> 75</span> : : * Fused cores have interleaved threads:</span> |
| <span id="L76"><span class="lineNum"> 76</span> : : * core chiplet 0/2 = t0, t2, t4, t6</span> |
| <span id="L77"><span class="lineNum"> 77</span> : : * core chiplet 1/3 = t1, t3, t5, t7</span> |
| <span id="L78"><span class="lineNum"> 78</span> : : *</span> |
| <span id="L79"><span class="lineNum"> 79</span> : : */</span> |
| <span id="L80"><span class="lineNum"> 80</span> : : #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f)</span> |
| <span id="L81"><span class="lineNum"> 81</span> : : </span> |
| <span id="L82"><span class="lineNum"> 82</span> : : #define P9_PIR2COREID(pir) (((pir) >> 2) & 0x3f)</span> |
| <span id="L83"><span class="lineNum"> 83</span> : : </span> |
| <span id="L84"><span class="lineNum"> 84</span> : : #define P9_PIR2THREADID(pir) ((pir) & 0x3)</span> |
| <span id="L85"><span class="lineNum"> 85</span> : : </span> |
| <span id="L86"><span class="lineNum"> 86</span> : : #define P9_GCID2NODEID(gcid) (((gcid) >> 3) & 0xf)</span> |
| <span id="L87"><span class="lineNum"> 87</span> : : </span> |
| <span id="L88"><span class="lineNum"> 88</span> : : #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7)</span> |
| <span id="L89"><span class="lineNum"> 89</span> : : </span> |
| <span id="L90"><span class="lineNum"> 90</span> : : #define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7)</span> |
| <span id="L91"><span class="lineNum"> 91</span> : : </span> |
| <span id="L92"><span class="lineNum"> 92</span> : : #define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1)</span> |
| <span id="L93"><span class="lineNum"> 93</span> : : </span> |
| <span id="L94"><span class="lineNum"> 94</span> : : #define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7)</span> |
| <span id="L95"><span class="lineNum"> 95</span> : : </span> |
| <span id="L96"><span class="lineNum"> 96</span> : : #define P9_PIRFUSED2NORMALCOREID(pir) \</span> |
| <span id="L97"><span class="lineNum"> 97</span> : : (P9_PIR2FUSEDQUADID(pir) << 2) | \</span> |
| <span id="L98"><span class="lineNum"> 98</span> : : (P9_PIR2FUSEDCOREID(pir) << 1) | \</span> |
| <span id="L99"><span class="lineNum"> 99</span> : : (P9_PIR2FUSEDTHREADID(pir) & 1)</span> |
| <span id="L100"><span class="lineNum"> 100</span> : : </span> |
| <span id="L101"><span class="lineNum"> 101</span> : : #define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3)</span> |
| <span id="L102"><span class="lineNum"> 102</span> : : </span> |
| <span id="L103"><span class="lineNum"> 103</span> : : #define P10_PIR2FUSEDCOREID(pir) P9_PIR2FUSEDCOREID(pir)</span> |
| <span id="L104"><span class="lineNum"> 104</span> : : #define P10_PIRFUSED2NORMALCOREID(pir) P9_PIRFUSED2NORMALCOREID(pir)</span> |
| <span id="L105"><span class="lineNum"> 105</span> : : #define P10_PIRFUSED2NORMALTHREADID(pir) P9_PIRFUSED2NORMALTHREADID(pir)</span> |
| <span id="L106"><span class="lineNum"> 106</span> : : </span> |
| <span id="L107"><span class="lineNum"> 107</span> : : /* P9 specific ones mostly used by XIVE */</span> |
| <span id="L108"><span class="lineNum"> 108</span> : : #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff)</span> |
| <span id="L109"><span class="lineNum"> 109</span> : : #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu))</span> |
| <span id="L110"><span class="lineNum"> 110</span> : : </span> |
| <span id="L111"><span class="lineNum"> 111</span> : : /*</span> |
| <span id="L112"><span class="lineNum"> 112</span> : : * P10 PIR</span> |
| <span id="L113"><span class="lineNum"> 113</span> : : * -------</span> |
| <span id="L114"><span class="lineNum"> 114</span> : : *</span> |
| <span id="L115"><span class="lineNum"> 115</span> : : * PIR layout:</span> |
| <span id="L116"><span class="lineNum"> 116</span> : : *</span> |
| <span id="L117"><span class="lineNum"> 117</span> : : * | 49| 50| 51| 52| 53| 54| 55| 56| 57| 58| 59| 60| 61| 62| 63|</span> |
| <span id="L118"><span class="lineNum"> 118</span> : : * |Spare ID |Topology ID |Sp. |Quad ID |Core ID |Thread ID|</span> |
| <span id="L119"><span class="lineNum"> 119</span> : : *</span> |
| <span id="L120"><span class="lineNum"> 120</span> : : * Bit 56 is a spare quad ID. In big-core mode, thread ID extends to bit 61.</span> |
| <span id="L121"><span class="lineNum"> 121</span> : : *</span> |
| <span id="L122"><span class="lineNum"> 122</span> : : * P10 GCID</span> |
| <span id="L123"><span class="lineNum"> 123</span> : : * --------</span> |
| <span id="L124"><span class="lineNum"> 124</span> : : *</span> |
| <span id="L125"><span class="lineNum"> 125</span> : : * - Global chip ID is also called Topology ID.</span> |
| <span id="L126"><span class="lineNum"> 126</span> : : * - Node ID is called Group ID (? XXX P10).</span> |
| <span id="L127"><span class="lineNum"> 127</span> : : *</span> |
| <span id="L128"><span class="lineNum"> 128</span> : : * Global chip ID is a 4 bit number.</span> |
| <span id="L129"><span class="lineNum"> 129</span> : : *</span> |
| <span id="L130"><span class="lineNum"> 130</span> : : * There is a topology mode bit that can be 0 or 1, which changes GCID mapping.</span> |
| <span id="L131"><span class="lineNum"> 131</span> : : *</span> |
| <span id="L132"><span class="lineNum"> 132</span> : : * Topology mode 0:</span> |
| <span id="L133"><span class="lineNum"> 133</span> : : * NodeID ChipID</span> |
| <span id="L134"><span class="lineNum"> 134</span> : : * | | |</span> |
| <span id="L135"><span class="lineNum"> 135</span> : : * |____|____|____|____|</span> |
| <span id="L136"><span class="lineNum"> 136</span> : : *</span> |
| <span id="L137"><span class="lineNum"> 137</span> : : * Topology mode 1:</span> |
| <span id="L138"><span class="lineNum"> 138</span> : : * NodeID ChipID</span> |
| <span id="L139"><span class="lineNum"> 139</span> : : * | | |</span> |
| <span id="L140"><span class="lineNum"> 140</span> : : * |____|____|____|____|</span> |
| <span id="L141"><span class="lineNum"> 141</span> : : */</span> |
| <span id="L142"><span class="lineNum"> 142</span> : : #define P10_PIR2GCID(pir) (((pir) >> 8) & 0xf)</span> |
| <span id="L143"><span class="lineNum"> 143</span> : : </span> |
| <span id="L144"><span class="lineNum"> 144</span> : : #define P10_PIR2COREID(pir) (((pir) >> 2) & 0x3f)</span> |
| <span id="L145"><span class="lineNum"> 145</span> : : </span> |
| <span id="L146"><span class="lineNum"> 146</span> : : #define P10_PIR2THREADID(pir) ((pir) & 0x3)</span> |
| <span id="L147"><span class="lineNum"> 147</span> : : </span> |
| <span id="L148"><span class="lineNum"> 148</span> : : // XXX P10 These depend on the topology mode, how to get that (system type?)</span> |
| <span id="L149"><span class="lineNum"> 149</span> : : #define P10_GCID2NODEID(gcid, mode) ((mode) == 0 ? ((gcid) >> 1) & 0x7 : ((gcid) >> 2) & 0x3)</span> |
| <span id="L150"><span class="lineNum"> 150</span> : : #define P10_GCID2CHIPID(gcid, mode) ((mode) == 0 ? (gcid) & 0x1 : (gcid) & 0x3)</span> |
| <span id="L151"><span class="lineNum"> 151</span> : : </span> |
| <span id="L152"><span class="lineNum"> 152</span> : : /* P10 specific ones mostly used by XIVE */</span> |
| <span id="L153"><span class="lineNum"> 153</span> : : #define P10_PIR2LOCALCPU(pir) ((pir) & 0xff)</span> |
| <span id="L154"><span class="lineNum"> 154</span> : : #define P10_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu))</span> |
| <span id="L155"><span class="lineNum"> 155</span> : : </span> |
| <span id="L156"><span class="lineNum"> 156</span> : : struct dt_node;</span> |
| <span id="L157"><span class="lineNum"> 157</span> : : struct centaur_chip;</span> |
| <span id="L158"><span class="lineNum"> 158</span> : : struct mfsi;</span> |
| <span id="L159"><span class="lineNum"> 159</span> : : struct xive;</span> |
| <span id="L160"><span class="lineNum"> 160</span> : : struct lpcm;</span> |
| <span id="L161"><span class="lineNum"> 161</span> : : struct vas;</span> |
| <span id="L162"><span class="lineNum"> 162</span> : : struct p9_sbe;</span> |
| <span id="L163"><span class="lineNum"> 163</span> : : struct p9_dio;</span> |
| <span id="L164"><span class="lineNum"> 164</span> : : </span> |
| <span id="L165"><span class="lineNum"> 165</span> : : /* Chip type */</span> |
| <span id="L166"><span class="lineNum"> 166</span> : : enum proc_chip_type {</span> |
| <span id="L167"><span class="lineNum"> 167</span> : : PROC_CHIP_UNKNOWN,</span> |
| <span id="L168"><span class="lineNum"> 168</span> : : PROC_CHIP_P8_MURANO,</span> |
| <span id="L169"><span class="lineNum"> 169</span> : : PROC_CHIP_P8_VENICE,</span> |
| <span id="L170"><span class="lineNum"> 170</span> : : PROC_CHIP_P8_NAPLES,</span> |
| <span id="L171"><span class="lineNum"> 171</span> : : PROC_CHIP_P9_NIMBUS,</span> |
| <span id="L172"><span class="lineNum"> 172</span> : : PROC_CHIP_P9_CUMULUS,</span> |
| <span id="L173"><span class="lineNum"> 173</span> : : PROC_CHIP_P9P,</span> |
| <span id="L174"><span class="lineNum"> 174</span> : : PROC_CHIP_P10,</span> |
| <span id="L175"><span class="lineNum"> 175</span> : : PROC_CHIP_P11,</span> |
| <span id="L176"><span class="lineNum"> 176</span> : : };</span> |
| <span id="L177"><span class="lineNum"> 177</span> : : </span> |
| <span id="L178"><span class="lineNum"> 178</span> : : /* Simulator quirks */</span> |
| <span id="L179"><span class="lineNum"> 179</span> : : enum proc_chip_quirks {</span> |
| <span id="L180"><span class="lineNum"> 180</span> : : QUIRK_NO_CHIPTOD = 0x00000001,</span> |
| <span id="L181"><span class="lineNum"> 181</span> : : QUIRK_MAMBO_CALLOUTS = 0x00000002,</span> |
| <span id="L182"><span class="lineNum"> 182</span> : : QUIRK_NO_F000F = 0x00000004,</span> |
| <span id="L183"><span class="lineNum"> 183</span> : : QUIRK_NO_PBA = 0x00000008,</span> |
| <span id="L184"><span class="lineNum"> 184</span> : : QUIRK_NO_OCC_IRQ = 0x00000010,</span> |
| <span id="L185"><span class="lineNum"> 185</span> : : QUIRK_SIMICS = 0x00000020,</span> |
| <span id="L186"><span class="lineNum"> 186</span> : : QUIRK_SLOW_SIM = 0x00000040,</span> |
| <span id="L187"><span class="lineNum"> 187</span> : : QUIRK_NO_DIRECT_CTL = 0x00000080,</span> |
| <span id="L188"><span class="lineNum"> 188</span> : : QUIRK_NO_RNG = 0x00000100,</span> |
| <span id="L189"><span class="lineNum"> 189</span> : : QUIRK_QEMU = 0x00000200,</span> |
| <span id="L190"><span class="lineNum"> 190</span> : : QUIRK_AWAN = 0x00000400,</span> |
| <span id="L191"><span class="lineNum"> 191</span> : : QUIRK_BML = 0x00000800,</span> |
| <span id="L192"><span class="lineNum"> 192</span> : : QUIRK_NO_SBE = 0x00001000,</span> |
| <span id="L193"><span class="lineNum"> 193</span> : : };</span> |
| <span id="L194"><span class="lineNum"> 194</span> : : </span> |
| <span id="L195"><span class="lineNum"> 195</span> : : extern enum proc_chip_quirks proc_chip_quirks;</span> |
| <span id="L196"><span class="lineNum"> 196</span> : : </span> |
| <span id="L197"><span class="lineNum"> 197</span> :<span class="tlaGNC tlaBgGNC"> 36 : static inline bool chip_quirk(unsigned int q)</span></span> |
| <span id="L198"><span class="lineNum"> 198</span> : : {</span> |
| <span id="L199"><span class="lineNum"> 199</span> :<span class="tlaGNC"> 36 : return !!(proc_chip_quirks & q);</span></span> |
| <span id="L200"><span class="lineNum"> 200</span> : : }</span> |
| <span id="L201"><span class="lineNum"> 201</span> : : </span> |
| <span id="L202"><span class="lineNum"> 202</span> : : #define MAX_CHIPS (1 << 6) /* 6-bit chip ID */</span> |
| <span id="L203"><span class="lineNum"> 203</span> : : </span> |
| <span id="L204"><span class="lineNum"> 204</span> : : /*</span> |
| <span id="L205"><span class="lineNum"> 205</span> : : * For each chip in the system, we maintain this structure</span> |
| <span id="L206"><span class="lineNum"> 206</span> : : *</span> |
| <span id="L207"><span class="lineNum"> 207</span> : : * This contains fields used by different modules including</span> |
| <span id="L208"><span class="lineNum"> 208</span> : : * modules in hw/ but is handy to keep per-chip data</span> |
| <span id="L209"><span class="lineNum"> 209</span> : : */</span> |
| <span id="L210"><span class="lineNum"> 210</span> : : struct proc_chip {</span> |
| <span id="L211"><span class="lineNum"> 211</span> : : uint32_t id; /* HW Chip ID (GCID) */</span> |
| <span id="L212"><span class="lineNum"> 212</span> : : struct dt_node *devnode; /* "xscom" chip node */</span> |
| <span id="L213"><span class="lineNum"> 213</span> : : </span> |
| <span id="L214"><span class="lineNum"> 214</span> : : /* These are only initialized after xcom_init */</span> |
| <span id="L215"><span class="lineNum"> 215</span> : : enum proc_chip_type type;</span> |
| <span id="L216"><span class="lineNum"> 216</span> : : uint32_t ec_level; /* 0xMm (DD1.0 = 0x10) */</span> |
| <span id="L217"><span class="lineNum"> 217</span> : : uint8_t ec_rev; /* sub-revision */</span> |
| <span id="L218"><span class="lineNum"> 218</span> : : </span> |
| <span id="L219"><span class="lineNum"> 219</span> : : /* Those two values are only populated on machines with an FSP</span> |
| <span id="L220"><span class="lineNum"> 220</span> : : * dbob_id = Drawer/Block/Octant/Blade (DBOBID)</span> |
| <span id="L221"><span class="lineNum"> 221</span> : : * pcid = HDAT processor_chip_id</span> |
| <span id="L222"><span class="lineNum"> 222</span> : : */</span> |
| <span id="L223"><span class="lineNum"> 223</span> : : uint32_t dbob_id;</span> |
| <span id="L224"><span class="lineNum"> 224</span> : : uint32_t pcid;</span> |
| <span id="L225"><span class="lineNum"> 225</span> : : </span> |
| <span id="L226"><span class="lineNum"> 226</span> : : /* If we expect to have an OCC (i.e. P8) and it is functional,</span> |
| <span id="L227"><span class="lineNum"> 227</span> : : * set TRUE. If something has told us it is not, set FALSE and</span> |
| <span id="L228"><span class="lineNum"> 228</span> : : * we can not wait for OCCs to init. This is only going to be</span> |
| <span id="L229"><span class="lineNum"> 229</span> : : * FALSE in a simulator that doesn't simulate OCCs. */</span> |
| <span id="L230"><span class="lineNum"> 230</span> : : bool occ_functional;</span> |
| <span id="L231"><span class="lineNum"> 231</span> : : </span> |
| <span id="L232"><span class="lineNum"> 232</span> : : /* Used by hw/xscom.c */</span> |
| <span id="L233"><span class="lineNum"> 233</span> : : uint64_t xscom_base;</span> |
| <span id="L234"><span class="lineNum"> 234</span> : : </span> |
| <span id="L235"><span class="lineNum"> 235</span> : : /* Used by hw/lpc.c */</span> |
| <span id="L236"><span class="lineNum"> 236</span> : : struct lpcm *lpc;</span> |
| <span id="L237"><span class="lineNum"> 237</span> : : </span> |
| <span id="L238"><span class="lineNum"> 238</span> : : /* Used by hw/slw.c */</span> |
| <span id="L239"><span class="lineNum"> 239</span> : : uint64_t slw_base;</span> |
| <span id="L240"><span class="lineNum"> 240</span> : : uint64_t slw_bar_size;</span> |
| <span id="L241"><span class="lineNum"> 241</span> : : uint64_t slw_image_size;</span> |
| <span id="L242"><span class="lineNum"> 242</span> : : </span> |
| <span id="L243"><span class="lineNum"> 243</span> : : /* Used by hw/homer.c */</span> |
| <span id="L244"><span class="lineNum"> 244</span> : : uint64_t homer_base;</span> |
| <span id="L245"><span class="lineNum"> 245</span> : : uint64_t homer_size;</span> |
| <span id="L246"><span class="lineNum"> 246</span> : : uint64_t occ_common_base;</span> |
| <span id="L247"><span class="lineNum"> 247</span> : : uint64_t occ_common_size;</span> |
| <span id="L248"><span class="lineNum"> 248</span> : : uint8_t throttle;</span> |
| <span id="L249"><span class="lineNum"> 249</span> : : </span> |
| <span id="L250"><span class="lineNum"> 250</span> : : /* Must hold capi_lock to change */</span> |
| <span id="L251"><span class="lineNum"> 251</span> : : uint8_t capp_phb3_attached_mask;</span> |
| <span id="L252"><span class="lineNum"> 252</span> : : uint8_t capp_ucode_loaded;</span> |
| <span id="L253"><span class="lineNum"> 253</span> : : </span> |
| <span id="L254"><span class="lineNum"> 254</span> : : /* Used by hw/centaur.c */</span> |
| <span id="L255"><span class="lineNum"> 255</span> : : struct centaur_chip *centaurs;</span> |
| <span id="L256"><span class="lineNum"> 256</span> : : </span> |
| <span id="L257"><span class="lineNum"> 257</span> : : /* Used by hw/p8-i2c.c */</span> |
| <span id="L258"><span class="lineNum"> 258</span> : : struct list_head i2cms;</span> |
| <span id="L259"><span class="lineNum"> 259</span> : : </span> |
| <span id="L260"><span class="lineNum"> 260</span> : : /* Used by hw/psi.c */</span> |
| <span id="L261"><span class="lineNum"> 261</span> : : struct psi *psi;</span> |
| <span id="L262"><span class="lineNum"> 262</span> : : </span> |
| <span id="L263"><span class="lineNum"> 263</span> : : /* Used by hw/fsi-master.c */</span> |
| <span id="L264"><span class="lineNum"> 264</span> : : struct mfsi *fsi_masters;</span> |
| <span id="L265"><span class="lineNum"> 265</span> : : </span> |
| <span id="L266"><span class="lineNum"> 266</span> : : /* Used by hw/xive.c */</span> |
| <span id="L267"><span class="lineNum"> 267</span> : : struct xive *xive;</span> |
| <span id="L268"><span class="lineNum"> 268</span> : : </span> |
| <span id="L269"><span class="lineNum"> 269</span> : : struct vas *vas;</span> |
| <span id="L270"><span class="lineNum"> 270</span> : : </span> |
| <span id="L271"><span class="lineNum"> 271</span> : : /* Used by hw/nx-compress.c */</span> |
| <span id="L272"><span class="lineNum"> 272</span> : : uint64_t nx_base;</span> |
| <span id="L273"><span class="lineNum"> 273</span> : : /* location code of this chip */</span> |
| <span id="L274"><span class="lineNum"> 274</span> : : const uint8_t *loc_code;</span> |
| <span id="L275"><span class="lineNum"> 275</span> : : </span> |
| <span id="L276"><span class="lineNum"> 276</span> : : /* Used by hw/sbe-p9.c */</span> |
| <span id="L277"><span class="lineNum"> 277</span> : : struct p9_sbe *sbe;</span> |
| <span id="L278"><span class="lineNum"> 278</span> : : </span> |
| <span id="L279"><span class="lineNum"> 279</span> : : /* Used by hw/dio-p9.c */</span> |
| <span id="L280"><span class="lineNum"> 280</span> : : struct p9_dio *dio;</span> |
| <span id="L281"><span class="lineNum"> 281</span> : : </span> |
| <span id="L282"><span class="lineNum"> 282</span> : : /* Used during OCC init */</span> |
| <span id="L283"><span class="lineNum"> 283</span> : : bool ex_present;</span> |
| <span id="L284"><span class="lineNum"> 284</span> : : </span> |
| <span id="L285"><span class="lineNum"> 285</span> : : /* Used by hw/vas.c on p10 */</span> |
| <span id="L286"><span class="lineNum"> 286</span> : : uint32_t primary_topology;</span> |
| <span id="L287"><span class="lineNum"> 287</span> : : };</span> |
| <span id="L288"><span class="lineNum"> 288</span> : : </span> |
| <span id="L289"><span class="lineNum"> 289</span> : : extern uint32_t pir_to_chip_id(uint32_t pir);</span> |
| <span id="L290"><span class="lineNum"> 290</span> : : </span> |
| <span id="L291"><span class="lineNum"> 291</span> : : /*</span> |
| <span id="L292"><span class="lineNum"> 292</span> : : * Note: In P9 fused-core mode, these will return the "normal"</span> |
| <span id="L293"><span class="lineNum"> 293</span> : : * core ID and thread ID (ie, thread ID 0..3)</span> |
| <span id="L294"><span class="lineNum"> 294</span> : : */</span> |
| <span id="L295"><span class="lineNum"> 295</span> : : extern uint32_t pir_to_core_id(uint32_t pir);</span> |
| <span id="L296"><span class="lineNum"> 296</span> : : extern uint32_t pir_to_thread_id(uint32_t pir);</span> |
| <span id="L297"><span class="lineNum"> 297</span> : : </span> |
| <span id="L298"><span class="lineNum"> 298</span> : : /* In P9 fused core mode, this is the "fused" core ID, in</span> |
| <span id="L299"><span class="lineNum"> 299</span> : : * normal core mode or P8, this is the same as pir_to_core_id</span> |
| <span id="L300"><span class="lineNum"> 300</span> : : */</span> |
| <span id="L301"><span class="lineNum"> 301</span> : : extern uint32_t pir_to_fused_core_id(uint32_t pir);</span> |
| <span id="L302"><span class="lineNum"> 302</span> : : </span> |
| <span id="L303"><span class="lineNum"> 303</span> : : extern struct proc_chip *next_chip(struct proc_chip *chip);</span> |
| <span id="L304"><span class="lineNum"> 304</span> : : </span> |
| <span id="L305"><span class="lineNum"> 305</span> : : #define for_each_chip(__c) for (__c=next_chip(NULL); __c; __c=next_chip(__c))</span> |
| <span id="L306"><span class="lineNum"> 306</span> : : </span> |
| <span id="L307"><span class="lineNum"> 307</span> : : extern struct proc_chip *get_chip(uint32_t chip_id);</span> |
| <span id="L308"><span class="lineNum"> 308</span> : : </span> |
| <span id="L309"><span class="lineNum"> 309</span> : : extern void init_chips(void);</span> |
| <span id="L310"><span class="lineNum"> 310</span> : : </span> |
| <span id="L311"><span class="lineNum"> 311</span> : : /* helper to get number of chips in the system */</span> |
| <span id="L312"><span class="lineNum"> 312</span> : : static inline int nr_chips(void)</span> |
| <span id="L313"><span class="lineNum"> 313</span> : : {</span> |
| <span id="L314"><span class="lineNum"> 314</span> : : struct proc_chip *chip;</span> |
| <span id="L315"><span class="lineNum"> 315</span> : : int nr_chips = 0;</span> |
| <span id="L316"><span class="lineNum"> 316</span> : : </span> |
| <span id="L317"><span class="lineNum"> 317</span> : : for_each_chip(chip)</span> |
| <span id="L318"><span class="lineNum"> 318</span> : : nr_chips++;</span> |
| <span id="L319"><span class="lineNum"> 319</span> : : </span> |
| <span id="L320"><span class="lineNum"> 320</span> : : return nr_chips;</span> |
| <span id="L321"><span class="lineNum"> 321</span> : : }</span> |
| <span id="L322"><span class="lineNum"> 322</span> : : </span> |
| <span id="L323"><span class="lineNum"> 323</span> : : /* helper to get location code of a chip */</span> |
| <span id="L324"><span class="lineNum"> 324</span> : : static inline const char *chip_loc_code(uint32_t chip_id)</span> |
| <span id="L325"><span class="lineNum"> 325</span> : : {</span> |
| <span id="L326"><span class="lineNum"> 326</span> : : struct proc_chip *chip;</span> |
| <span id="L327"><span class="lineNum"> 327</span> : : </span> |
| <span id="L328"><span class="lineNum"> 328</span> : : chip = get_chip(chip_id);</span> |
| <span id="L329"><span class="lineNum"> 329</span> : : if (!chip)</span> |
| <span id="L330"><span class="lineNum"> 330</span> : : return NULL;</span> |
| <span id="L331"><span class="lineNum"> 331</span> : : </span> |
| <span id="L332"><span class="lineNum"> 332</span> : : return chip->loc_code;</span> |
| <span id="L333"><span class="lineNum"> 333</span> : : }</span> |
| <span id="L334"><span class="lineNum"> 334</span> : : </span> |
| <span id="L335"><span class="lineNum"> 335</span> : : #endif /* __CHIP_H */</span> |
| <span id="L336"><span class="lineNum"> 336</span> : : </span> |
| </pre> |
| </td> |
| </tr> |
| </table> |
| <br> |
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| <tr><td class="versionInfo">Generated by: <a href="https://github.com//linux-test-project/lcov" target="_parent">LCOV version 2.0-1</a></td></tr> |
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