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| <td width="10%" class="headerItem">Current view:</td> |
| <td width="10%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">hw</a> - phys-map.c<span style="font-size: 80%;"> (source / <a href="phys-map.c.func-c.html">functions</a>)</span></td> |
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| <td width="5%" class="headerCovTableHead">Coverage</td> |
| <td width="5%" class="headerCovTableHead" title="Covered + Uncovered code">Total</td> |
| <td width="5%" class="headerCovTableHead" title="Exercised code only">Hit</td> |
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| <td class="headerItem">Test:</td> |
| <td class="headerValue">skiboot.info</td> |
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| <td class="headerItem">Lines:</td> |
| <td class="headerCovTableEntryLo">73.1 %</td> |
| <td class="headerCovTableEntry">52</td> |
| <td class="headerCovTableEntry">38</td> |
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| <td class="headerItem">Test Date:</td> |
| <td class="headerValue">2025-06-27 16:54:26</td> |
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| <td class="headerItem">Functions:</td> |
| <td class="headerCovTableEntryMed">75.0 %</td> |
| <td class="headerCovTableEntry">4</td> |
| <td class="headerCovTableEntry">3</td> |
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| <td class="headerItem">Branches:</td> |
| <td class="headerCovTableEntryHi">-</td> |
| <td class="headerCovTableEntry">0</td> |
| <td class="headerCovTableEntry">0</td> |
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| <pre class="sourceHeading"> Branch data Line data Source code</pre> |
| <pre class="source"> |
| <span id="L1"><span class="lineNum"> 1</span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</span> |
| <span id="L2"><span class="lineNum"> 2</span> : : /*</span> |
| <span id="L3"><span class="lineNum"> 3</span> : : * Physical memory map</span> |
| <span id="L4"><span class="lineNum"> 4</span> : : *</span> |
| <span id="L5"><span class="lineNum"> 5</span> : : * Copyright 2017-2019 IBM Corp.</span> |
| <span id="L6"><span class="lineNum"> 6</span> : : */</span> |
| <span id="L7"><span class="lineNum"> 7</span> : : </span> |
| <span id="L8"><span class="lineNum"> 8</span> : : #include <phys-map.h></span> |
| <span id="L9"><span class="lineNum"> 9</span> : : #include <chip.h></span> |
| <span id="L10"><span class="lineNum"> 10</span> : : #include <skiboot.h></span> |
| <span id="L11"><span class="lineNum"> 11</span> : : #include <opal-api.h></span> |
| <span id="L12"><span class="lineNum"> 12</span> : : #include <stack.h></span> |
| <span id="L13"><span class="lineNum"> 13</span> : : #include <inttypes.h></span> |
| <span id="L14"><span class="lineNum"> 14</span> : : </span> |
| <span id="L15"><span class="lineNum"> 15</span> : : struct phys_map_entry {</span> |
| <span id="L16"><span class="lineNum"> 16</span> : : enum phys_map_type type;</span> |
| <span id="L17"><span class="lineNum"> 17</span> : : int index;</span> |
| <span id="L18"><span class="lineNum"> 18</span> : : uint64_t addr;</span> |
| <span id="L19"><span class="lineNum"> 19</span> : : uint64_t size;</span> |
| <span id="L20"><span class="lineNum"> 20</span> : : };</span> |
| <span id="L21"><span class="lineNum"> 21</span> : : </span> |
| <span id="L22"><span class="lineNum"> 22</span> : : struct phys_map_info {</span> |
| <span id="L23"><span class="lineNum"> 23</span> : : int chip_select_shift;</span> |
| <span id="L24"><span class="lineNum"> 24</span> : : const struct phys_map_entry *table;</span> |
| <span id="L25"><span class="lineNum"> 25</span> : : };</span> |
| <span id="L26"><span class="lineNum"> 26</span> : : </span> |
| <span id="L27"><span class="lineNum"> 27</span> : : static const struct phys_map_info *phys_map;</span> |
| <span id="L28"><span class="lineNum"> 28</span> : : </span> |
| <span id="L29"><span class="lineNum"> 29</span> : : static const struct phys_map_entry phys_map_table_p10[] = {</span> |
| <span id="L30"><span class="lineNum"> 30</span> : : /* System memory upto 4TB minus GPU memory */</span> |
| <span id="L31"><span class="lineNum"> 31</span> : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },</span> |
| <span id="L32"><span class="lineNum"> 32</span> : : </span> |
| <span id="L33"><span class="lineNum"> 33</span> : : /* Configure OpenCapi memory as before with the old chips.</span> |
| <span id="L34"><span class="lineNum"> 34</span> : : * Keep in mind that we would need to rework this by allocating</span> |
| <span id="L35"><span class="lineNum"> 35</span> : : * a new topology id.</span> |
| <span id="L36"><span class="lineNum"> 36</span> : : */</span> |
| <span id="L37"><span class="lineNum"> 37</span> : : { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },</span> |
| <span id="L38"><span class="lineNum"> 38</span> : : { OCAPI_MEM, 1, 0x0002040000000000ull, 0x0000040000000000ull },</span> |
| <span id="L39"><span class="lineNum"> 39</span> : : </span> |
| <span id="L40"><span class="lineNum"> 40</span> : : /* 0 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L41"><span class="lineNum"> 41</span> : : { PHB5_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },</span> |
| <span id="L42"><span class="lineNum"> 42</span> : : { PHB5_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },</span> |
| <span id="L43"><span class="lineNum"> 43</span> : : { PHB5_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },</span> |
| <span id="L44"><span class="lineNum"> 44</span> : : { PHB5_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },</span> |
| <span id="L45"><span class="lineNum"> 45</span> : : { PHB5_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },</span> |
| <span id="L46"><span class="lineNum"> 46</span> : : { PHB5_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },</span> |
| <span id="L47"><span class="lineNum"> 47</span> : : { PHB5_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },</span> |
| <span id="L48"><span class="lineNum"> 48</span> : : { PHB5_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },</span> |
| <span id="L49"><span class="lineNum"> 49</span> : : { PHB5_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },</span> |
| <span id="L50"><span class="lineNum"> 50</span> : : { PHB5_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },</span> |
| <span id="L51"><span class="lineNum"> 51</span> : : { PHB5_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },</span> |
| <span id="L52"><span class="lineNum"> 52</span> : : { PHB5_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },</span> |
| <span id="L53"><span class="lineNum"> 53</span> : : { PHB5_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },</span> |
| <span id="L54"><span class="lineNum"> 54</span> : : { PHB5_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },</span> |
| <span id="L55"><span class="lineNum"> 55</span> : : { PHB5_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },</span> |
| <span id="L56"><span class="lineNum"> 56</span> : : { PHB5_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },</span> |
| <span id="L57"><span class="lineNum"> 57</span> : : { PHB5_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },</span> |
| <span id="L58"><span class="lineNum"> 58</span> : : { PHB5_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },</span> |
| <span id="L59"><span class="lineNum"> 59</span> : : { PHB5_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },</span> |
| <span id="L60"><span class="lineNum"> 60</span> : : { PHB5_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },</span> |
| <span id="L61"><span class="lineNum"> 61</span> : : { PHB5_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },</span> |
| <span id="L62"><span class="lineNum"> 62</span> : : { RESV , 0, 0x000600c3c0600000ull, 0x0000003c3fa00000ull },</span> |
| <span id="L63"><span class="lineNum"> 63</span> : : </span> |
| <span id="L64"><span class="lineNum"> 64</span> : : /* 1 TB offset */</span> |
| <span id="L65"><span class="lineNum"> 65</span> : : { RESV , 1, 0x0006010000000000ull, 0x0000010000000000ull },</span> |
| <span id="L66"><span class="lineNum"> 66</span> : : </span> |
| <span id="L67"><span class="lineNum"> 67</span> : : /* 2 TB offset */</span> |
| <span id="L68"><span class="lineNum"> 68</span> : : { PHB5_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },</span> |
| <span id="L69"><span class="lineNum"> 69</span> : : { PHB5_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },</span> |
| <span id="L70"><span class="lineNum"> 70</span> : : { PHB5_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },</span> |
| <span id="L71"><span class="lineNum"> 71</span> : : { RESV , 2, 0x000602c000000000ull, 0x0000004000000000ull },</span> |
| <span id="L72"><span class="lineNum"> 72</span> : : </span> |
| <span id="L73"><span class="lineNum"> 73</span> : : /* 3 TB offset */</span> |
| <span id="L74"><span class="lineNum"> 74</span> : : { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },</span> |
| <span id="L75"><span class="lineNum"> 75</span> : : { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },</span> |
| <span id="L76"><span class="lineNum"> 76</span> : : { XIVE_IC , 0, 0x0006030200000000ull, 0x0000000002000000ull },</span> |
| <span id="L77"><span class="lineNum"> 77</span> : : { PSIHB_ESB , 0, 0x0006030202000000ull, 0x0000000000100000ull },</span> |
| <span id="L78"><span class="lineNum"> 78</span> : : { RESV , 3, 0x0006030202100000ull, 0x0000000000f00000ull },</span> |
| <span id="L79"><span class="lineNum"> 79</span> : : { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },</span> |
| <span id="L80"><span class="lineNum"> 80</span> : : { RESV , 4, 0x0006030203100000ull, 0x0000000000080000ull },</span> |
| <span id="L81"><span class="lineNum"> 81</span> : : { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },</span> |
| <span id="L82"><span class="lineNum"> 82</span> : : { RESV , 5, 0x00060302031c0000ull, 0x0000000000010000ull },</span> |
| <span id="L83"><span class="lineNum"> 83</span> : : { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },</span> |
| <span id="L84"><span class="lineNum"> 84</span> : : { RESV , 6, 0x00060302031e0000ull, 0x0000000004e20000ull },</span> |
| <span id="L85"><span class="lineNum"> 85</span> : : { XIVE_NVC , 0, 0x0006030208000000ull, 0x0000000008000000ull },</span> |
| <span id="L86"><span class="lineNum"> 86</span> : : { RESV , 7, 0x0006030210000000ull, 0x00000000ee000000ull },</span> |
| <span id="L87"><span class="lineNum"> 87</span> : : { VAS_HYP_WIN , 0, 0x00060302fe000000ull, 0x0000000002000000ull },</span> |
| <span id="L88"><span class="lineNum"> 88</span> : : { VAS_USER_WIN , 0, 0x0006030300000000ull, 0x0000000100000000ull },</span> |
| <span id="L89"><span class="lineNum"> 89</span> : : </span> |
| <span id="L90"><span class="lineNum"> 90</span> : : /* TODO: MC, OCMB */</span> |
| <span id="L91"><span class="lineNum"> 91</span> : : { RESV , 8, 0x0006030400000000ull, 0x0000008400000000ull },</span> |
| <span id="L92"><span class="lineNum"> 92</span> : : { PAU_OCAPI_MMIO , 0, 0x0006038800000000ull, 0x0000000800000000ull },</span> |
| <span id="L93"><span class="lineNum"> 93</span> : : { PAU_OCAPI_MMIO , 1, 0x0006039000000000ull, 0x0000000800000000ull },</span> |
| <span id="L94"><span class="lineNum"> 94</span> : : { PAU_OCAPI_MMIO , 2, 0x0006039800000000ull, 0x0000000800000000ull },</span> |
| <span id="L95"><span class="lineNum"> 95</span> : : { PAU_OCAPI_MMIO , 3, 0x000603a000000000ull, 0x0000000800000000ull },</span> |
| <span id="L96"><span class="lineNum"> 96</span> : : { PAU_OCAPI_MMIO , 4, 0x000603a800000000ull, 0x0000000800000000ull },</span> |
| <span id="L97"><span class="lineNum"> 97</span> : : { PAU_OCAPI_MMIO , 5, 0x000603b000000000ull, 0x0000000800000000ull },</span> |
| <span id="L98"><span class="lineNum"> 98</span> : : { PAU_OCAPI_MMIO , 6, 0x000603b800000000ull, 0x0000000800000000ull },</span> |
| <span id="L99"><span class="lineNum"> 99</span> : : { PAU_OCAPI_MMIO , 7, 0x000603c000000000ull, 0x0000000800000000ull },</span> |
| <span id="L100"><span class="lineNum"> 100</span> : : { PAU_OCAPI_MMIO , 8, 0x000603c800000000ull, 0x0000000800000000ull },</span> |
| <span id="L101"><span class="lineNum"> 101</span> : : { PAU_OCAPI_MMIO , 9, 0x000603d000000000ull, 0x0000000800000000ull },</span> |
| <span id="L102"><span class="lineNum"> 102</span> : : { PAU_OCAPI_MMIO ,10, 0x000603d800000000ull, 0x0000000800000000ull },</span> |
| <span id="L103"><span class="lineNum"> 103</span> : : { PAU_OCAPI_MMIO ,11, 0x000603e000000000ull, 0x0000000800000000ull },</span> |
| <span id="L104"><span class="lineNum"> 104</span> : : { PAU_REGS , 0, 0x000603e800000000ull, 0x0000000001000000ull },</span> |
| <span id="L105"><span class="lineNum"> 105</span> : : { PAU_REGS , 1, 0x000603e801000000ull, 0x0000000001000000ull },</span> |
| <span id="L106"><span class="lineNum"> 106</span> : : { PAU_REGS , 2, 0x000603e802000000ull, 0x0000000001000000ull },</span> |
| <span id="L107"><span class="lineNum"> 107</span> : : { PAU_REGS , 3, 0x000603e803000000ull, 0x0000000001000000ull },</span> |
| <span id="L108"><span class="lineNum"> 108</span> : : { PAU_REGS , 4, 0x000603e804000000ull, 0x0000000001000000ull },</span> |
| <span id="L109"><span class="lineNum"> 109</span> : : { PAU_REGS , 5, 0x000603e805000000ull, 0x0000000001000000ull },</span> |
| <span id="L110"><span class="lineNum"> 110</span> : : { RESV , 9, 0x000603e806000000ull, 0x0000000000040000ull },</span> |
| <span id="L111"><span class="lineNum"> 111</span> : : { PAU_NTL , 0, 0x000603e806040000ull, 0x0000000000020000ull },</span> |
| <span id="L112"><span class="lineNum"> 112</span> : : { PAU_NTL , 1, 0x000603e806060000ull, 0x0000000000020000ull },</span> |
| <span id="L113"><span class="lineNum"> 113</span> : : { PAU_GENID , 0, 0x000603e806080000ull, 0x0000000000080000ull },</span> |
| <span id="L114"><span class="lineNum"> 114</span> : : { RESV ,10, 0x000603e806100000ull, 0x0000000000040000ull },</span> |
| <span id="L115"><span class="lineNum"> 115</span> : : { PAU_NTL , 2, 0x000603e806140000ull, 0x0000000000020000ull },</span> |
| <span id="L116"><span class="lineNum"> 116</span> : : { PAU_NTL , 3, 0x000603e806160000ull, 0x0000000000020000ull },</span> |
| <span id="L117"><span class="lineNum"> 117</span> : : { PAU_GENID , 1, 0x000603e806180000ull, 0x0000000000080000ull },</span> |
| <span id="L118"><span class="lineNum"> 118</span> : : { RESV ,11, 0x000603e806200000ull, 0x0000000000040000ull },</span> |
| <span id="L119"><span class="lineNum"> 119</span> : : { PAU_NTL , 4, 0x000603e806240000ull, 0x0000000000020000ull },</span> |
| <span id="L120"><span class="lineNum"> 120</span> : : { PAU_NTL , 5, 0x000603e806260000ull, 0x0000000000020000ull },</span> |
| <span id="L121"><span class="lineNum"> 121</span> : : { PAU_GENID , 2, 0x000603e806280000ull, 0x0000000000080000ull },</span> |
| <span id="L122"><span class="lineNum"> 122</span> : : { RESV ,12, 0x000603e806300000ull, 0x0000000000040000ull },</span> |
| <span id="L123"><span class="lineNum"> 123</span> : : { PAU_NTL , 6, 0x000603e806340000ull, 0x0000000000020000ull },</span> |
| <span id="L124"><span class="lineNum"> 124</span> : : { PAU_NTL , 7, 0x000603e806360000ull, 0x0000000000020000ull },</span> |
| <span id="L125"><span class="lineNum"> 125</span> : : { PAU_GENID , 3, 0x000603e806380000ull, 0x0000000000080000ull },</span> |
| <span id="L126"><span class="lineNum"> 126</span> : : { RESV ,13, 0x000603e806400000ull, 0x0000000000040000ull },</span> |
| <span id="L127"><span class="lineNum"> 127</span> : : { PAU_NTL , 8, 0x000603e806440000ull, 0x0000000000020000ull },</span> |
| <span id="L128"><span class="lineNum"> 128</span> : : { PAU_NTL , 9, 0x000603e806460000ull, 0x0000000000020000ull },</span> |
| <span id="L129"><span class="lineNum"> 129</span> : : { PAU_GENID , 4, 0x000603e806480000ull, 0x0000000000080000ull },</span> |
| <span id="L130"><span class="lineNum"> 130</span> : : { RESV ,14, 0x000603e806500000ull, 0x0000000000040000ull },</span> |
| <span id="L131"><span class="lineNum"> 131</span> : : { PAU_NTL ,10, 0x000603e806540000ull, 0x0000000000020000ull },</span> |
| <span id="L132"><span class="lineNum"> 132</span> : : { PAU_NTL ,11, 0x000603e806560000ull, 0x0000000000020000ull },</span> |
| <span id="L133"><span class="lineNum"> 133</span> : : { PAU_GENID , 5, 0x000603e806580000ull, 0x0000000000080000ull },</span> |
| <span id="L134"><span class="lineNum"> 134</span> : : { RESV ,15, 0x000603e806600000ull, 0x00000013F9A00000ull },</span> |
| <span id="L135"><span class="lineNum"> 135</span> : : { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },</span> |
| <span id="L136"><span class="lineNum"> 136</span> : : </span> |
| <span id="L137"><span class="lineNum"> 137</span> : : /* 4 TB offset */</span> |
| <span id="L138"><span class="lineNum"> 138</span> : : { XIVE_NVPG , 0, 0x0006040000000000ull, 0x0000010000000000ull },</span> |
| <span id="L139"><span class="lineNum"> 139</span> : : </span> |
| <span id="L140"><span class="lineNum"> 140</span> : : /* 5 - 7 TB offset */</span> |
| <span id="L141"><span class="lineNum"> 141</span> : : /* for P10 the END and ESB regions are separate in the MMIO</span> |
| <span id="L142"><span class="lineNum"> 142</span> : : * table */</span> |
| <span id="L143"><span class="lineNum"> 143</span> : : { XIVE_ESB , 0, 0x0006050000000000ull, 0x0000010000000000ull },</span> |
| <span id="L144"><span class="lineNum"> 144</span> : : { XIVE_END , 0, 0x0006060000000000ull, 0x0000020000000000ull },</span> |
| <span id="L145"><span class="lineNum"> 145</span> : : </span> |
| <span id="L146"><span class="lineNum"> 146</span> : : /* 8 - 13 TB offset */</span> |
| <span id="L147"><span class="lineNum"> 147</span> : : { RESV ,16, 0x0006080000000000ull, 0x0000060000000000ull },</span> |
| <span id="L148"><span class="lineNum"> 148</span> : : </span> |
| <span id="L149"><span class="lineNum"> 149</span> : : /* 14 TB offset */</span> |
| <span id="L150"><span class="lineNum"> 150</span> : : { RESV ,17, 0x00060e0000000000ull, 0x0000008000000000ull },</span> |
| <span id="L151"><span class="lineNum"> 151</span> : : </span> |
| <span id="L152"><span class="lineNum"> 152</span> : : { NULL_MAP, 0, 0, 0 },</span> |
| <span id="L153"><span class="lineNum"> 153</span> : : };</span> |
| <span id="L154"><span class="lineNum"> 154</span> : : </span> |
| <span id="L155"><span class="lineNum"> 155</span> : : static const struct phys_map_entry phys_map_table_nimbus[] = {</span> |
| <span id="L156"><span class="lineNum"> 156</span> : : </span> |
| <span id="L157"><span class="lineNum"> 157</span> : : /* System memory upto 4TB minus GPU memory */</span> |
| <span id="L158"><span class="lineNum"> 158</span> : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },</span> |
| <span id="L159"><span class="lineNum"> 159</span> : : /* GPU memory from 4TB - 128GB*GPU */</span> |
| <span id="L160"><span class="lineNum"> 160</span> : : { GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },</span> |
| <span id="L161"><span class="lineNum"> 161</span> : : { GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },</span> |
| <span id="L162"><span class="lineNum"> 162</span> : : { GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },</span> |
| <span id="L163"><span class="lineNum"> 163</span> : : { GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },</span> |
| <span id="L164"><span class="lineNum"> 164</span> : : { GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },</span> |
| <span id="L165"><span class="lineNum"> 165</span> : : { GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },</span> |
| <span id="L166"><span class="lineNum"> 166</span> : : /* GPU memory from 4TB + 128GB*GPU. 4 GPUs only */</span> |
| <span id="L167"><span class="lineNum"> 167</span> : : { GPU_MEM_4T_UP, 0, 0x0000040000000000ull, 0x0000002000000000ull },</span> |
| <span id="L168"><span class="lineNum"> 168</span> : : { GPU_MEM_4T_UP, 1, 0x0000042000000000ull, 0x0000002000000000ull },</span> |
| <span id="L169"><span class="lineNum"> 169</span> : : { GPU_MEM_4T_UP, 2, 0x0000044000000000ull, 0x0000002000000000ull },</span> |
| <span id="L170"><span class="lineNum"> 170</span> : : { GPU_MEM_4T_UP, 3, 0x0000046000000000ull, 0x0000002000000000ull },</span> |
| <span id="L171"><span class="lineNum"> 171</span> : : </span> |
| <span id="L172"><span class="lineNum"> 172</span> : : /*</span> |
| <span id="L173"><span class="lineNum"> 173</span> : : * OpenCAPI LPC Memory</span> |
| <span id="L174"><span class="lineNum"> 174</span> : : *</span> |
| <span id="L175"><span class="lineNum"> 175</span> : : * With chip address extension enabled, we allocate 4TB ranges</span> |
| <span id="L176"><span class="lineNum"> 176</span> : : * (in the second non-mirrored region) for each OpenCAPI link</span> |
| <span id="L177"><span class="lineNum"> 177</span> : : * by varying the upper 2 bits of the group ID.</span> |
| <span id="L178"><span class="lineNum"> 178</span> : : *</span> |
| <span id="L179"><span class="lineNum"> 179</span> : : * We don't currently support >4TB ranges.</span> |
| <span id="L180"><span class="lineNum"> 180</span> : : */</span> |
| <span id="L181"><span class="lineNum"> 181</span> : : { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },</span> |
| <span id="L182"><span class="lineNum"> 182</span> : : { OCAPI_MEM, 1, 0x0002800000000000ull, 0x0000040000000000ull },</span> |
| <span id="L183"><span class="lineNum"> 183</span> : : { OCAPI_MEM, 2, 0x0003000000000000ull, 0x0000040000000000ull },</span> |
| <span id="L184"><span class="lineNum"> 184</span> : : { OCAPI_MEM, 3, 0x0003800000000000ull, 0x0000040000000000ull },</span> |
| <span id="L185"><span class="lineNum"> 185</span> : : </span> |
| <span id="L186"><span class="lineNum"> 186</span> : : /* 0 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L187"><span class="lineNum"> 187</span> : : { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },</span> |
| <span id="L188"><span class="lineNum"> 188</span> : : { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },</span> |
| <span id="L189"><span class="lineNum"> 189</span> : : { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },</span> |
| <span id="L190"><span class="lineNum"> 190</span> : : { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },</span> |
| <span id="L191"><span class="lineNum"> 191</span> : : { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },</span> |
| <span id="L192"><span class="lineNum"> 192</span> : : { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },</span> |
| <span id="L193"><span class="lineNum"> 193</span> : : { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },</span> |
| <span id="L194"><span class="lineNum"> 194</span> : : { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },</span> |
| <span id="L195"><span class="lineNum"> 195</span> : : { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },</span> |
| <span id="L196"><span class="lineNum"> 196</span> : : { PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },</span> |
| <span id="L197"><span class="lineNum"> 197</span> : : { PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },</span> |
| <span id="L198"><span class="lineNum"> 198</span> : : { PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },</span> |
| <span id="L199"><span class="lineNum"> 199</span> : : { PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },</span> |
| <span id="L200"><span class="lineNum"> 200</span> : : { PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },</span> |
| <span id="L201"><span class="lineNum"> 201</span> : : { PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },</span> |
| <span id="L202"><span class="lineNum"> 202</span> : : { PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },</span> |
| <span id="L203"><span class="lineNum"> 203</span> : : { PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },</span> |
| <span id="L204"><span class="lineNum"> 204</span> : : { PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },</span> |
| <span id="L205"><span class="lineNum"> 205</span> : : { PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },</span> |
| <span id="L206"><span class="lineNum"> 206</span> : : { PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },</span> |
| <span id="L207"><span class="lineNum"> 207</span> : : { PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },</span> |
| <span id="L208"><span class="lineNum"> 208</span> : : { RESV , 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },</span> |
| <span id="L209"><span class="lineNum"> 209</span> : : { NPU_OCAPI_MMIO , 0, 0x000600d000000000ull, 0x0000000800000000ull },</span> |
| <span id="L210"><span class="lineNum"> 210</span> : : { NPU_OCAPI_MMIO , 1, 0x000600d800000000ull, 0x0000000800000000ull },</span> |
| <span id="L211"><span class="lineNum"> 211</span> : : { NPU_OCAPI_MMIO , 2, 0x000600e000000000ull, 0x0000000800000000ull },</span> |
| <span id="L212"><span class="lineNum"> 212</span> : : { NPU_OCAPI_MMIO , 3, 0x000600e800000000ull, 0x0000000800000000ull },</span> |
| <span id="L213"><span class="lineNum"> 213</span> : : { NPU_OCAPI_MMIO , 4, 0x000600f000000000ull, 0x0000000800000000ull },</span> |
| <span id="L214"><span class="lineNum"> 214</span> : : { NPU_OCAPI_MMIO , 5, 0x000600f800000000ull, 0x0000000800000000ull },</span> |
| <span id="L215"><span class="lineNum"> 215</span> : : </span> |
| <span id="L216"><span class="lineNum"> 216</span> : : /* 1 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L217"><span class="lineNum"> 217</span> : : { XIVE_VC , 0, 0x0006010000000000ull, 0x0000008000000000ull },</span> |
| <span id="L218"><span class="lineNum"> 218</span> : : { XIVE_PC , 0, 0x0006018000000000ull, 0x0000001000000000ull },</span> |
| <span id="L219"><span class="lineNum"> 219</span> : : { VAS_USER_WIN , 0, 0x0006019000000000ull, 0x0000000100000000ull },</span> |
| <span id="L220"><span class="lineNum"> 220</span> : : { VAS_HYP_WIN , 0, 0x0006019100000000ull, 0x0000000002000000ull },</span> |
| <span id="L221"><span class="lineNum"> 221</span> : : { RESV , 1, 0x0006019102000000ull, 0x000000001e000000ull },</span> |
| <span id="L222"><span class="lineNum"> 222</span> : : { OCAB_XIVE_ESB , 0, 0x0006019120000000ull, 0x0000000020000000ull },</span> |
| <span id="L223"><span class="lineNum"> 223</span> : : { RESV , 3, 0x0006019140000000ull, 0x0000006ec0000000ull },</span> |
| <span id="L224"><span class="lineNum"> 224</span> : : </span> |
| <span id="L225"><span class="lineNum"> 225</span> : : /* 2 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L226"><span class="lineNum"> 226</span> : : { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },</span> |
| <span id="L227"><span class="lineNum"> 227</span> : : { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },</span> |
| <span id="L228"><span class="lineNum"> 228</span> : : { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },</span> |
| <span id="L229"><span class="lineNum"> 229</span> : : { RESV , 4, 0x000602c000000000ull, 0x0000004000000000ull },</span> |
| <span id="L230"><span class="lineNum"> 230</span> : : </span> |
| <span id="L231"><span class="lineNum"> 231</span> : : /* 3 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L232"><span class="lineNum"> 232</span> : : { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },</span> |
| <span id="L233"><span class="lineNum"> 233</span> : : { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },</span> |
| <span id="L234"><span class="lineNum"> 234</span> : : { NPU_REGS , 0, 0x0006030200000000ull, 0x0000000001000000ull },</span> |
| <span id="L235"><span class="lineNum"> 235</span> : : { NPU_USR , 0, 0x0006030201000000ull, 0x0000000000200000ull },</span> |
| <span id="L236"><span class="lineNum"> 236</span> : : { NPU_PHY , 0, 0x0006030201200000ull, 0x0000000000200000ull },</span> |
| <span id="L237"><span class="lineNum"> 237</span> : : { NPU_PHY , 1, 0x0006030201400000ull, 0x0000000000200000ull },</span> |
| <span id="L238"><span class="lineNum"> 238</span> : : { NPU_NTL , 0, 0x0006030201600000ull, 0x0000000000020000ull },</span> |
| <span id="L239"><span class="lineNum"> 239</span> : : { NPU_NTL , 1, 0x0006030201620000ull, 0x0000000000020000ull },</span> |
| <span id="L240"><span class="lineNum"> 240</span> : : { NPU_NTL , 2, 0x0006030201640000ull, 0x0000000000020000ull },</span> |
| <span id="L241"><span class="lineNum"> 241</span> : : { NPU_NTL , 3, 0x0006030201660000ull, 0x0000000000020000ull },</span> |
| <span id="L242"><span class="lineNum"> 242</span> : : { NPU_NTL , 4, 0x0006030201680000ull, 0x0000000000020000ull },</span> |
| <span id="L243"><span class="lineNum"> 243</span> : : { NPU_NTL , 5, 0x00060302016a0000ull, 0x0000000000020000ull },</span> |
| <span id="L244"><span class="lineNum"> 244</span> : : { NPU_GENID , 0, 0x00060302016c0000ull, 0x0000000000020000ull },</span> |
| <span id="L245"><span class="lineNum"> 245</span> : : { NPU_GENID , 1, 0x00060302016e0000ull, 0x0000000000020000ull },</span> |
| <span id="L246"><span class="lineNum"> 246</span> : : { NPU_GENID , 2, 0x0006030201700000ull, 0x0000000000020000ull },</span> |
| <span id="L247"><span class="lineNum"> 247</span> : : { RESV , 5, 0x0006030201720000ull, 0x00000000018e0000ull },</span> |
| <span id="L248"><span class="lineNum"> 248</span> : : { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },</span> |
| <span id="L249"><span class="lineNum"> 249</span> : : { XIVE_IC , 0, 0x0006030203100000ull, 0x0000000000080000ull },</span> |
| <span id="L250"><span class="lineNum"> 250</span> : : { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },</span> |
| <span id="L251"><span class="lineNum"> 251</span> : : { PSIHB_ESB , 0, 0x00060302031c0000ull, 0x0000000000010000ull },</span> |
| <span id="L252"><span class="lineNum"> 252</span> : : { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },</span> |
| <span id="L253"><span class="lineNum"> 253</span> : : { RESV , 6, 0x00060302031e0000ull, 0x000000001ce20000ull },</span> |
| <span id="L254"><span class="lineNum"> 254</span> : : { CENTAUR_SCOM , 0, 0x0006030220000000ull, 0x0000000020000000ull },</span> |
| <span id="L255"><span class="lineNum"> 255</span> : : { RESV , 7, 0x0006030240000000ull, 0x000000f9c0000000ull },</span> |
| <span id="L256"><span class="lineNum"> 256</span> : : { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },</span> |
| <span id="L257"><span class="lineNum"> 257</span> : : </span> |
| <span id="L258"><span class="lineNum"> 258</span> : : /* NULL entry at end */</span> |
| <span id="L259"><span class="lineNum"> 259</span> : : { NULL_MAP, 0, 0, 0 },</span> |
| <span id="L260"><span class="lineNum"> 260</span> : : };</span> |
| <span id="L261"><span class="lineNum"> 261</span> : : </span> |
| <span id="L262"><span class="lineNum"> 262</span> : : static const struct phys_map_info phys_map_nimbus = {</span> |
| <span id="L263"><span class="lineNum"> 263</span> : : .chip_select_shift = 42,</span> |
| <span id="L264"><span class="lineNum"> 264</span> : : .table = phys_map_table_nimbus,</span> |
| <span id="L265"><span class="lineNum"> 265</span> : : };</span> |
| <span id="L266"><span class="lineNum"> 266</span> : : </span> |
| <span id="L267"><span class="lineNum"> 267</span> : : static const struct phys_map_entry phys_map_table_axone[] = {</span> |
| <span id="L268"><span class="lineNum"> 268</span> : : </span> |
| <span id="L269"><span class="lineNum"> 269</span> : : /* System memory up to 4TB minus GPU memory */</span> |
| <span id="L270"><span class="lineNum"> 270</span> : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },</span> |
| <span id="L271"><span class="lineNum"> 271</span> : : /* GPU memory from 4TB - 128GB*GPU */</span> |
| <span id="L272"><span class="lineNum"> 272</span> : : { GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },</span> |
| <span id="L273"><span class="lineNum"> 273</span> : : { GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },</span> |
| <span id="L274"><span class="lineNum"> 274</span> : : { GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },</span> |
| <span id="L275"><span class="lineNum"> 275</span> : : { GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },</span> |
| <span id="L276"><span class="lineNum"> 276</span> : : { GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },</span> |
| <span id="L277"><span class="lineNum"> 277</span> : : { GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },</span> |
| <span id="L278"><span class="lineNum"> 278</span> : : </span> |
| <span id="L279"><span class="lineNum"> 279</span> : : /* 0 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L280"><span class="lineNum"> 280</span> : : { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },</span> |
| <span id="L281"><span class="lineNum"> 281</span> : : { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },</span> |
| <span id="L282"><span class="lineNum"> 282</span> : : { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },</span> |
| <span id="L283"><span class="lineNum"> 283</span> : : { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },</span> |
| <span id="L284"><span class="lineNum"> 284</span> : : { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },</span> |
| <span id="L285"><span class="lineNum"> 285</span> : : { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },</span> |
| <span id="L286"><span class="lineNum"> 286</span> : : { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },</span> |
| <span id="L287"><span class="lineNum"> 287</span> : : { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },</span> |
| <span id="L288"><span class="lineNum"> 288</span> : : { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },</span> |
| <span id="L289"><span class="lineNum"> 289</span> : : { PHB4_XIVE_ESB, 0, 0x000600c300000000ull, 0x0000000020000000ull },</span> |
| <span id="L290"><span class="lineNum"> 290</span> : : { PHB4_XIVE_ESB, 1, 0x000600c320000000ull, 0x0000000020000000ull },</span> |
| <span id="L291"><span class="lineNum"> 291</span> : : { PHB4_XIVE_ESB, 2, 0x000600c340000000ull, 0x0000000020000000ull },</span> |
| <span id="L292"><span class="lineNum"> 292</span> : : { PHB4_XIVE_ESB, 3, 0x000600c360000000ull, 0x0000000020000000ull },</span> |
| <span id="L293"><span class="lineNum"> 293</span> : : { PHB4_XIVE_ESB, 4, 0x000600c380000000ull, 0x0000000020000000ull },</span> |
| <span id="L294"><span class="lineNum"> 294</span> : : { PHB4_XIVE_ESB, 5, 0x000600c3a0000000ull, 0x0000000020000000ull },</span> |
| <span id="L295"><span class="lineNum"> 295</span> : : { PHB4_REG_SPC, 0, 0x000600c3c0000000ull, 0x0000000000100000ull },</span> |
| <span id="L296"><span class="lineNum"> 296</span> : : { PHB4_REG_SPC, 1, 0x000600c3c0100000ull, 0x0000000000100000ull },</span> |
| <span id="L297"><span class="lineNum"> 297</span> : : { PHB4_REG_SPC, 2, 0x000600c3c0200000ull, 0x0000000000100000ull },</span> |
| <span id="L298"><span class="lineNum"> 298</span> : : { PHB4_REG_SPC, 3, 0x000600c3c0300000ull, 0x0000000000100000ull },</span> |
| <span id="L299"><span class="lineNum"> 299</span> : : { PHB4_REG_SPC, 4, 0x000600c3c0400000ull, 0x0000000000100000ull },</span> |
| <span id="L300"><span class="lineNum"> 300</span> : : { PHB4_REG_SPC, 5, 0x000600c3c0500000ull, 0x0000000000100000ull },</span> |
| <span id="L301"><span class="lineNum"> 301</span> : : { RESV, 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },</span> |
| <span id="L302"><span class="lineNum"> 302</span> : : { NPU_OCAPI_MMIO, 0, 0x000600d000000000ull, 0x0000000800000000ull },</span> |
| <span id="L303"><span class="lineNum"> 303</span> : : { NPU_OCAPI_MMIO, 1, 0x000600d800000000ull, 0x0000000800000000ull },</span> |
| <span id="L304"><span class="lineNum"> 304</span> : : { NPU_OCAPI_MMIO, 2, 0x000600e000000000ull, 0x0000000800000000ull },</span> |
| <span id="L305"><span class="lineNum"> 305</span> : : { NPU_OCAPI_MMIO, 3, 0x000600e800000000ull, 0x0000000800000000ull },</span> |
| <span id="L306"><span class="lineNum"> 306</span> : : { NPU_OCAPI_MMIO, 4, 0x000600f000000000ull, 0x0000000800000000ull },</span> |
| <span id="L307"><span class="lineNum"> 307</span> : : { NPU_OCAPI_MMIO, 5, 0x000600f800000000ull, 0x0000000800000000ull },</span> |
| <span id="L308"><span class="lineNum"> 308</span> : : </span> |
| <span id="L309"><span class="lineNum"> 309</span> : : /* 1 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L310"><span class="lineNum"> 310</span> : : { XIVE_VC, 0, 0x0006010000000000ull, 0x0000008000000000ull },</span> |
| <span id="L311"><span class="lineNum"> 311</span> : : { XIVE_PC, 0, 0x0006018000000000ull, 0x0000004000000000ull },</span> |
| <span id="L312"><span class="lineNum"> 312</span> : : { VAS_USER_WIN, 0, 0x000601c000000000ull, 0x0000000100000000ull },</span> |
| <span id="L313"><span class="lineNum"> 313</span> : : { VAS_HYP_WIN, 0, 0x000601c100000000ull, 0x0000000002000000ull },</span> |
| <span id="L314"><span class="lineNum"> 314</span> : : { RESV, 1, 0x000601c102000000ull, 0x0000003efe000000ull },</span> |
| <span id="L315"><span class="lineNum"> 315</span> : : </span> |
| <span id="L316"><span class="lineNum"> 316</span> : : /* 2 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L317"><span class="lineNum"> 317</span> : : { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },</span> |
| <span id="L318"><span class="lineNum"> 318</span> : : { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },</span> |
| <span id="L319"><span class="lineNum"> 319</span> : : { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },</span> |
| <span id="L320"><span class="lineNum"> 320</span> : : { RESV, 2, 0x000602c000000000ull, 0x0000004000000000ull },</span> |
| <span id="L321"><span class="lineNum"> 321</span> : : </span> |
| <span id="L322"><span class="lineNum"> 322</span> : : /* 3 TB offset @ MMIO 0x0006000000000000ull */</span> |
| <span id="L323"><span class="lineNum"> 323</span> : : { LPC_BUS, 0, 0x0006030000000000ull, 0x0000000100000000ull },</span> |
| <span id="L324"><span class="lineNum"> 324</span> : : { FSP_MMIO, 0, 0x0006030100000000ull, 0x0000000100000000ull },</span> |
| <span id="L325"><span class="lineNum"> 325</span> : : { RESV, 3, 0x0006030200000000ull, 0x0000000003000000ull },</span> |
| <span id="L326"><span class="lineNum"> 326</span> : : { PSIHB_REG, 0, 0x0006030203000000ull, 0x0000000000100000ull },</span> |
| <span id="L327"><span class="lineNum"> 327</span> : : { XIVE_IC, 0, 0x0006030203100000ull, 0x0000000000080000ull },</span> |
| <span id="L328"><span class="lineNum"> 328</span> : : { XIVE_TM, 0, 0x0006030203180000ull, 0x0000000000040000ull },</span> |
| <span id="L329"><span class="lineNum"> 329</span> : : { PSIHB_ESB, 0, 0x00060302031c0000ull, 0x0000000000010000ull },</span> |
| <span id="L330"><span class="lineNum"> 330</span> : : { NX_RNG, 0, 0x00060302031d0000ull, 0x0000000000010000ull },</span> |
| <span id="L331"><span class="lineNum"> 331</span> : : { RESV, 4, 0x00060302031e0000ull, 0x00000001fce20000ull },</span> |
| <span id="L332"><span class="lineNum"> 332</span> : : { MC_OCMB_CFG, 0, 0x0006030400000000ull, 0x0000000080000000ull },</span> |
| <span id="L333"><span class="lineNum"> 333</span> : : { MC_OCMB_CFG, 1, 0x0006030480000000ull, 0x0000000080000000ull },</span> |
| <span id="L334"><span class="lineNum"> 334</span> : : { MC_OCMB_MMIO, 0, 0x0006030500000000ull, 0x0000000080000000ull },</span> |
| <span id="L335"><span class="lineNum"> 335</span> : : { MC_OCMB_MMIO, 1, 0x0006030580000000ull, 0x0000000080000000ull },</span> |
| <span id="L336"><span class="lineNum"> 336</span> : : { MC_OCMB_CFG, 2, 0x0006030600000000ull, 0x0000000080000000ull },</span> |
| <span id="L337"><span class="lineNum"> 337</span> : : { MC_OCMB_CFG, 3, 0x0006030680000000ull, 0x0000000080000000ull },</span> |
| <span id="L338"><span class="lineNum"> 338</span> : : { MC_OCMB_MMIO, 2, 0x0006030700000000ull, 0x0000000080000000ull },</span> |
| <span id="L339"><span class="lineNum"> 339</span> : : { MC_OCMB_MMIO, 3, 0x0006030780000000ull, 0x0000000080000000ull },</span> |
| <span id="L340"><span class="lineNum"> 340</span> : : { MC_OCMB_CFG, 4, 0x0006030800000000ull, 0x0000000080000000ull },</span> |
| <span id="L341"><span class="lineNum"> 341</span> : : { MC_OCMB_CFG, 5, 0x0006030880000000ull, 0x0000000080000000ull },</span> |
| <span id="L342"><span class="lineNum"> 342</span> : : { MC_OCMB_MMIO, 4, 0x0006030900000000ull, 0x0000000080000000ull },</span> |
| <span id="L343"><span class="lineNum"> 343</span> : : { MC_OCMB_MMIO, 5, 0x0006030980000000ull, 0x0000000080000000ull },</span> |
| <span id="L344"><span class="lineNum"> 344</span> : : { MC_OCMB_CFG, 6, 0x0006030a00000000ull, 0x0000000080000000ull },</span> |
| <span id="L345"><span class="lineNum"> 345</span> : : { MC_OCMB_CFG, 7, 0x0006030a80000000ull, 0x0000000080000000ull },</span> |
| <span id="L346"><span class="lineNum"> 346</span> : : { MC_OCMB_MMIO, 6, 0x0006030b00000000ull, 0x0000000080000000ull },</span> |
| <span id="L347"><span class="lineNum"> 347</span> : : { MC_OCMB_MMIO, 7, 0x0006030b80000000ull, 0x0000000080000000ull },</span> |
| <span id="L348"><span class="lineNum"> 348</span> : : { MC_OCMB_CFG, 8, 0x0006030c00000000ull, 0x0000000080000000ull },</span> |
| <span id="L349"><span class="lineNum"> 349</span> : : { MC_OCMB_CFG, 9, 0x0006030c80000000ull, 0x0000000080000000ull },</span> |
| <span id="L350"><span class="lineNum"> 350</span> : : { MC_OCMB_MMIO, 8, 0x0006030d00000000ull, 0x0000000080000000ull },</span> |
| <span id="L351"><span class="lineNum"> 351</span> : : { MC_OCMB_MMIO, 9, 0x0006030d80000000ull, 0x0000000080000000ull },</span> |
| <span id="L352"><span class="lineNum"> 352</span> : : { MC_OCMB_CFG, 10, 0x0006030e00000000ull, 0x0000000080000000ull },</span> |
| <span id="L353"><span class="lineNum"> 353</span> : : { MC_OCMB_CFG, 11, 0x0006030e80000000ull, 0x0000000080000000ull },</span> |
| <span id="L354"><span class="lineNum"> 354</span> : : { MC_OCMB_MMIO, 10, 0x0006030f00000000ull, 0x0000000080000000ull },</span> |
| <span id="L355"><span class="lineNum"> 355</span> : : { MC_OCMB_MMIO, 11, 0x0006030f80000000ull, 0x0000000080000000ull },</span> |
| <span id="L356"><span class="lineNum"> 356</span> : : { MC_OCMB_CFG, 12, 0x0006031000000000ull, 0x0000000080000000ull },</span> |
| <span id="L357"><span class="lineNum"> 357</span> : : { MC_OCMB_CFG, 13, 0x0006031080000000ull, 0x0000000080000000ull },</span> |
| <span id="L358"><span class="lineNum"> 358</span> : : { MC_OCMB_MMIO, 12, 0x0006031100000000ull, 0x0000000080000000ull },</span> |
| <span id="L359"><span class="lineNum"> 359</span> : : { MC_OCMB_MMIO, 13, 0x0006031180000000ull, 0x0000000080000000ull },</span> |
| <span id="L360"><span class="lineNum"> 360</span> : : { MC_OCMB_CFG, 14, 0x0006031200000000ull, 0x0000000080000000ull },</span> |
| <span id="L361"><span class="lineNum"> 361</span> : : { MC_OCMB_CFG, 15, 0x0006031280000000ull, 0x0000000080000000ull },</span> |
| <span id="L362"><span class="lineNum"> 362</span> : : { MC_OCMB_MMIO, 14, 0x0006031300000000ull, 0x0000000080000000ull },</span> |
| <span id="L363"><span class="lineNum"> 363</span> : : { MC_OCMB_MMIO, 15, 0x0006031380000000ull, 0x0000000080000000ull },</span> |
| <span id="L364"><span class="lineNum"> 364</span> : : { RESV, 5, 0x0006031400000000ull, 0x000000d800000000ull },</span> |
| <span id="L365"><span class="lineNum"> 365</span> : : { NPU_REGS, 0, 0x000603ec00000000ull, 0x0000000001000000ull },</span> |
| <span id="L366"><span class="lineNum"> 366</span> : : { NPU_REGS, 1, 0x000603ec01000000ull, 0x0000000001000000ull },</span> |
| <span id="L367"><span class="lineNum"> 367</span> : : { NPU_REGS, 2, 0x000603ec02000000ull, 0x0000000001000000ull },</span> |
| <span id="L368"><span class="lineNum"> 368</span> : : { NPU_NTL, 0, 0x000603ec03000000ull, 0x0000000000020000ull },</span> |
| <span id="L369"><span class="lineNum"> 369</span> : : { NPU_NTL, 1, 0x000603ec03020000ull, 0x0000000000020000ull },</span> |
| <span id="L370"><span class="lineNum"> 370</span> : : { NPU_NTL, 2, 0x000603ec03040000ull, 0x0000000000020000ull },</span> |
| <span id="L371"><span class="lineNum"> 371</span> : : { NPU_NTL, 3, 0x000603ec03060000ull, 0x0000000000020000ull },</span> |
| <span id="L372"><span class="lineNum"> 372</span> : : { NPU_GENID, 0, 0x000603ec03080000ull, 0x0000000000080000ull },</span> |
| <span id="L373"><span class="lineNum"> 373</span> : : { NPU_NTL, 4, 0x000603ec03100000ull, 0x0000000000020000ull },</span> |
| <span id="L374"><span class="lineNum"> 374</span> : : { NPU_NTL, 5, 0x000603ec03120000ull, 0x0000000000020000ull },</span> |
| <span id="L375"><span class="lineNum"> 375</span> : : { NPU_NTL, 6, 0x000603ec03140000ull, 0x0000000000020000ull },</span> |
| <span id="L376"><span class="lineNum"> 376</span> : : { NPU_NTL, 7, 0x000603ec03160000ull, 0x0000000000020000ull },</span> |
| <span id="L377"><span class="lineNum"> 377</span> : : { NPU_GENID, 1, 0x000603ec03180000ull, 0x0000000000080000ull },</span> |
| <span id="L378"><span class="lineNum"> 378</span> : : { NPU_NTL, 8, 0x000603ec03200000ull, 0x0000000000020000ull },</span> |
| <span id="L379"><span class="lineNum"> 379</span> : : { NPU_NTL, 9, 0x000603ec03220000ull, 0x0000000000020000ull },</span> |
| <span id="L380"><span class="lineNum"> 380</span> : : { NPU_NTL, 10, 0x000603ec03240000ull, 0x0000000000020000ull },</span> |
| <span id="L381"><span class="lineNum"> 381</span> : : { NPU_NTL, 11, 0x000603ec03260000ull, 0x0000000000020000ull },</span> |
| <span id="L382"><span class="lineNum"> 382</span> : : { NPU_GENID, 2, 0x000603ec03280000ull, 0x0000000000080000ull },</span> |
| <span id="L383"><span class="lineNum"> 383</span> : : { RESV, 6, 0x000603ec03300000ull, 0x0000000ffcd00000ull },</span> |
| <span id="L384"><span class="lineNum"> 384</span> : : { XSCOM, 0, 0x000603fc00000000ull, 0x0000000400000000ull },</span> |
| <span id="L385"><span class="lineNum"> 385</span> : : </span> |
| <span id="L386"><span class="lineNum"> 386</span> : : /* NULL entry at end */</span> |
| <span id="L387"><span class="lineNum"> 387</span> : : { NULL_MAP, 0, 0, 0 },</span> |
| <span id="L388"><span class="lineNum"> 388</span> : : };</span> |
| <span id="L389"><span class="lineNum"> 389</span> : : </span> |
| <span id="L390"><span class="lineNum"> 390</span> : : static const struct phys_map_info phys_map_axone = {</span> |
| <span id="L391"><span class="lineNum"> 391</span> : : .chip_select_shift = 42,</span> |
| <span id="L392"><span class="lineNum"> 392</span> : : .table = phys_map_table_axone,</span> |
| <span id="L393"><span class="lineNum"> 393</span> : : };</span> |
| <span id="L394"><span class="lineNum"> 394</span> : : </span> |
| <span id="L395"><span class="lineNum"> 395</span> : : static const struct phys_map_info phys_map_p10 = {</span> |
| <span id="L396"><span class="lineNum"> 396</span> : : .chip_select_shift = 44,</span> |
| <span id="L397"><span class="lineNum"> 397</span> : : .table = phys_map_table_p10,</span> |
| <span id="L398"><span class="lineNum"> 398</span> : : };</span> |
| <span id="L399"><span class="lineNum"> 399</span> : : </span> |
| <span id="L400"><span class="lineNum"> 400</span> :<span class="tlaGNC tlaBgGNC"> 14240 : static inline bool phys_map_entry_null(const struct phys_map_entry *e)</span></span> |
| <span id="L401"><span class="lineNum"> 401</span> : : {</span> |
| <span id="L402"><span class="lineNum"> 402</span> :<span class="tlaGNC"> 14240 : if (e->type == NULL_MAP)</span></span> |
| <span id="L403"><span class="lineNum"> 403</span> :<span class="tlaGNC"> 9 : return true;</span></span> |
| <span id="L404"><span class="lineNum"> 404</span> :<span class="tlaGNC"> 14231 : return false;</span></span> |
| <span id="L405"><span class="lineNum"> 405</span> : : }</span> |
| <span id="L406"><span class="lineNum"> 406</span> : : </span> |
| <span id="L407"><span class="lineNum"> 407</span> : : </span> |
| <span id="L408"><span class="lineNum"> 408</span> : : /* This crashes skiboot on error as any bad calls here are almost</span> |
| <span id="L409"><span class="lineNum"> 409</span> : : * certainly a developer error</span> |
| <span id="L410"><span class="lineNum"> 410</span> : : */</span> |
| <span id="L411"><span class="lineNum"> 411</span> :<span class="tlaGNC"> 280 : void __phys_map_get(uint64_t topology_idx, uint64_t gcid, enum phys_map_type type,</span></span> |
| <span id="L412"><span class="lineNum"> 412</span> : : int index, uint64_t *addr, uint64_t *size) {</span> |
| <span id="L413"><span class="lineNum"> 413</span> : : const struct phys_map_entry *e;</span> |
| <span id="L414"><span class="lineNum"> 414</span> : : uint64_t a;</span> |
| <span id="L415"><span class="lineNum"> 415</span> : : </span> |
| <span id="L416"><span class="lineNum"> 416</span> :<span class="tlaGNC"> 280 : if (!phys_map)</span></span> |
| <span id="L417"><span class="lineNum"> 417</span> :<span class="tlaUNC tlaBgUNC"> 0 : goto error;</span></span> |
| <span id="L418"><span class="lineNum"> 418</span> : : </span> |
| <span id="L419"><span class="lineNum"> 419</span> : : /* Find entry in table */</span> |
| <span id="L420"><span class="lineNum"> 420</span> :<span class="tlaGNC tlaBgGNC"> 280 : for (e = phys_map->table; ; e++) {</span></span> |
| <span id="L421"><span class="lineNum"> 421</span> : : </span> |
| <span id="L422"><span class="lineNum"> 422</span> : : /* End of table */</span> |
| <span id="L423"><span class="lineNum"> 423</span> :<span class="tlaGNC"> 13391 : if (phys_map_entry_null(e))</span></span> |
| <span id="L424"><span class="lineNum"> 424</span> :<span class="tlaUNC tlaBgUNC"> 0 : goto error;</span></span> |
| <span id="L425"><span class="lineNum"> 425</span> : : </span> |
| <span id="L426"><span class="lineNum"> 426</span> : : /* Is this our entry? */</span> |
| <span id="L427"><span class="lineNum"> 427</span> :<span class="tlaGNC tlaBgGNC"> 13391 : if (e->type != type)</span></span> |
| <span id="L428"><span class="lineNum"> 428</span> :<span class="tlaGNC"> 12170 : continue;</span></span> |
| <span id="L429"><span class="lineNum"> 429</span> :<span class="tlaGNC"> 1221 : if (e->index != index)</span></span> |
| <span id="L430"><span class="lineNum"> 430</span> :<span class="tlaGNC"> 941 : continue;</span></span> |
| <span id="L431"><span class="lineNum"> 431</span> : : </span> |
| <span id="L432"><span class="lineNum"> 432</span> : : /* Found entry! */</span> |
| <span id="L433"><span class="lineNum"> 433</span> :<span class="tlaGNC"> 280 : break;</span></span> |
| <span id="L434"><span class="lineNum"> 434</span> : : }</span> |
| <span id="L435"><span class="lineNum"> 435</span> :<span class="tlaGNC"> 280 : a = e->addr;</span></span> |
| <span id="L436"><span class="lineNum"> 436</span> :<span class="tlaGNC"> 280 : a += topology_idx << (phys_map->chip_select_shift);</span></span> |
| <span id="L437"><span class="lineNum"> 437</span> : : </span> |
| <span id="L438"><span class="lineNum"> 438</span> :<span class="tlaGNC"> 280 : if (addr)</span></span> |
| <span id="L439"><span class="lineNum"> 439</span> :<span class="tlaGNC"> 280 : *addr = a;</span></span> |
| <span id="L440"><span class="lineNum"> 440</span> :<span class="tlaGNC"> 280 : if (size)</span></span> |
| <span id="L441"><span class="lineNum"> 441</span> :<span class="tlaGNC"> 280 : *size = e->size;</span></span> |
| <span id="L442"><span class="lineNum"> 442</span> : : </span> |
| <span id="L443"><span class="lineNum"> 443</span> :<span class="tlaGNC"> 280 : prlog(PR_TRACE, "Assigning BAR [%"PRIx64"] type:%02i index:%x "</span></span> |
| <span id="L444"><span class="lineNum"> 444</span> : : "0x%016"PRIx64" for 0x%016"PRIx64"\n",</span> |
| <span id="L445"><span class="lineNum"> 445</span> : : gcid, type, index, a, e->size);</span> |
| <span id="L446"><span class="lineNum"> 446</span> : : </span> |
| <span id="L447"><span class="lineNum"> 447</span> :<span class="tlaGNC"> 280 : return;</span></span> |
| <span id="L448"><span class="lineNum"> 448</span> : : </span> |
| <span id="L449"><span class="lineNum"> 449</span> :<span class="tlaUNC tlaBgUNC"> 0 : error:</span></span> |
| <span id="L450"><span class="lineNum"> 450</span> : : /* Something has gone really wrong */</span> |
| <span id="L451"><span class="lineNum"> 451</span> :<span class="tlaUNC"> 0 : prlog(PR_EMERG, "ERROR: Failed to lookup BAR type:%i index:%i\n",</span></span> |
| <span id="L452"><span class="lineNum"> 452</span> : : type, index);</span> |
| <span id="L453"><span class="lineNum"> 453</span> :<span class="tlaUNC"> 0 : assert(0);</span></span> |
| <span id="L454"><span class="lineNum"> 454</span> : : }</span> |
| <span id="L455"><span class="lineNum"> 455</span> : : </span> |
| <span id="L456"><span class="lineNum"> 456</span> :<span class="tlaUNC"> 0 : void phys_map_get(uint64_t gcid, enum phys_map_type type,</span></span> |
| <span id="L457"><span class="lineNum"> 457</span> : : int index, uint64_t *addr, uint64_t *size)</span> |
| <span id="L458"><span class="lineNum"> 458</span> : : {</span> |
| <span id="L459"><span class="lineNum"> 459</span> : : struct proc_chip *chip;</span> |
| <span id="L460"><span class="lineNum"> 460</span> :<span class="tlaUNC"> 0 : uint64_t topology_idx = gcid;</span></span> |
| <span id="L461"><span class="lineNum"> 461</span> : : </span> |
| <span id="L462"><span class="lineNum"> 462</span> :<span class="tlaUNC"> 0 : if (proc_gen >= proc_gen_p10) {</span></span> |
| <span id="L463"><span class="lineNum"> 463</span> :<span class="tlaUNC"> 0 : chip = get_chip(gcid);</span></span> |
| <span id="L464"><span class="lineNum"> 464</span> :<span class="tlaUNC"> 0 : topology_idx = chip->primary_topology;</span></span> |
| <span id="L465"><span class="lineNum"> 465</span> : : }</span> |
| <span id="L466"><span class="lineNum"> 466</span> : : </span> |
| <span id="L467"><span class="lineNum"> 467</span> :<span class="tlaUNC"> 0 : return __phys_map_get(topology_idx, gcid, type, index, addr, size);</span></span> |
| <span id="L468"><span class="lineNum"> 468</span> : : }</span> |
| <span id="L469"><span class="lineNum"> 469</span> : : </span> |
| <span id="L470"><span class="lineNum"> 470</span> :<span class="tlaGNC tlaBgGNC"> 3 : void phys_map_init(unsigned long pvr)</span></span> |
| <span id="L471"><span class="lineNum"> 471</span> : : {</span> |
| <span id="L472"><span class="lineNum"> 472</span> :<span class="tlaGNC"> 3 : const char *name = "unused";</span></span> |
| <span id="L473"><span class="lineNum"> 473</span> : : </span> |
| <span id="L474"><span class="lineNum"> 474</span> :<span class="tlaGNC"> 3 : phys_map = NULL;</span></span> |
| <span id="L475"><span class="lineNum"> 475</span> : : </span> |
| <span id="L476"><span class="lineNum"> 476</span> :<span class="tlaGNC"> 3 : if (proc_gen == proc_gen_p9) {</span></span> |
| <span id="L477"><span class="lineNum"> 477</span> :<span class="tlaGNC"> 2 : switch(PVR_TYPE(pvr)) {</span></span> |
| <span id="L478"><span class="lineNum"> 478</span> :<span class="tlaGNC"> 1 : case PVR_TYPE_P9P:</span></span> |
| <span id="L479"><span class="lineNum"> 479</span> :<span class="tlaGNC"> 1 : name = "axone";</span></span> |
| <span id="L480"><span class="lineNum"> 480</span> :<span class="tlaGNC"> 1 : phys_map = &phys_map_axone;</span></span> |
| <span id="L481"><span class="lineNum"> 481</span> :<span class="tlaGNC"> 1 : break;</span></span> |
| <span id="L482"><span class="lineNum"> 482</span> :<span class="tlaGNC"> 1 : default:</span></span> |
| <span id="L483"><span class="lineNum"> 483</span> :<span class="tlaGNC"> 1 : name = "nimbus";</span></span> |
| <span id="L484"><span class="lineNum"> 484</span> :<span class="tlaGNC"> 1 : phys_map = &phys_map_nimbus;</span></span> |
| <span id="L485"><span class="lineNum"> 485</span> : : }</span> |
| <span id="L486"><span class="lineNum"> 486</span> :<span class="tlaGNC"> 1 : } else if (proc_gen == proc_gen_p10) {</span></span> |
| <span id="L487"><span class="lineNum"> 487</span> :<span class="tlaGNC"> 1 : name = "p10";</span></span> |
| <span id="L488"><span class="lineNum"> 488</span> :<span class="tlaGNC"> 1 : phys_map = &phys_map_p10;</span></span> |
| <span id="L489"><span class="lineNum"> 489</span> :<span class="tlaUNC tlaBgUNC"> 0 : } else if (proc_gen == proc_gen_p11) {</span></span> |
| <span id="L490"><span class="lineNum"> 490</span> :<span class="tlaUNC"> 0 : name = "p11";</span></span> |
| <span id="L491"><span class="lineNum"> 491</span> :<span class="tlaUNC"> 0 : phys_map = &phys_map_p10;</span></span> |
| <span id="L492"><span class="lineNum"> 492</span> : : }</span> |
| <span id="L493"><span class="lineNum"> 493</span> : : </span> |
| <span id="L494"><span class="lineNum"> 494</span> :<span class="tlaGNC tlaBgGNC"> 3 : prlog(PR_DEBUG, "Assigning physical memory map table for %s\n", name);</span></span> |
| <span id="L495"><span class="lineNum"> 495</span> : : </span> |
| <span id="L496"><span class="lineNum"> 496</span> :<span class="tlaGNC"> 3 : }</span></span> |
| </pre> |
| </td> |
| </tr> |
| </table> |
| <br> |
| |
| <table width="100%" border=0 cellspacing=0 cellpadding=0> |
| <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr> |
| <tr><td class="versionInfo">Generated by: <a href="https://github.com//linux-test-project/lcov" target="_parent">LCOV version 2.0-1</a></td></tr> |
| </table> |
| <br> |
| |
| </body> |
| </html> |
