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| <td width="10%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">hdata</a> - pcia.c<span style="font-size: 80%;"> (source / <a href="pcia.c.func-c.html">functions</a>)</span></td> |
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| <td class="headerValue">skiboot.info</td> |
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| <td class="headerCovTableEntryMed">81.3 %</td> |
| <td class="headerCovTableEntry">107</td> |
| <td class="headerCovTableEntry">87</td> |
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| <td class="headerValue">2025-06-27 16:54:26</td> |
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| <td class="headerCovTableEntryHi">100.0 %</td> |
| <td class="headerCovTableEntry">5</td> |
| <td class="headerCovTableEntry">5</td> |
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| <pre class="sourceHeading"> Branch data Line data Source code</pre> |
| <pre class="source"> |
| <span id="L1"><span class="lineNum"> 1</span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</span> |
| <span id="L2"><span class="lineNum"> 2</span> : : /* Copyright 2013-2019 IBM Corp. */</span> |
| <span id="L3"><span class="lineNum"> 3</span> : : </span> |
| <span id="L4"><span class="lineNum"> 4</span> : : #include <skiboot.h></span> |
| <span id="L5"><span class="lineNum"> 5</span> : : #include "spira.h"</span> |
| <span id="L6"><span class="lineNum"> 6</span> : : #include <cpu.h></span> |
| <span id="L7"><span class="lineNum"> 7</span> : : #include <fsp.h></span> |
| <span id="L8"><span class="lineNum"> 8</span> : : #include <opal.h></span> |
| <span id="L9"><span class="lineNum"> 9</span> : : #include <ccan/str/str.h></span> |
| <span id="L10"><span class="lineNum"> 10</span> : : #include <device.h></span> |
| <span id="L11"><span class="lineNum"> 11</span> : : </span> |
| <span id="L12"><span class="lineNum"> 12</span> : : #include "hdata.h"</span> |
| <span id="L13"><span class="lineNum"> 13</span> : : </span> |
| <span id="L14"><span class="lineNum"> 14</span> : : #define PCIA_MAX_THREADS 8</span> |
| <span id="L15"><span class="lineNum"> 15</span> : : </span> |
| <span id="L16"><span class="lineNum"> 16</span> :<span class="tlaGNC tlaBgGNC"> 12 : static unsigned int pcia_index(const void *pcia)</span></span> |
| <span id="L17"><span class="lineNum"> 17</span> : : {</span> |
| <span id="L18"><span class="lineNum"> 18</span> :<span class="tlaGNC"> 12 : return (pcia - (void *)get_hdif(&spiras->ntuples.pcia, "SPPCIA"))</span></span> |
| <span id="L19"><span class="lineNum"> 19</span> :<span class="tlaGNC"> 12 : / be32_to_cpu(spiras->ntuples.pcia.alloc_len);</span></span> |
| <span id="L20"><span class="lineNum"> 20</span> : : }</span> |
| <span id="L21"><span class="lineNum"> 21</span> : : </span> |
| <span id="L22"><span class="lineNum"> 22</span> :<span class="tlaGNC"> 102 : static const struct sppcia_cpu_thread *find_tada(const void *pcia,</span></span> |
| <span id="L23"><span class="lineNum"> 23</span> : : unsigned int thread)</span> |
| <span id="L24"><span class="lineNum"> 24</span> : : {</span> |
| <span id="L25"><span class="lineNum"> 25</span> :<span class="tlaGNC"> 102 : int count = HDIF_get_iarray_size(pcia, SPPCIA_IDATA_THREAD_ARRAY);</span></span> |
| <span id="L26"><span class="lineNum"> 26</span> : : int i;</span> |
| <span id="L27"><span class="lineNum"> 27</span> : : </span> |
| <span id="L28"><span class="lineNum"> 28</span> :<span class="tlaGNC"> 102 : if (count < 0)</span></span> |
| <span id="L29"><span class="lineNum"> 29</span> :<span class="tlaUNC tlaBgUNC"> 0 : return NULL;</span></span> |
| <span id="L30"><span class="lineNum"> 30</span> : : </span> |
| <span id="L31"><span class="lineNum"> 31</span> :<span class="tlaGNC tlaBgGNC"> 438 : for (i = 0; i < count; i++) {</span></span> |
| <span id="L32"><span class="lineNum"> 32</span> : : const struct sppcia_cpu_thread *t;</span> |
| <span id="L33"><span class="lineNum"> 33</span> : : unsigned int size;</span> |
| <span id="L34"><span class="lineNum"> 34</span> : : </span> |
| <span id="L35"><span class="lineNum"> 35</span> :<span class="tlaGNC"> 438 : t = HDIF_get_iarray_item(pcia, SPPCIA_IDATA_THREAD_ARRAY,</span></span> |
| <span id="L36"><span class="lineNum"> 36</span> : : i, &size);</span> |
| <span id="L37"><span class="lineNum"> 37</span> :<span class="tlaGNC"> 438 : if (!t || size < sizeof(*t))</span></span> |
| <span id="L38"><span class="lineNum"> 38</span> :<span class="tlaUNC tlaBgUNC"> 0 : continue;</span></span> |
| <span id="L39"><span class="lineNum"> 39</span> :<span class="tlaGNC tlaBgGNC"> 438 : if (be32_to_cpu(t->phys_thread_id) == thread)</span></span> |
| <span id="L40"><span class="lineNum"> 40</span> :<span class="tlaGNC"> 102 : return t;</span></span> |
| <span id="L41"><span class="lineNum"> 41</span> : : }</span> |
| <span id="L42"><span class="lineNum"> 42</span> :<span class="tlaUNC tlaBgUNC"> 0 : return NULL;</span></span> |
| <span id="L43"><span class="lineNum"> 43</span> : : }</span> |
| <span id="L44"><span class="lineNum"> 44</span> : : </span> |
| <span id="L45"><span class="lineNum"> 45</span> :<span class="tlaGNC tlaBgGNC"> 6 : static void add_xics_icp(const void *pcia, u32 tcount, const char *compat)</span></span> |
| <span id="L46"><span class="lineNum"> 46</span> : : {</span> |
| <span id="L47"><span class="lineNum"> 47</span> : : const struct sppcia_cpu_thread *t;</span> |
| <span id="L48"><span class="lineNum"> 48</span> : : struct dt_node *icp;</span> |
| <span id="L49"><span class="lineNum"> 49</span> : : __be64 *reg;</span> |
| <span id="L50"><span class="lineNum"> 50</span> : : u32 i, irange[2], rsize;</span> |
| <span id="L51"><span class="lineNum"> 51</span> : : </span> |
| <span id="L52"><span class="lineNum"> 52</span> :<span class="tlaGNC"> 6 : rsize = tcount * 2 * sizeof(__be64);</span></span> |
| <span id="L53"><span class="lineNum"> 53</span> :<span class="tlaGNC"> 6 : reg = malloc(rsize);</span></span> |
| <span id="L54"><span class="lineNum"> 54</span> :<span class="tlaGNC"> 6 : assert(reg);</span></span> |
| <span id="L55"><span class="lineNum"> 55</span> : : </span> |
| <span id="L56"><span class="lineNum"> 56</span> : : /* Suppresses uninitialized warning from gcc */</span> |
| <span id="L57"><span class="lineNum"> 57</span> :<span class="tlaGNC"> 6 : irange[0] = 0;</span></span> |
| <span id="L58"><span class="lineNum"> 58</span> :<span class="tlaGNC"> 54 : for (i = 0; i < tcount; i++) {</span></span> |
| <span id="L59"><span class="lineNum"> 59</span> :<span class="tlaGNC"> 48 : t = find_tada(pcia, i);</span></span> |
| <span id="L60"><span class="lineNum"> 60</span> :<span class="tlaGNC"> 48 : assert(t);</span></span> |
| <span id="L61"><span class="lineNum"> 61</span> :<span class="tlaGNC"> 48 : if (i == 0)</span></span> |
| <span id="L62"><span class="lineNum"> 62</span> :<span class="tlaGNC"> 6 : irange[0] = be32_to_cpu(t->pir);</span></span> |
| <span id="L63"><span class="lineNum"> 63</span> :<span class="tlaGNC"> 48 : reg[i * 2] = cpu_to_be64(cleanup_addr(be64_to_cpu(t->ibase)));</span></span> |
| <span id="L64"><span class="lineNum"> 64</span> :<span class="tlaGNC"> 48 : reg[i * 2 + 1] = cpu_to_be64(0x1000);</span></span> |
| <span id="L65"><span class="lineNum"> 65</span> : : }</span> |
| <span id="L66"><span class="lineNum"> 66</span> :<span class="tlaGNC"> 6 : irange[1] = tcount;</span></span> |
| <span id="L67"><span class="lineNum"> 67</span> : : </span> |
| <span id="L68"><span class="lineNum"> 68</span> :<span class="tlaGNC"> 6 : icp = dt_new_addr(dt_root, "interrupt-controller", be64_to_cpu(reg[0]));</span></span> |
| <span id="L69"><span class="lineNum"> 69</span> :<span class="tlaGNC"> 6 : if (!icp) {</span></span> |
| <span id="L70"><span class="lineNum"> 70</span> :<span class="tlaUNC tlaBgUNC"> 0 : free(reg);</span></span> |
| <span id="L71"><span class="lineNum"> 71</span> :<span class="tlaUNC"> 0 : return;</span></span> |
| <span id="L72"><span class="lineNum"> 72</span> : : }</span> |
| <span id="L73"><span class="lineNum"> 73</span> : : </span> |
| <span id="L74"><span class="lineNum"> 74</span> :<span class="tlaGNC tlaBgGNC"> 6 : if (compat)</span></span> |
| <span id="L75"><span class="lineNum"> 75</span> :<span class="tlaGNC"> 6 : dt_add_property_strings(icp, "compatible", "ibm,ppc-xicp", compat);</span></span> |
| <span id="L76"><span class="lineNum"> 76</span> : : else</span> |
| <span id="L77"><span class="lineNum"> 77</span> :<span class="tlaUNC tlaBgUNC"> 0 : dt_add_property_strings(icp, "compatible", "ibm,ppc-xicp");</span></span> |
| <span id="L78"><span class="lineNum"> 78</span> :<span class="tlaGNC tlaBgGNC"> 6 : dt_add_property_cells(icp, "ibm,interrupt-server-ranges",</span></span> |
| <span id="L79"><span class="lineNum"> 79</span> : : irange[0], irange[1]);</span> |
| <span id="L80"><span class="lineNum"> 80</span> :<span class="tlaGNC"> 6 : dt_add_property(icp, "interrupt-controller", NULL, 0);</span></span> |
| <span id="L81"><span class="lineNum"> 81</span> :<span class="tlaGNC"> 6 : dt_add_property_cells(icp, "#interrupt-cells", 1);</span></span> |
| <span id="L82"><span class="lineNum"> 82</span> :<span class="tlaGNC"> 6 : dt_add_property(icp, "reg", reg, rsize);</span></span> |
| <span id="L83"><span class="lineNum"> 83</span> :<span class="tlaGNC"> 6 : dt_add_property_cells(icp, "#address-cells", 0);</span></span> |
| <span id="L84"><span class="lineNum"> 84</span> :<span class="tlaGNC"> 6 : dt_add_property_string(icp, "device_type",</span></span> |
| <span id="L85"><span class="lineNum"> 85</span> : : "PowerPC-External-Interrupt-Presentation");</span> |
| <span id="L86"><span class="lineNum"> 86</span> :<span class="tlaGNC"> 6 : free(reg);</span></span> |
| <span id="L87"><span class="lineNum"> 87</span> : : }</span> |
| <span id="L88"><span class="lineNum"> 88</span> : : </span> |
| <span id="L89"><span class="lineNum"> 89</span> :<span class="tlaGNC"> 6 : static struct dt_node *add_core_node(struct dt_node *cpus,</span></span> |
| <span id="L90"><span class="lineNum"> 90</span> : : const void *pcia,</span> |
| <span id="L91"><span class="lineNum"> 91</span> : : const struct sppcia_core_unique *id,</span> |
| <span id="L92"><span class="lineNum"> 92</span> : : bool okay)</span> |
| <span id="L93"><span class="lineNum"> 93</span> : : {</span> |
| <span id="L94"><span class="lineNum"> 94</span> : : const struct sppcia_cpu_thread *t;</span> |
| <span id="L95"><span class="lineNum"> 95</span> : : const struct sppcia_cpu_timebase *timebase;</span> |
| <span id="L96"><span class="lineNum"> 96</span> : : const struct sppcia_cpu_cache *cache;</span> |
| <span id="L97"><span class="lineNum"> 97</span> : : const struct sppcia_cpu_attr *attr;</span> |
| <span id="L98"><span class="lineNum"> 98</span> : : struct dt_node *cpu;</span> |
| <span id="L99"><span class="lineNum"> 99</span> : : const char *icp_compat;</span> |
| <span id="L100"><span class="lineNum"> 100</span> : : u32 i, size, threads, ve_flags, l2_phandle, chip_id;</span> |
| <span id="L101"><span class="lineNum"> 101</span> : : __be32 iserv[PCIA_MAX_THREADS];</span> |
| <span id="L102"><span class="lineNum"> 102</span> : : </span> |
| <span id="L103"><span class="lineNum"> 103</span> : : /* Look for thread 0 */</span> |
| <span id="L104"><span class="lineNum"> 104</span> :<span class="tlaGNC"> 6 : t = find_tada(pcia, 0);</span></span> |
| <span id="L105"><span class="lineNum"> 105</span> :<span class="tlaGNC"> 6 : if (!t) {</span></span> |
| <span id="L106"><span class="lineNum"> 106</span> :<span class="tlaUNC tlaBgUNC"> 0 : prerror("CORE[%i]: Failed to find thread 0 !\n",</span></span> |
| <span id="L107"><span class="lineNum"> 107</span> : : pcia_index(pcia));</span> |
| <span id="L108"><span class="lineNum"> 108</span> :<span class="tlaUNC"> 0 : return NULL;</span></span> |
| <span id="L109"><span class="lineNum"> 109</span> : : }</span> |
| <span id="L110"><span class="lineNum"> 110</span> : : </span> |
| <span id="L111"><span class="lineNum"> 111</span> :<span class="tlaGNC tlaBgGNC"> 6 : ve_flags = be32_to_cpu(id->verif_exist_flags);</span></span> |
| <span id="L112"><span class="lineNum"> 112</span> :<span class="tlaGNC"> 6 : threads = ((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK)</span></span> |
| <span id="L113"><span class="lineNum"> 113</span> :<span class="tlaGNC"> 6 : >> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1;</span></span> |
| <span id="L114"><span class="lineNum"> 114</span> :<span class="tlaGNC"> 6 : assert(threads <= PCIA_MAX_THREADS);</span></span> |
| <span id="L115"><span class="lineNum"> 115</span> : : </span> |
| <span id="L116"><span class="lineNum"> 116</span> :<span class="tlaGNC"> 6 : prlog(PR_INFO, "CORE[%i]: PIR=%.8x %s %s(%u threads)\n",</span></span> |
| <span id="L117"><span class="lineNum"> 117</span> : : pcia_index(pcia), be32_to_cpu(t->pir),</span> |
| <span id="L118"><span class="lineNum"> 118</span> : : ve_flags & CPU_ID_PCIA_RESERVED</span> |
| <span id="L119"><span class="lineNum"> 119</span> : : ? "**RESERVED**" : cpu_state(ve_flags),</span> |
| <span id="L120"><span class="lineNum"> 120</span> : : be32_to_cpu(t->pir) == boot_cpu->pir ? "[boot] " : "", threads);</span> |
| <span id="L121"><span class="lineNum"> 121</span> : : </span> |
| <span id="L122"><span class="lineNum"> 122</span> :<span class="tlaGNC"> 6 : timebase = HDIF_get_idata(pcia, SPPCIA_IDATA_TIMEBASE, &size);</span></span> |
| <span id="L123"><span class="lineNum"> 123</span> :<span class="tlaGNC"> 6 : if (!timebase || size < sizeof(*timebase)) {</span></span> |
| <span id="L124"><span class="lineNum"> 124</span> :<span class="tlaUNC tlaBgUNC"> 0 : prerror("CORE[%i]: bad timebase size %u @ %p\n",</span></span> |
| <span id="L125"><span class="lineNum"> 125</span> : : pcia_index(pcia), size, timebase);</span> |
| <span id="L126"><span class="lineNum"> 126</span> :<span class="tlaUNC"> 0 : return NULL;</span></span> |
| <span id="L127"><span class="lineNum"> 127</span> : : }</span> |
| <span id="L128"><span class="lineNum"> 128</span> : : </span> |
| <span id="L129"><span class="lineNum"> 129</span> :<span class="tlaGNC tlaBgGNC"> 6 : cache = HDIF_get_idata(pcia, SPPCIA_IDATA_CPU_CACHE, &size);</span></span> |
| <span id="L130"><span class="lineNum"> 130</span> :<span class="tlaGNC"> 6 : if (!cache || size < sizeof(*cache)) {</span></span> |
| <span id="L131"><span class="lineNum"> 131</span> :<span class="tlaUNC tlaBgUNC"> 0 : prerror("CORE[%i]: bad cache size %u @ %p\n",</span></span> |
| <span id="L132"><span class="lineNum"> 132</span> : : pcia_index(pcia), size, cache);</span> |
| <span id="L133"><span class="lineNum"> 133</span> :<span class="tlaUNC"> 0 : return NULL;</span></span> |
| <span id="L134"><span class="lineNum"> 134</span> : : }</span> |
| <span id="L135"><span class="lineNum"> 135</span> : : </span> |
| <span id="L136"><span class="lineNum"> 136</span> :<span class="tlaGNC tlaBgGNC"> 6 : cpu = add_core_common(cpus, cache, timebase,</span></span> |
| <span id="L137"><span class="lineNum"> 137</span> :<span class="tlaGNC"> 6 : be32_to_cpu(t->pir), okay);</span></span> |
| <span id="L138"><span class="lineNum"> 138</span> : : </span> |
| <span id="L139"><span class="lineNum"> 139</span> : : /* Core attributes */</span> |
| <span id="L140"><span class="lineNum"> 140</span> :<span class="tlaGNC"> 6 : attr = HDIF_get_idata(pcia, SPPCIA_IDATA_CPU_ATTR, &size);</span></span> |
| <span id="L141"><span class="lineNum"> 141</span> :<span class="tlaGNC"> 6 : if (attr)</span></span> |
| <span id="L142"><span class="lineNum"> 142</span> :<span class="tlaGNC"> 6 : add_core_attr(cpu, be32_to_cpu(attr->attr));</span></span> |
| <span id="L143"><span class="lineNum"> 143</span> : : </span> |
| <span id="L144"><span class="lineNum"> 144</span> : : /* Add cache info */</span> |
| <span id="L145"><span class="lineNum"> 145</span> :<span class="tlaGNC"> 6 : l2_phandle = add_core_cache_info(cpus, cache,</span></span> |
| <span id="L146"><span class="lineNum"> 146</span> :<span class="tlaGNC"> 6 : be32_to_cpu(t->pir), okay);</span></span> |
| <span id="L147"><span class="lineNum"> 147</span> :<span class="tlaGNC"> 6 : dt_add_property_cells(cpu, "l2-cache", l2_phandle);</span></span> |
| <span id="L148"><span class="lineNum"> 148</span> : : </span> |
| <span id="L149"><span class="lineNum"> 149</span> :<span class="tlaGNC"> 6 : if (proc_gen == proc_gen_p8)</span></span> |
| <span id="L150"><span class="lineNum"> 150</span> :<span class="tlaGNC"> 6 : icp_compat = "IBM,power8-icp";</span></span> |
| <span id="L151"><span class="lineNum"> 151</span> : : </span> |
| <span id="L152"><span class="lineNum"> 152</span> : : /* Get HW Chip ID */</span> |
| <span id="L153"><span class="lineNum"> 153</span> :<span class="tlaGNC"> 6 : chip_id = pcid_to_chip_id(be32_to_cpu(id->proc_chip_id));</span></span> |
| <span id="L154"><span class="lineNum"> 154</span> : : </span> |
| <span id="L155"><span class="lineNum"> 155</span> :<span class="tlaGNC"> 6 : dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(t->pir));</span></span> |
| <span id="L156"><span class="lineNum"> 156</span> :<span class="tlaGNC"> 6 : dt_add_property_cells(cpu, "ibm,chip-id", chip_id);</span></span> |
| <span id="L157"><span class="lineNum"> 157</span> : : </span> |
| <span id="L158"><span class="lineNum"> 158</span> : : /* Build ibm,ppc-interrupt-server#s with all threads */</span> |
| <span id="L159"><span class="lineNum"> 159</span> :<span class="tlaGNC"> 54 : for (i = 0; i < threads; i++) {</span></span> |
| <span id="L160"><span class="lineNum"> 160</span> :<span class="tlaGNC"> 48 : t = find_tada(pcia, i);</span></span> |
| <span id="L161"><span class="lineNum"> 161</span> :<span class="tlaGNC"> 48 : if (!t) {</span></span> |
| <span id="L162"><span class="lineNum"> 162</span> :<span class="tlaUNC tlaBgUNC"> 0 : threads = i;</span></span> |
| <span id="L163"><span class="lineNum"> 163</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L164"><span class="lineNum"> 164</span> : : }</span> |
| <span id="L165"><span class="lineNum"> 165</span> : : </span> |
| <span id="L166"><span class="lineNum"> 166</span> :<span class="tlaGNC tlaBgGNC"> 48 : iserv[i] = t->pir;</span></span> |
| <span id="L167"><span class="lineNum"> 167</span> : : }</span> |
| <span id="L168"><span class="lineNum"> 168</span> : : </span> |
| <span id="L169"><span class="lineNum"> 169</span> :<span class="tlaGNC"> 6 : dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads);</span></span> |
| <span id="L170"><span class="lineNum"> 170</span> : : </span> |
| <span id="L171"><span class="lineNum"> 171</span> : : /* Add the ICP node for this CPU for P8 */</span> |
| <span id="L172"><span class="lineNum"> 172</span> :<span class="tlaGNC"> 6 : if (proc_gen == proc_gen_p8)</span></span> |
| <span id="L173"><span class="lineNum"> 173</span> :<span class="tlaGNC"> 6 : add_xics_icp(pcia, threads, icp_compat);</span></span> |
| <span id="L174"><span class="lineNum"> 174</span> : : </span> |
| <span id="L175"><span class="lineNum"> 175</span> :<span class="tlaGNC"> 6 : return cpu;</span></span> |
| <span id="L176"><span class="lineNum"> 176</span> : : }</span> |
| <span id="L177"><span class="lineNum"> 177</span> : : </span> |
| <span id="L178"><span class="lineNum"> 178</span> :<span class="tlaGNC"> 1 : bool pcia_parse(void)</span></span> |
| <span id="L179"><span class="lineNum"> 179</span> : : {</span> |
| <span id="L180"><span class="lineNum"> 180</span> : : const void *pcia;</span> |
| <span id="L181"><span class="lineNum"> 181</span> : : struct dt_node *cpus;</span> |
| <span id="L182"><span class="lineNum"> 182</span> : : </span> |
| <span id="L183"><span class="lineNum"> 183</span> :<span class="tlaGNC"> 1 : pcia = get_hdif(&spiras->ntuples.pcia, SPPCIA_HDIF_SIG);</span></span> |
| <span id="L184"><span class="lineNum"> 184</span> :<span class="tlaGNC"> 1 : if (!pcia)</span></span> |
| <span id="L185"><span class="lineNum"> 185</span> :<span class="tlaUNC tlaBgUNC"> 0 : return false;</span></span> |
| <span id="L186"><span class="lineNum"> 186</span> : : </span> |
| <span id="L187"><span class="lineNum"> 187</span> :<span class="tlaGNC tlaBgGNC"> 1 : prlog(PR_INFO, "Got PCIA !\n");</span></span> |
| <span id="L188"><span class="lineNum"> 188</span> : : </span> |
| <span id="L189"><span class="lineNum"> 189</span> :<span class="tlaGNC"> 1 : cpus = dt_new(dt_root, "cpus");</span></span> |
| <span id="L190"><span class="lineNum"> 190</span> :<span class="tlaGNC"> 1 : dt_add_property_cells(cpus, "#address-cells", 1);</span></span> |
| <span id="L191"><span class="lineNum"> 191</span> :<span class="tlaGNC"> 1 : dt_add_property_cells(cpus, "#size-cells", 0);</span></span> |
| <span id="L192"><span class="lineNum"> 192</span> : : </span> |
| <span id="L193"><span class="lineNum"> 193</span> :<span class="tlaGNC"> 7 : for_each_pcia(spiras, pcia) {</span></span> |
| <span id="L194"><span class="lineNum"> 194</span> : : const struct sppcia_core_unique *id;</span> |
| <span id="L195"><span class="lineNum"> 195</span> : : u32 size, ve_flags;</span> |
| <span id="L196"><span class="lineNum"> 196</span> : : bool okay;</span> |
| <span id="L197"><span class="lineNum"> 197</span> : : </span> |
| <span id="L198"><span class="lineNum"> 198</span> :<span class="tlaGNC"> 6 : id = HDIF_get_idata(pcia, SPPCIA_IDATA_CORE_UNIQUE, &size);</span></span> |
| <span id="L199"><span class="lineNum"> 199</span> :<span class="tlaGNC"> 6 : if (!id || size < sizeof(*id)) {</span></span> |
| <span id="L200"><span class="lineNum"> 200</span> :<span class="tlaUNC tlaBgUNC"> 0 : prerror("CORE[%i]: bad id size %u @ %p\n",</span></span> |
| <span id="L201"><span class="lineNum"> 201</span> : : pcia_index(pcia), size, id);</span> |
| <span id="L202"><span class="lineNum"> 202</span> :<span class="tlaUNC"> 0 : return false;</span></span> |
| <span id="L203"><span class="lineNum"> 203</span> : : }</span> |
| <span id="L204"><span class="lineNum"> 204</span> :<span class="tlaGNC tlaBgGNC"> 6 : ve_flags = be32_to_cpu(id->verif_exist_flags);</span></span> |
| <span id="L205"><span class="lineNum"> 205</span> : : </span> |
| <span id="L206"><span class="lineNum"> 206</span> :<span class="tlaGNC"> 6 : switch ((ve_flags & CPU_ID_VERIFY_MASK)</span></span> |
| <span id="L207"><span class="lineNum"> 207</span> :<span class="tlaGNC"> 6 : >> CPU_ID_VERIFY_SHIFT) {</span></span> |
| <span id="L208"><span class="lineNum"> 208</span> :<span class="tlaGNC"> 6 : case CPU_ID_VERIFY_USABLE_NO_FAILURES:</span></span> |
| <span id="L209"><span class="lineNum"> 209</span> : : case CPU_ID_VERIFY_USABLE_FAILURES:</span> |
| <span id="L210"><span class="lineNum"> 210</span> :<span class="tlaGNC"> 6 : okay = true;</span></span> |
| <span id="L211"><span class="lineNum"> 211</span> :<span class="tlaGNC"> 6 : break;</span></span> |
| <span id="L212"><span class="lineNum"> 212</span> :<span class="tlaUNC tlaBgUNC"> 0 : default:</span></span> |
| <span id="L213"><span class="lineNum"> 213</span> :<span class="tlaUNC"> 0 : okay = false;</span></span> |
| <span id="L214"><span class="lineNum"> 214</span> : : }</span> |
| <span id="L215"><span class="lineNum"> 215</span> : : </span> |
| <span id="L216"><span class="lineNum"> 216</span> :<span class="tlaGNC tlaBgGNC"> 6 : prlog(okay ? PR_INFO : PR_WARNING,</span></span> |
| <span id="L217"><span class="lineNum"> 217</span> : : "CORE[%i]: HW_PROC_ID=%i PROC_CHIP_ID=%i EC=0x%x %s\n",</span> |
| <span id="L218"><span class="lineNum"> 218</span> : : pcia_index(pcia), be32_to_cpu(id->hw_proc_id),</span> |
| <span id="L219"><span class="lineNum"> 219</span> : : be32_to_cpu(id->proc_chip_id),</span> |
| <span id="L220"><span class="lineNum"> 220</span> : : be32_to_cpu(id->chip_ec_level),</span> |
| <span id="L221"><span class="lineNum"> 221</span> : : okay ? "OK" : "UNAVAILABLE");</span> |
| <span id="L222"><span class="lineNum"> 222</span> : : </span> |
| <span id="L223"><span class="lineNum"> 223</span> :<span class="tlaGNC"> 6 : if (!add_core_node(cpus, pcia, id, okay))</span></span> |
| <span id="L224"><span class="lineNum"> 224</span> :<span class="tlaUNC tlaBgUNC"> 0 : break;</span></span> |
| <span id="L225"><span class="lineNum"> 225</span> : : }</span> |
| <span id="L226"><span class="lineNum"> 226</span> :<span class="tlaGNC tlaBgGNC"> 1 : return true;</span></span> |
| <span id="L227"><span class="lineNum"> 227</span> : : }</span> |
| </pre> |
| </td> |
| </tr> |
| </table> |
| <br> |
| |
| <table width="100%" border=0 cellspacing=0 cellpadding=0> |
| <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr> |
| <tr><td class="versionInfo">Generated by: <a href="https://github.com//linux-test-project/lcov" target="_parent">LCOV version 2.0-1</a></td></tr> |
| </table> |
| <br> |
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| </body> |
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