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| <td class="headerCovTableEntryMed">78.1 %</td> |
| <td class="headerCovTableEntry">151</td> |
| <td class="headerCovTableEntry">118</td> |
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| <td class="headerValue">2025-06-27 16:54:26</td> |
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| <td class="headerCovTableEntryHi">100.0 %</td> |
| <td class="headerCovTableEntry">4</td> |
| <td class="headerCovTableEntry">4</td> |
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| <pre class="sourceHeading"> Branch data Line data Source code</pre> |
| <pre class="source"> |
| <span id="L1"><span class="lineNum"> 1</span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</span> |
| <span id="L2"><span class="lineNum"> 2</span> : : /*</span> |
| <span id="L3"><span class="lineNum"> 3</span> : : * This file deals with setup of /cpus/ibm,powerpc-cpu-features dt</span> |
| <span id="L4"><span class="lineNum"> 4</span> : : *</span> |
| <span id="L5"><span class="lineNum"> 5</span> : : * Copyright 2017-2019 IBM Corp.</span> |
| <span id="L6"><span class="lineNum"> 6</span> : : */</span> |
| <span id="L7"><span class="lineNum"> 7</span> : : </span> |
| <span id="L8"><span class="lineNum"> 8</span> : : #include <skiboot.h></span> |
| <span id="L9"><span class="lineNum"> 9</span> : : #include <cpu.h></span> |
| <span id="L10"><span class="lineNum"> 10</span> : : #include <processor.h></span> |
| <span id="L11"><span class="lineNum"> 11</span> : : #include <ccan/str/str.h></span> |
| <span id="L12"><span class="lineNum"> 12</span> : : #include <device.h></span> |
| <span id="L13"><span class="lineNum"> 13</span> : : </span> |
| <span id="L14"><span class="lineNum"> 14</span> : : #ifdef DEBUG</span> |
| <span id="L15"><span class="lineNum"> 15</span> : : #define DBG(fmt, a...) prlog(PR_DEBUG, "CPUFT: " fmt, ##a)</span> |
| <span id="L16"><span class="lineNum"> 16</span> : : #else</span> |
| <span id="L17"><span class="lineNum"> 17</span> : : #define DBG(fmt, a...)</span> |
| <span id="L18"><span class="lineNum"> 18</span> : : #endif</span> |
| <span id="L19"><span class="lineNum"> 19</span> : : </span> |
| <span id="L20"><span class="lineNum"> 20</span> : : /* Device-tree visible constants follow */</span> |
| <span id="L21"><span class="lineNum"> 21</span> : : #define ISA_V2_07B 2070</span> |
| <span id="L22"><span class="lineNum"> 22</span> : : #define ISA_V3_0B 3000</span> |
| <span id="L23"><span class="lineNum"> 23</span> : : #define ISA_V3_1 3100</span> |
| <span id="L24"><span class="lineNum"> 24</span> : : </span> |
| <span id="L25"><span class="lineNum"> 25</span> : : #define USABLE_PR (1U << 0)</span> |
| <span id="L26"><span class="lineNum"> 26</span> : : #define USABLE_OS (1U << 1)</span> |
| <span id="L27"><span class="lineNum"> 27</span> : : #define USABLE_HV (1U << 2)</span> |
| <span id="L28"><span class="lineNum"> 28</span> : : </span> |
| <span id="L29"><span class="lineNum"> 29</span> : : #define HV_SUPPORT_HFSCR (1U << 0)</span> |
| <span id="L30"><span class="lineNum"> 30</span> : : #define OS_SUPPORT_FSCR (1U << 0)</span> |
| <span id="L31"><span class="lineNum"> 31</span> : : </span> |
| <span id="L32"><span class="lineNum"> 32</span> : : /* Following are definitions for the match tables, not the DT binding itself */</span> |
| <span id="L33"><span class="lineNum"> 33</span> : : #define ISA_BASE 0</span> |
| <span id="L34"><span class="lineNum"> 34</span> : : </span> |
| <span id="L35"><span class="lineNum"> 35</span> : : #define HV_NONE 0</span> |
| <span id="L36"><span class="lineNum"> 36</span> : : #define HV_CUSTOM 1</span> |
| <span id="L37"><span class="lineNum"> 37</span> : : #define HV_HFSCR 2</span> |
| <span id="L38"><span class="lineNum"> 38</span> : : </span> |
| <span id="L39"><span class="lineNum"> 39</span> : : #define OS_NONE 0</span> |
| <span id="L40"><span class="lineNum"> 40</span> : : #define OS_CUSTOM 1</span> |
| <span id="L41"><span class="lineNum"> 41</span> : : #define OS_FSCR 2</span> |
| <span id="L42"><span class="lineNum"> 42</span> : : </span> |
| <span id="L43"><span class="lineNum"> 43</span> : : /* CPU bitmasks for match table */</span> |
| <span id="L44"><span class="lineNum"> 44</span> : : #define CPU_P8_DD1 (1U << 0)</span> |
| <span id="L45"><span class="lineNum"> 45</span> : : #define CPU_P8_DD2 (1U << 1)</span> |
| <span id="L46"><span class="lineNum"> 46</span> : : #define CPU_P9_DD1 (1U << 2)</span> |
| <span id="L47"><span class="lineNum"> 47</span> : : #define CPU_P9_DD2_0_1 (1U << 3) // 2.01 or 2.1</span> |
| <span id="L48"><span class="lineNum"> 48</span> : : #define CPU_P9P (1U << 4)</span> |
| <span id="L49"><span class="lineNum"> 49</span> : : #define CPU_P9_DD2_2 (1U << 5)</span> |
| <span id="L50"><span class="lineNum"> 50</span> : : #define CPU_P9_DD2_3 (1U << 6)</span> |
| <span id="L51"><span class="lineNum"> 51</span> : : #define CPU_P10 (1U << 7)</span> |
| <span id="L52"><span class="lineNum"> 52</span> : : #define CPU_P11 (1U << 8)</span> |
| <span id="L53"><span class="lineNum"> 53</span> : : </span> |
| <span id="L54"><span class="lineNum"> 54</span> : : #define CPU_P9_DD2 (CPU_P9_DD2_0_1|CPU_P9_DD2_2|CPU_P9_DD2_3|CPU_P9P)</span> |
| <span id="L55"><span class="lineNum"> 55</span> : : </span> |
| <span id="L56"><span class="lineNum"> 56</span> : : #define CPU_P8 (CPU_P8_DD1|CPU_P8_DD2)</span> |
| <span id="L57"><span class="lineNum"> 57</span> : : #define CPU_P9 (CPU_P9_DD1|CPU_P9_DD2|CPU_P9P)</span> |
| <span id="L58"><span class="lineNum"> 58</span> : : #define CPU_ALL (CPU_P8|CPU_P9|CPU_P10|CPU_P11)</span> |
| <span id="L59"><span class="lineNum"> 59</span> : : </span> |
| <span id="L60"><span class="lineNum"> 60</span> : : struct cpu_feature {</span> |
| <span id="L61"><span class="lineNum"> 61</span> : : const char *name;</span> |
| <span id="L62"><span class="lineNum"> 62</span> : : uint32_t cpus_supported;</span> |
| <span id="L63"><span class="lineNum"> 63</span> : : uint32_t isa;</span> |
| <span id="L64"><span class="lineNum"> 64</span> : : uint32_t usable_privilege;</span> |
| <span id="L65"><span class="lineNum"> 65</span> : : uint32_t hv_support;</span> |
| <span id="L66"><span class="lineNum"> 66</span> : : uint32_t os_support;</span> |
| <span id="L67"><span class="lineNum"> 67</span> : : uint32_t hfscr_bit_nr;</span> |
| <span id="L68"><span class="lineNum"> 68</span> : : uint32_t fscr_bit_nr;</span> |
| <span id="L69"><span class="lineNum"> 69</span> : : uint32_t hwcap_bit_nr;</span> |
| <span id="L70"><span class="lineNum"> 70</span> : : const char *dependencies_names; /* space-delimited names */</span> |
| <span id="L71"><span class="lineNum"> 71</span> : : };</span> |
| <span id="L72"><span class="lineNum"> 72</span> : : </span> |
| <span id="L73"><span class="lineNum"> 73</span> : : /*</span> |
| <span id="L74"><span class="lineNum"> 74</span> : : * The base (or NULL) cpu feature set is the CPU features available</span> |
| <span id="L75"><span class="lineNum"> 75</span> : : * when no child nodes of the /cpus/ibm,powerpc-cpu-features node exist. The</span> |
| <span id="L76"><span class="lineNum"> 76</span> : : * base feature set is POWER8 (ISAv2.07B), less features that are listed</span> |
| <span id="L77"><span class="lineNum"> 77</span> : : * explicitly.</span> |
| <span id="L78"><span class="lineNum"> 78</span> : : *</span> |
| <span id="L79"><span class="lineNum"> 79</span> : : * XXX: currently, the feature dependencies are not necessarily captured</span> |
| <span id="L80"><span class="lineNum"> 80</span> : : * exactly or completely. This is somewhat acceptable because all</span> |
| <span id="L81"><span class="lineNum"> 81</span> : : * implementations must be aware of all these features.</span> |
| <span id="L82"><span class="lineNum"> 82</span> : : */</span> |
| <span id="L83"><span class="lineNum"> 83</span> : : static const struct cpu_feature cpu_features_table[] = {</span> |
| <span id="L84"><span class="lineNum"> 84</span> : : /*</span> |
| <span id="L85"><span class="lineNum"> 85</span> : : * Big endian as in ISAv2.07B, MSR_LE=0</span> |
| <span id="L86"><span class="lineNum"> 86</span> : : */</span> |
| <span id="L87"><span class="lineNum"> 87</span> : : { "big-endian",</span> |
| <span id="L88"><span class="lineNum"> 88</span> : : CPU_ALL,</span> |
| <span id="L89"><span class="lineNum"> 89</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L90"><span class="lineNum"> 90</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L91"><span class="lineNum"> 91</span> : : -1, -1, -1,</span> |
| <span id="L92"><span class="lineNum"> 92</span> : : NULL, },</span> |
| <span id="L93"><span class="lineNum"> 93</span> : : </span> |
| <span id="L94"><span class="lineNum"> 94</span> : : /*</span> |
| <span id="L95"><span class="lineNum"> 95</span> : : * Little endian as in ISAv2.07B, MSR_LE=1.</span> |
| <span id="L96"><span class="lineNum"> 96</span> : : *</span> |
| <span id="L97"><span class="lineNum"> 97</span> : : * When both big and little endian are defined, there is an LPCR ILE</span> |
| <span id="L98"><span class="lineNum"> 98</span> : : * bit and implementation specific way to switch HILE mode, MSR_SLE,</span> |
| <span id="L99"><span class="lineNum"> 99</span> : : * etc.</span> |
| <span id="L100"><span class="lineNum"> 100</span> : : */</span> |
| <span id="L101"><span class="lineNum"> 101</span> : : { "little-endian",</span> |
| <span id="L102"><span class="lineNum"> 102</span> : : CPU_ALL,</span> |
| <span id="L103"><span class="lineNum"> 103</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L104"><span class="lineNum"> 104</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L105"><span class="lineNum"> 105</span> : : -1, -1, -1,</span> |
| <span id="L106"><span class="lineNum"> 106</span> : : NULL, },</span> |
| <span id="L107"><span class="lineNum"> 107</span> : : </span> |
| <span id="L108"><span class="lineNum"> 108</span> : : /*</span> |
| <span id="L109"><span class="lineNum"> 109</span> : : * MSR_HV=1 mode as in ISAv2.07B (i.e., hypervisor privileged</span> |
| <span id="L110"><span class="lineNum"> 110</span> : : * instructions and registers).</span> |
| <span id="L111"><span class="lineNum"> 111</span> : : */</span> |
| <span id="L112"><span class="lineNum"> 112</span> : : { "hypervisor",</span> |
| <span id="L113"><span class="lineNum"> 113</span> : : CPU_ALL,</span> |
| <span id="L114"><span class="lineNum"> 114</span> : : ISA_BASE, USABLE_HV,</span> |
| <span id="L115"><span class="lineNum"> 115</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L116"><span class="lineNum"> 116</span> : : -1, -1, -1,</span> |
| <span id="L117"><span class="lineNum"> 117</span> : : NULL, },</span> |
| <span id="L118"><span class="lineNum"> 118</span> : : </span> |
| <span id="L119"><span class="lineNum"> 119</span> : : /*</span> |
| <span id="L120"><span class="lineNum"> 120</span> : : * ISAv2.07B interrupt vectors, registers, and control registers</span> |
| <span id="L121"><span class="lineNum"> 121</span> : : * (e.g., AIL, ILE, HV, etc LPCR bits).</span> |
| <span id="L122"><span class="lineNum"> 122</span> : : *</span> |
| <span id="L123"><span class="lineNum"> 123</span> : : * This does not necessarily specify all possible interrupt types.</span> |
| <span id="L124"><span class="lineNum"> 124</span> : : * floating-point, for example requires some ways to handle floating</span> |
| <span id="L125"><span class="lineNum"> 125</span> : : * point exceptions, but the low level details of interrupt handler</span> |
| <span id="L126"><span class="lineNum"> 126</span> : : * is not a dependency there. There will always be *some* interrupt</span> |
| <span id="L127"><span class="lineNum"> 127</span> : : * handler, (and some way to provide memory magagement, etc.).</span> |
| <span id="L128"><span class="lineNum"> 128</span> : : */</span> |
| <span id="L129"><span class="lineNum"> 129</span> : : { "interrupt-facilities",</span> |
| <span id="L130"><span class="lineNum"> 130</span> : : CPU_ALL,</span> |
| <span id="L131"><span class="lineNum"> 131</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L132"><span class="lineNum"> 132</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L133"><span class="lineNum"> 133</span> : : -1, -1, -1,</span> |
| <span id="L134"><span class="lineNum"> 134</span> : : NULL, },</span> |
| <span id="L135"><span class="lineNum"> 135</span> : : </span> |
| <span id="L136"><span class="lineNum"> 136</span> : : { "smt",</span> |
| <span id="L137"><span class="lineNum"> 137</span> : : CPU_ALL,</span> |
| <span id="L138"><span class="lineNum"> 138</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L139"><span class="lineNum"> 139</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L140"><span class="lineNum"> 140</span> : : -1, -1, 14,</span> |
| <span id="L141"><span class="lineNum"> 141</span> : : NULL, },</span> |
| <span id="L142"><span class="lineNum"> 142</span> : : </span> |
| <span id="L143"><span class="lineNum"> 143</span> : : /*</span> |
| <span id="L144"><span class="lineNum"> 144</span> : : * ISAv2.07B Program Priority Registers (PPR)</span> |
| <span id="L145"><span class="lineNum"> 145</span> : : * PPR and associated control registers (e.g. RPR, PSPB),</span> |
| <span id="L146"><span class="lineNum"> 146</span> : : * priority "or" instructions, etc.</span> |
| <span id="L147"><span class="lineNum"> 147</span> : : */</span> |
| <span id="L148"><span class="lineNum"> 148</span> : : { "program-priority-register",</span> |
| <span id="L149"><span class="lineNum"> 149</span> : : CPU_ALL,</span> |
| <span id="L150"><span class="lineNum"> 150</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L151"><span class="lineNum"> 151</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L152"><span class="lineNum"> 152</span> : : -1, -1, -1,</span> |
| <span id="L153"><span class="lineNum"> 153</span> : : NULL, },</span> |
| <span id="L154"><span class="lineNum"> 154</span> : : </span> |
| <span id="L155"><span class="lineNum"> 155</span> : : /*</span> |
| <span id="L156"><span class="lineNum"> 156</span> : : * ISAv2.07B Book3S Chapter 5.7.9.1. Virtual Page Class Key Protecion</span> |
| <span id="L157"><span class="lineNum"> 157</span> : : * AMR, IAMR, AMOR, UAMOR, etc registers and MMU key bits.</span> |
| <span id="L158"><span class="lineNum"> 158</span> : : */</span> |
| <span id="L159"><span class="lineNum"> 159</span> : : { "virtual-page-class-key-protection",</span> |
| <span id="L160"><span class="lineNum"> 160</span> : : CPU_ALL,</span> |
| <span id="L161"><span class="lineNum"> 161</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L162"><span class="lineNum"> 162</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L163"><span class="lineNum"> 163</span> : : -1, -1, -1,</span> |
| <span id="L164"><span class="lineNum"> 164</span> : : NULL, },</span> |
| <span id="L165"><span class="lineNum"> 165</span> : : </span> |
| <span id="L166"><span class="lineNum"> 166</span> : : /*</span> |
| <span id="L167"><span class="lineNum"> 167</span> : : * ISAv2.07B SAO storage control attribute</span> |
| <span id="L168"><span class="lineNum"> 168</span> : : */</span> |
| <span id="L169"><span class="lineNum"> 169</span> : : { "strong-access-ordering",</span> |
| <span id="L170"><span class="lineNum"> 170</span> : : CPU_ALL & ~CPU_P9_DD1,</span> |
| <span id="L171"><span class="lineNum"> 171</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L172"><span class="lineNum"> 172</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L173"><span class="lineNum"> 173</span> : : -1, -1, -1,</span> |
| <span id="L174"><span class="lineNum"> 174</span> : : NULL, },</span> |
| <span id="L175"><span class="lineNum"> 175</span> : : </span> |
| <span id="L176"><span class="lineNum"> 176</span> : : /*</span> |
| <span id="L177"><span class="lineNum"> 177</span> : : * ISAv2.07B no-execute storage control attribute</span> |
| <span id="L178"><span class="lineNum"> 178</span> : : */</span> |
| <span id="L179"><span class="lineNum"> 179</span> : : { "no-execute",</span> |
| <span id="L180"><span class="lineNum"> 180</span> : : CPU_ALL,</span> |
| <span id="L181"><span class="lineNum"> 181</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L182"><span class="lineNum"> 182</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L183"><span class="lineNum"> 183</span> : : -1, -1, -1,</span> |
| <span id="L184"><span class="lineNum"> 184</span> : : NULL, },</span> |
| <span id="L185"><span class="lineNum"> 185</span> : : </span> |
| <span id="L186"><span class="lineNum"> 186</span> : : /*</span> |
| <span id="L187"><span class="lineNum"> 187</span> : : * Cache inhibited attribute supported on large pages.</span> |
| <span id="L188"><span class="lineNum"> 188</span> : : */</span> |
| <span id="L189"><span class="lineNum"> 189</span> : : { "cache-inhibited-large-page",</span> |
| <span id="L190"><span class="lineNum"> 190</span> : : CPU_ALL,</span> |
| <span id="L191"><span class="lineNum"> 191</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L192"><span class="lineNum"> 192</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L193"><span class="lineNum"> 193</span> : : -1, -1, -1,</span> |
| <span id="L194"><span class="lineNum"> 194</span> : : NULL, },</span> |
| <span id="L195"><span class="lineNum"> 195</span> : : </span> |
| <span id="L196"><span class="lineNum"> 196</span> : : /*</span> |
| <span id="L197"><span class="lineNum"> 197</span> : : * ISAv2.07B Book3S Chapter 8. Debug Facilities</span> |
| <span id="L198"><span class="lineNum"> 198</span> : : * CIEA, CIABR, DEAW, MEte, trace interrupt, etc.</span> |
| <span id="L199"><span class="lineNum"> 199</span> : : * Except CFAR, branch tracing.</span> |
| <span id="L200"><span class="lineNum"> 200</span> : : */</span> |
| <span id="L201"><span class="lineNum"> 201</span> : : { "debug-facilities",</span> |
| <span id="L202"><span class="lineNum"> 202</span> : : CPU_ALL,</span> |
| <span id="L203"><span class="lineNum"> 203</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L204"><span class="lineNum"> 204</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L205"><span class="lineNum"> 205</span> : : -1, -1, -1,</span> |
| <span id="L206"><span class="lineNum"> 206</span> : : NULL, },</span> |
| <span id="L207"><span class="lineNum"> 207</span> : : </span> |
| <span id="L208"><span class="lineNum"> 208</span> : : /*</span> |
| <span id="L209"><span class="lineNum"> 209</span> : : * DAWR1, DAWRX1 etc.</span> |
| <span id="L210"><span class="lineNum"> 210</span> : : */</span> |
| <span id="L211"><span class="lineNum"> 211</span> : : { "debug-facilities-v31",</span> |
| <span id="L212"><span class="lineNum"> 212</span> : : CPU_P10|CPU_P11,</span> |
| <span id="L213"><span class="lineNum"> 213</span> : : ISA_V3_1, USABLE_HV|USABLE_OS,</span> |
| <span id="L214"><span class="lineNum"> 214</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L215"><span class="lineNum"> 215</span> : : -1, -1, -1,</span> |
| <span id="L216"><span class="lineNum"> 216</span> : : NULL, },</span> |
| <span id="L217"><span class="lineNum"> 217</span> : : </span> |
| <span id="L218"><span class="lineNum"> 218</span> : : /*</span> |
| <span id="L219"><span class="lineNum"> 219</span> : : * ISAv2.07B CFAR</span> |
| <span id="L220"><span class="lineNum"> 220</span> : : */</span> |
| <span id="L221"><span class="lineNum"> 221</span> : : { "come-from-address-register",</span> |
| <span id="L222"><span class="lineNum"> 222</span> : : CPU_ALL,</span> |
| <span id="L223"><span class="lineNum"> 223</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L224"><span class="lineNum"> 224</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L225"><span class="lineNum"> 225</span> : : -1, -1, -1,</span> |
| <span id="L226"><span class="lineNum"> 226</span> : : "debug-facilities", },</span> |
| <span id="L227"><span class="lineNum"> 227</span> : : </span> |
| <span id="L228"><span class="lineNum"> 228</span> : : /*</span> |
| <span id="L229"><span class="lineNum"> 229</span> : : * ISAv2.07B Branch tracing (optional in ISA)</span> |
| <span id="L230"><span class="lineNum"> 230</span> : : */</span> |
| <span id="L231"><span class="lineNum"> 231</span> : : { "branch-tracing",</span> |
| <span id="L232"><span class="lineNum"> 232</span> : : CPU_ALL,</span> |
| <span id="L233"><span class="lineNum"> 233</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L234"><span class="lineNum"> 234</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L235"><span class="lineNum"> 235</span> : : -1, -1, -1,</span> |
| <span id="L236"><span class="lineNum"> 236</span> : : "debug-facilities", },</span> |
| <span id="L237"><span class="lineNum"> 237</span> : : </span> |
| <span id="L238"><span class="lineNum"> 238</span> : : /*</span> |
| <span id="L239"><span class="lineNum"> 239</span> : : * ISAv2.07B Floating-point Facility</span> |
| <span id="L240"><span class="lineNum"> 240</span> : : */</span> |
| <span id="L241"><span class="lineNum"> 241</span> : : { "floating-point",</span> |
| <span id="L242"><span class="lineNum"> 242</span> : : CPU_ALL,</span> |
| <span id="L243"><span class="lineNum"> 243</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L244"><span class="lineNum"> 244</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L245"><span class="lineNum"> 245</span> : : PPC_BITLSHIFT(63), -1, 27,</span> |
| <span id="L246"><span class="lineNum"> 246</span> : : NULL, },</span> |
| <span id="L247"><span class="lineNum"> 247</span> : : </span> |
| <span id="L248"><span class="lineNum"> 248</span> : : /*</span> |
| <span id="L249"><span class="lineNum"> 249</span> : : * ISAv2.07B Vector Facility (VMX)</span> |
| <span id="L250"><span class="lineNum"> 250</span> : : */</span> |
| <span id="L251"><span class="lineNum"> 251</span> : : { "vector",</span> |
| <span id="L252"><span class="lineNum"> 252</span> : : CPU_ALL,</span> |
| <span id="L253"><span class="lineNum"> 253</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L254"><span class="lineNum"> 254</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L255"><span class="lineNum"> 255</span> : : PPC_BITLSHIFT(62), -1, 28,</span> |
| <span id="L256"><span class="lineNum"> 256</span> : : "floating-point", },</span> |
| <span id="L257"><span class="lineNum"> 257</span> : : </span> |
| <span id="L258"><span class="lineNum"> 258</span> : : /*</span> |
| <span id="L259"><span class="lineNum"> 259</span> : : * ISAv2.07B Vector-scalar Facility (VSX)</span> |
| <span id="L260"><span class="lineNum"> 260</span> : : */</span> |
| <span id="L261"><span class="lineNum"> 261</span> : : { "vector-scalar",</span> |
| <span id="L262"><span class="lineNum"> 262</span> : : CPU_ALL,</span> |
| <span id="L263"><span class="lineNum"> 263</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L264"><span class="lineNum"> 264</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L265"><span class="lineNum"> 265</span> : : -1, -1, 7,</span> |
| <span id="L266"><span class="lineNum"> 266</span> : : "vector", },</span> |
| <span id="L267"><span class="lineNum"> 267</span> : : </span> |
| <span id="L268"><span class="lineNum"> 268</span> : : { "vector-crypto",</span> |
| <span id="L269"><span class="lineNum"> 269</span> : : CPU_ALL,</span> |
| <span id="L270"><span class="lineNum"> 270</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L271"><span class="lineNum"> 271</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L272"><span class="lineNum"> 272</span> : : -1, -1, 57,</span> |
| <span id="L273"><span class="lineNum"> 273</span> : : "vector", },</span> |
| <span id="L274"><span class="lineNum"> 274</span> : : </span> |
| <span id="L275"><span class="lineNum"> 275</span> : : /*</span> |
| <span id="L276"><span class="lineNum"> 276</span> : : * ISAv2.07B Quadword Load and Store instructions</span> |
| <span id="L277"><span class="lineNum"> 277</span> : : * including lqarx/stdqcx. instructions.</span> |
| <span id="L278"><span class="lineNum"> 278</span> : : */</span> |
| <span id="L279"><span class="lineNum"> 279</span> : : { "quadword-load-store",</span> |
| <span id="L280"><span class="lineNum"> 280</span> : : CPU_ALL,</span> |
| <span id="L281"><span class="lineNum"> 281</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L282"><span class="lineNum"> 282</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L283"><span class="lineNum"> 283</span> : : -1, -1, -1,</span> |
| <span id="L284"><span class="lineNum"> 284</span> : : NULL, },</span> |
| <span id="L285"><span class="lineNum"> 285</span> : : </span> |
| <span id="L286"><span class="lineNum"> 286</span> : : /*</span> |
| <span id="L287"><span class="lineNum"> 287</span> : : * ISAv2.07B Binary Coded Decimal (BCD)</span> |
| <span id="L288"><span class="lineNum"> 288</span> : : * BCD fixed point instructions</span> |
| <span id="L289"><span class="lineNum"> 289</span> : : */</span> |
| <span id="L290"><span class="lineNum"> 290</span> : : { "decimal-integer",</span> |
| <span id="L291"><span class="lineNum"> 291</span> : : CPU_ALL,</span> |
| <span id="L292"><span class="lineNum"> 292</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L293"><span class="lineNum"> 293</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L294"><span class="lineNum"> 294</span> : : -1, -1, -1,</span> |
| <span id="L295"><span class="lineNum"> 295</span> : : NULL, },</span> |
| <span id="L296"><span class="lineNum"> 296</span> : : </span> |
| <span id="L297"><span class="lineNum"> 297</span> : : /*</span> |
| <span id="L298"><span class="lineNum"> 298</span> : : * ISAv2.07B Decimal floating-point Facility (DFP)</span> |
| <span id="L299"><span class="lineNum"> 299</span> : : */</span> |
| <span id="L300"><span class="lineNum"> 300</span> : : { "decimal-floating-point",</span> |
| <span id="L301"><span class="lineNum"> 301</span> : : CPU_ALL,</span> |
| <span id="L302"><span class="lineNum"> 302</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L303"><span class="lineNum"> 303</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L304"><span class="lineNum"> 304</span> : : -1, -1, 10,</span> |
| <span id="L305"><span class="lineNum"> 305</span> : : "floating-point", },</span> |
| <span id="L306"><span class="lineNum"> 306</span> : : </span> |
| <span id="L307"><span class="lineNum"> 307</span> : : /*</span> |
| <span id="L308"><span class="lineNum"> 308</span> : : * ISAv2.07B</span> |
| <span id="L309"><span class="lineNum"> 309</span> : : * DSCR, default data prefetch LPCR, etc</span> |
| <span id="L310"><span class="lineNum"> 310</span> : : */</span> |
| <span id="L311"><span class="lineNum"> 311</span> : : { "data-stream-control-register",</span> |
| <span id="L312"><span class="lineNum"> 312</span> : : CPU_ALL,</span> |
| <span id="L313"><span class="lineNum"> 313</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L314"><span class="lineNum"> 314</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L315"><span class="lineNum"> 315</span> : : PPC_BITLSHIFT(61), PPC_BITLSHIFT(61), 61,</span> |
| <span id="L316"><span class="lineNum"> 316</span> : : NULL, },</span> |
| <span id="L317"><span class="lineNum"> 317</span> : : </span> |
| <span id="L318"><span class="lineNum"> 318</span> : : /*</span> |
| <span id="L319"><span class="lineNum"> 319</span> : : * ISAv2.07B Branch History Rolling Buffer (BHRB)</span> |
| <span id="L320"><span class="lineNum"> 320</span> : : */</span> |
| <span id="L321"><span class="lineNum"> 321</span> : : { "branch-history-rolling-buffer",</span> |
| <span id="L322"><span class="lineNum"> 322</span> : : CPU_ALL,</span> |
| <span id="L323"><span class="lineNum"> 323</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L324"><span class="lineNum"> 324</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L325"><span class="lineNum"> 325</span> : : PPC_BITLSHIFT(59), -1, -1,</span> |
| <span id="L326"><span class="lineNum"> 326</span> : : NULL, },</span> |
| <span id="L327"><span class="lineNum"> 327</span> : : </span> |
| <span id="L328"><span class="lineNum"> 328</span> : : /*</span> |
| <span id="L329"><span class="lineNum"> 329</span> : : * ISAv2.07B Transactional Memory Facility (TM or HTM)</span> |
| <span id="L330"><span class="lineNum"> 330</span> : : */</span> |
| <span id="L331"><span class="lineNum"> 331</span> : : { "transactional-memory",</span> |
| <span id="L332"><span class="lineNum"> 332</span> : : CPU_P8, /* P9 support is not enabled yet */</span> |
| <span id="L333"><span class="lineNum"> 333</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L334"><span class="lineNum"> 334</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L335"><span class="lineNum"> 335</span> : : PPC_BITLSHIFT(58), -1, 62,</span> |
| <span id="L336"><span class="lineNum"> 336</span> : : NULL, },</span> |
| <span id="L337"><span class="lineNum"> 337</span> : : </span> |
| <span id="L338"><span class="lineNum"> 338</span> : : /*</span> |
| <span id="L339"><span class="lineNum"> 339</span> : : * ISAv3.0B TM additions</span> |
| <span id="L340"><span class="lineNum"> 340</span> : : * TEXASR bit 17, self-induced vs external footprint overflow</span> |
| <span id="L341"><span class="lineNum"> 341</span> : : */</span> |
| <span id="L342"><span class="lineNum"> 342</span> : : { "transactional-memory-v3",</span> |
| <span id="L343"><span class="lineNum"> 343</span> : : 0,</span> |
| <span id="L344"><span class="lineNum"> 344</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L345"><span class="lineNum"> 345</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L346"><span class="lineNum"> 346</span> : : -1, -1, -1,</span> |
| <span id="L347"><span class="lineNum"> 347</span> : : "transactional-memory", },</span> |
| <span id="L348"><span class="lineNum"> 348</span> : : </span> |
| <span id="L349"><span class="lineNum"> 349</span> : : /*</span> |
| <span id="L350"><span class="lineNum"> 350</span> : : * ISAv2.07B Event-Based Branch Facility (EBB)</span> |
| <span id="L351"><span class="lineNum"> 351</span> : : */</span> |
| <span id="L352"><span class="lineNum"> 352</span> : : { "event-based-branch",</span> |
| <span id="L353"><span class="lineNum"> 353</span> : : CPU_ALL,</span> |
| <span id="L354"><span class="lineNum"> 354</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L355"><span class="lineNum"> 355</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L356"><span class="lineNum"> 356</span> : : PPC_BITLSHIFT(56), PPC_BITLSHIFT(56), 60,</span> |
| <span id="L357"><span class="lineNum"> 357</span> : : NULL, },</span> |
| <span id="L358"><span class="lineNum"> 358</span> : : </span> |
| <span id="L359"><span class="lineNum"> 359</span> : : /*</span> |
| <span id="L360"><span class="lineNum"> 360</span> : : * ISAv2.07B Target Address Register (TAR)</span> |
| <span id="L361"><span class="lineNum"> 361</span> : : */</span> |
| <span id="L362"><span class="lineNum"> 362</span> : : { "target-address-register",</span> |
| <span id="L363"><span class="lineNum"> 363</span> : : CPU_ALL,</span> |
| <span id="L364"><span class="lineNum"> 364</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L365"><span class="lineNum"> 365</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L366"><span class="lineNum"> 366</span> : : PPC_BITLSHIFT(55), PPC_BITLSHIFT(55), 58,</span> |
| <span id="L367"><span class="lineNum"> 367</span> : : NULL, },</span> |
| <span id="L368"><span class="lineNum"> 368</span> : : </span> |
| <span id="L369"><span class="lineNum"> 369</span> : : /*</span> |
| <span id="L370"><span class="lineNum"> 370</span> : : * ISAv2.07B Control Register (CTRL)</span> |
| <span id="L371"><span class="lineNum"> 371</span> : : */</span> |
| <span id="L372"><span class="lineNum"> 372</span> : : { "control-register",</span> |
| <span id="L373"><span class="lineNum"> 373</span> : : CPU_ALL,</span> |
| <span id="L374"><span class="lineNum"> 374</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L375"><span class="lineNum"> 375</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L376"><span class="lineNum"> 376</span> : : -1, -1, -1,</span> |
| <span id="L377"><span class="lineNum"> 377</span> : : NULL, },</span> |
| <span id="L378"><span class="lineNum"> 378</span> : : </span> |
| <span id="L379"><span class="lineNum"> 379</span> : : /*</span> |
| <span id="L380"><span class="lineNum"> 380</span> : : * ISAv2.07B Book3S Chapter 11. Processor Control.</span> |
| <span id="L381"><span class="lineNum"> 381</span> : : * msgsnd, msgsndp, doorbell, etc.</span> |
| <span id="L382"><span class="lineNum"> 382</span> : : *</span> |
| <span id="L383"><span class="lineNum"> 383</span> : : * ISAv3.0B is not compatible (different addressing, HFSCR required</span> |
| <span id="L384"><span class="lineNum"> 384</span> : : * for msgsndp).</span> |
| <span id="L385"><span class="lineNum"> 385</span> : : */</span> |
| <span id="L386"><span class="lineNum"> 386</span> : : { "processor-control-facility",</span> |
| <span id="L387"><span class="lineNum"> 387</span> : : CPU_P8_DD2, /* P8 DD1 has no dbell */</span> |
| <span id="L388"><span class="lineNum"> 388</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L389"><span class="lineNum"> 389</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L390"><span class="lineNum"> 390</span> : : -1, -1, -1,</span> |
| <span id="L391"><span class="lineNum"> 391</span> : : NULL, },</span> |
| <span id="L392"><span class="lineNum"> 392</span> : : </span> |
| <span id="L393"><span class="lineNum"> 393</span> : : /*</span> |
| <span id="L394"><span class="lineNum"> 394</span> : : * ISAv2.07B PURR, SPURR registers</span> |
| <span id="L395"><span class="lineNum"> 395</span> : : */</span> |
| <span id="L396"><span class="lineNum"> 396</span> : : { "processor-utilization-of-resources-register",</span> |
| <span id="L397"><span class="lineNum"> 397</span> : : CPU_ALL,</span> |
| <span id="L398"><span class="lineNum"> 398</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L399"><span class="lineNum"> 399</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L400"><span class="lineNum"> 400</span> : : -1, -1, -1,</span> |
| <span id="L401"><span class="lineNum"> 401</span> : : NULL, },</span> |
| <span id="L402"><span class="lineNum"> 402</span> : : </span> |
| <span id="L403"><span class="lineNum"> 403</span> : : /*</span> |
| <span id="L404"><span class="lineNum"> 404</span> : : * POWER8 initiate coprocessor store word indexed (icswx) instruction</span> |
| <span id="L405"><span class="lineNum"> 405</span> : : */</span> |
| <span id="L406"><span class="lineNum"> 406</span> : : { "coprocessor-icswx",</span> |
| <span id="L407"><span class="lineNum"> 407</span> : : CPU_P8,</span> |
| <span id="L408"><span class="lineNum"> 408</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L409"><span class="lineNum"> 409</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L410"><span class="lineNum"> 410</span> : : -1, -1, -1,</span> |
| <span id="L411"><span class="lineNum"> 411</span> : : NULL, },</span> |
| <span id="L412"><span class="lineNum"> 412</span> : : </span> |
| <span id="L413"><span class="lineNum"> 413</span> : : /*</span> |
| <span id="L414"><span class="lineNum"> 414</span> : : * ISAv2.07B hash based MMU and all instructions, registers,</span> |
| <span id="L415"><span class="lineNum"> 415</span> : : * data structures, exceptions, etc.</span> |
| <span id="L416"><span class="lineNum"> 416</span> : : */</span> |
| <span id="L417"><span class="lineNum"> 417</span> : : { "mmu-hash",</span> |
| <span id="L418"><span class="lineNum"> 418</span> : : CPU_P8,</span> |
| <span id="L419"><span class="lineNum"> 419</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L420"><span class="lineNum"> 420</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L421"><span class="lineNum"> 421</span> : : -1, -1, -1,</span> |
| <span id="L422"><span class="lineNum"> 422</span> : : NULL, },</span> |
| <span id="L423"><span class="lineNum"> 423</span> : : </span> |
| <span id="L424"><span class="lineNum"> 424</span> : : /*</span> |
| <span id="L425"><span class="lineNum"> 425</span> : : * POWER8 MCE / machine check exception.</span> |
| <span id="L426"><span class="lineNum"> 426</span> : : */</span> |
| <span id="L427"><span class="lineNum"> 427</span> : : { "machine-check-power8",</span> |
| <span id="L428"><span class="lineNum"> 428</span> : : CPU_P8,</span> |
| <span id="L429"><span class="lineNum"> 429</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L430"><span class="lineNum"> 430</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L431"><span class="lineNum"> 431</span> : : -1, -1, -1,</span> |
| <span id="L432"><span class="lineNum"> 432</span> : : NULL, },</span> |
| <span id="L433"><span class="lineNum"> 433</span> : : </span> |
| <span id="L434"><span class="lineNum"> 434</span> : : /*</span> |
| <span id="L435"><span class="lineNum"> 435</span> : : * POWER8 PMU / performance monitor unit.</span> |
| <span id="L436"><span class="lineNum"> 436</span> : : */</span> |
| <span id="L437"><span class="lineNum"> 437</span> : : { "performance-monitor-power8",</span> |
| <span id="L438"><span class="lineNum"> 438</span> : : CPU_P8,</span> |
| <span id="L439"><span class="lineNum"> 439</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L440"><span class="lineNum"> 440</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L441"><span class="lineNum"> 441</span> : : -1, -1, -1,</span> |
| <span id="L442"><span class="lineNum"> 442</span> : : NULL, },</span> |
| <span id="L443"><span class="lineNum"> 443</span> : : </span> |
| <span id="L444"><span class="lineNum"> 444</span> : : /*</span> |
| <span id="L445"><span class="lineNum"> 445</span> : : * ISAv2.07B alignment interrupts set DSISR register</span> |
| <span id="L446"><span class="lineNum"> 446</span> : : *</span> |
| <span id="L447"><span class="lineNum"> 447</span> : : * POWER CPUs do not used this, and it's removed from ISAv3.0B.</span> |
| <span id="L448"><span class="lineNum"> 448</span> : : */</span> |
| <span id="L449"><span class="lineNum"> 449</span> : : { "alignment-interrupt-dsisr",</span> |
| <span id="L450"><span class="lineNum"> 450</span> : : 0,</span> |
| <span id="L451"><span class="lineNum"> 451</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L452"><span class="lineNum"> 452</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L453"><span class="lineNum"> 453</span> : : -1, -1, -1,</span> |
| <span id="L454"><span class="lineNum"> 454</span> : : NULL, },</span> |
| <span id="L455"><span class="lineNum"> 455</span> : : </span> |
| <span id="L456"><span class="lineNum"> 456</span> : : /*</span> |
| <span id="L457"><span class="lineNum"> 457</span> : : * ISAv2.07B / POWER8 doze, nap, sleep, winkle instructions</span> |
| <span id="L458"><span class="lineNum"> 458</span> : : * XXX: is Linux we using some BookIV specific implementation details</span> |
| <span id="L459"><span class="lineNum"> 459</span> : : * in nap handling? We have no POWER8 specific key here.</span> |
| <span id="L460"><span class="lineNum"> 460</span> : : */</span> |
| <span id="L461"><span class="lineNum"> 461</span> : : { "idle-nap",</span> |
| <span id="L462"><span class="lineNum"> 462</span> : : CPU_P8,</span> |
| <span id="L463"><span class="lineNum"> 463</span> : : ISA_BASE, USABLE_HV,</span> |
| <span id="L464"><span class="lineNum"> 464</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L465"><span class="lineNum"> 465</span> : : -1, -1, -1,</span> |
| <span id="L466"><span class="lineNum"> 466</span> : : NULL, },</span> |
| <span id="L467"><span class="lineNum"> 467</span> : : </span> |
| <span id="L468"><span class="lineNum"> 468</span> : : /*</span> |
| <span id="L469"><span class="lineNum"> 469</span> : : * ISAv2.07B wait instruction</span> |
| <span id="L470"><span class="lineNum"> 470</span> : : */</span> |
| <span id="L471"><span class="lineNum"> 471</span> : : { "wait",</span> |
| <span id="L472"><span class="lineNum"> 472</span> : : CPU_P8,</span> |
| <span id="L473"><span class="lineNum"> 473</span> : : ISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L474"><span class="lineNum"> 474</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L475"><span class="lineNum"> 475</span> : : -1, -1, -1,</span> |
| <span id="L476"><span class="lineNum"> 476</span> : : NULL, },</span> |
| <span id="L477"><span class="lineNum"> 477</span> : : </span> |
| <span id="L478"><span class="lineNum"> 478</span> : : { "subcore",</span> |
| <span id="L479"><span class="lineNum"> 479</span> : : CPU_P8,</span> |
| <span id="L480"><span class="lineNum"> 480</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L481"><span class="lineNum"> 481</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L482"><span class="lineNum"> 482</span> : : -1, -1, -1,</span> |
| <span id="L483"><span class="lineNum"> 483</span> : : "smt", },</span> |
| <span id="L484"><span class="lineNum"> 484</span> : : </span> |
| <span id="L485"><span class="lineNum"> 485</span> : : /*</span> |
| <span id="L486"><span class="lineNum"> 486</span> : : * ISAv3.0B radix based MMU</span> |
| <span id="L487"><span class="lineNum"> 487</span> : : */</span> |
| <span id="L488"><span class="lineNum"> 488</span> : : { "mmu-radix",</span> |
| <span id="L489"><span class="lineNum"> 489</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L490"><span class="lineNum"> 490</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L491"><span class="lineNum"> 491</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L492"><span class="lineNum"> 492</span> : : -1, -1, -1,</span> |
| <span id="L493"><span class="lineNum"> 493</span> : : NULL, },</span> |
| <span id="L494"><span class="lineNum"> 494</span> : : </span> |
| <span id="L495"><span class="lineNum"> 495</span> : : /*</span> |
| <span id="L496"><span class="lineNum"> 496</span> : : * ISAv3.0B hash based MMU, new hash pte format, PCTR, etc</span> |
| <span id="L497"><span class="lineNum"> 497</span> : : */</span> |
| <span id="L498"><span class="lineNum"> 498</span> : : { "mmu-hash-v3",</span> |
| <span id="L499"><span class="lineNum"> 499</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L500"><span class="lineNum"> 500</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L501"><span class="lineNum"> 501</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L502"><span class="lineNum"> 502</span> : : -1, -1, -1,</span> |
| <span id="L503"><span class="lineNum"> 503</span> : : NULL, },</span> |
| <span id="L504"><span class="lineNum"> 504</span> : : </span> |
| <span id="L505"><span class="lineNum"> 505</span> : : /*</span> |
| <span id="L506"><span class="lineNum"> 506</span> : : * ISAv3.0B wait instruction</span> |
| <span id="L507"><span class="lineNum"> 507</span> : : */</span> |
| <span id="L508"><span class="lineNum"> 508</span> : : { "wait-v3",</span> |
| <span id="L509"><span class="lineNum"> 509</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L510"><span class="lineNum"> 510</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L511"><span class="lineNum"> 511</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L512"><span class="lineNum"> 512</span> : : -1, -1, -1,</span> |
| <span id="L513"><span class="lineNum"> 513</span> : : NULL, },</span> |
| <span id="L514"><span class="lineNum"> 514</span> : : </span> |
| <span id="L515"><span class="lineNum"> 515</span> : : /*</span> |
| <span id="L516"><span class="lineNum"> 516</span> : : * ISAv3.0B stop idle instructions and registers</span> |
| <span id="L517"><span class="lineNum"> 517</span> : : * XXX: Same question as for idle-nap</span> |
| <span id="L518"><span class="lineNum"> 518</span> : : */</span> |
| <span id="L519"><span class="lineNum"> 519</span> : : { "idle-stop",</span> |
| <span id="L520"><span class="lineNum"> 520</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L521"><span class="lineNum"> 521</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L522"><span class="lineNum"> 522</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L523"><span class="lineNum"> 523</span> : : -1, -1, -1,</span> |
| <span id="L524"><span class="lineNum"> 524</span> : : NULL, },</span> |
| <span id="L525"><span class="lineNum"> 525</span> : : </span> |
| <span id="L526"><span class="lineNum"> 526</span> : : /*</span> |
| <span id="L527"><span class="lineNum"> 527</span> : : * ISAv3.0B Hypervisor Virtualization Interrupt</span> |
| <span id="L528"><span class="lineNum"> 528</span> : : * Also associated system registers, LPCR EE, HEIC, HVICE,</span> |
| <span id="L529"><span class="lineNum"> 529</span> : : * system reset SRR1 reason, etc.</span> |
| <span id="L530"><span class="lineNum"> 530</span> : : */</span> |
| <span id="L531"><span class="lineNum"> 531</span> : : { "hypervisor-virtualization-interrupt",</span> |
| <span id="L532"><span class="lineNum"> 532</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L533"><span class="lineNum"> 533</span> : : ISA_V3_0B, USABLE_HV,</span> |
| <span id="L534"><span class="lineNum"> 534</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L535"><span class="lineNum"> 535</span> : : -1, -1, -1,</span> |
| <span id="L536"><span class="lineNum"> 536</span> : : NULL, },</span> |
| <span id="L537"><span class="lineNum"> 537</span> : : </span> |
| <span id="L538"><span class="lineNum"> 538</span> : : /*</span> |
| <span id="L539"><span class="lineNum"> 539</span> : : * POWER9 MCE / machine check exception.</span> |
| <span id="L540"><span class="lineNum"> 540</span> : : */</span> |
| <span id="L541"><span class="lineNum"> 541</span> : : { "machine-check-power9",</span> |
| <span id="L542"><span class="lineNum"> 542</span> : : CPU_P9,</span> |
| <span id="L543"><span class="lineNum"> 543</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L544"><span class="lineNum"> 544</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L545"><span class="lineNum"> 545</span> : : -1, -1, -1,</span> |
| <span id="L546"><span class="lineNum"> 546</span> : : NULL, },</span> |
| <span id="L547"><span class="lineNum"> 547</span> : : </span> |
| <span id="L548"><span class="lineNum"> 548</span> : : /*</span> |
| <span id="L549"><span class="lineNum"> 549</span> : : * POWER10 MCE / machine check exception.</span> |
| <span id="L550"><span class="lineNum"> 550</span> : : */</span> |
| <span id="L551"><span class="lineNum"> 551</span> : : { "machine-check-power10",</span> |
| <span id="L552"><span class="lineNum"> 552</span> : : CPU_P10|CPU_P11,</span> |
| <span id="L553"><span class="lineNum"> 553</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L554"><span class="lineNum"> 554</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L555"><span class="lineNum"> 555</span> : : -1, -1, -1,</span> |
| <span id="L556"><span class="lineNum"> 556</span> : : NULL, },</span> |
| <span id="L557"><span class="lineNum"> 557</span> : : </span> |
| <span id="L558"><span class="lineNum"> 558</span> : : /*</span> |
| <span id="L559"><span class="lineNum"> 559</span> : : * POWER9 PMU / performance monitor unit.</span> |
| <span id="L560"><span class="lineNum"> 560</span> : : */</span> |
| <span id="L561"><span class="lineNum"> 561</span> : : { "performance-monitor-power9",</span> |
| <span id="L562"><span class="lineNum"> 562</span> : : CPU_P9,</span> |
| <span id="L563"><span class="lineNum"> 563</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L564"><span class="lineNum"> 564</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L565"><span class="lineNum"> 565</span> : : -1, -1, -1,</span> |
| <span id="L566"><span class="lineNum"> 566</span> : : NULL, },</span> |
| <span id="L567"><span class="lineNum"> 567</span> : : </span> |
| <span id="L568"><span class="lineNum"> 568</span> : : /*</span> |
| <span id="L569"><span class="lineNum"> 569</span> : : * POWER10 PMU / performance monitor unit.</span> |
| <span id="L570"><span class="lineNum"> 570</span> : : */</span> |
| <span id="L571"><span class="lineNum"> 571</span> : : { "performance-monitor-power10",</span> |
| <span id="L572"><span class="lineNum"> 572</span> : : CPU_P10|CPU_P11,</span> |
| <span id="L573"><span class="lineNum"> 573</span> : : ISA_V3_1, USABLE_HV|USABLE_OS,</span> |
| <span id="L574"><span class="lineNum"> 574</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L575"><span class="lineNum"> 575</span> : : -1, -1, -1,</span> |
| <span id="L576"><span class="lineNum"> 576</span> : : NULL, },</span> |
| <span id="L577"><span class="lineNum"> 577</span> : : </span> |
| <span id="L578"><span class="lineNum"> 578</span> : : /*</span> |
| <span id="L579"><span class="lineNum"> 579</span> : : * ISAv3.0B scv/rfscv system call instructions and exceptions, fscr bit</span> |
| <span id="L580"><span class="lineNum"> 580</span> : : * etc.</span> |
| <span id="L581"><span class="lineNum"> 581</span> : : */</span> |
| <span id="L582"><span class="lineNum"> 582</span> : : { "system-call-vectored",</span> |
| <span id="L583"><span class="lineNum"> 583</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L584"><span class="lineNum"> 584</span> : : ISA_V3_0B, USABLE_OS|USABLE_PR,</span> |
| <span id="L585"><span class="lineNum"> 585</span> : : HV_NONE, OS_CUSTOM,</span> |
| <span id="L586"><span class="lineNum"> 586</span> : : -1, PPC_BITLSHIFT(51), 52,</span> |
| <span id="L587"><span class="lineNum"> 587</span> : : NULL, },</span> |
| <span id="L588"><span class="lineNum"> 588</span> : : </span> |
| <span id="L589"><span class="lineNum"> 589</span> : : /*</span> |
| <span id="L590"><span class="lineNum"> 590</span> : : * ISAv3.0B Book3S Chapter 10. Processor Control.</span> |
| <span id="L591"><span class="lineNum"> 591</span> : : * global msgsnd, msgsndp, msgsync, doorbell, etc.</span> |
| <span id="L592"><span class="lineNum"> 592</span> : : */</span> |
| <span id="L593"><span class="lineNum"> 593</span> : : { "processor-control-facility-v3",</span> |
| <span id="L594"><span class="lineNum"> 594</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L595"><span class="lineNum"> 595</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L596"><span class="lineNum"> 596</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L597"><span class="lineNum"> 597</span> : : PPC_BITLSHIFT(53), -1, -1,</span> |
| <span id="L598"><span class="lineNum"> 598</span> : : NULL, },</span> |
| <span id="L599"><span class="lineNum"> 599</span> : : </span> |
| <span id="L600"><span class="lineNum"> 600</span> : : /*</span> |
| <span id="L601"><span class="lineNum"> 601</span> : : * ISAv3.0B addpcis instruction</span> |
| <span id="L602"><span class="lineNum"> 602</span> : : */</span> |
| <span id="L603"><span class="lineNum"> 603</span> : : { "pc-relative-addressing",</span> |
| <span id="L604"><span class="lineNum"> 604</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L605"><span class="lineNum"> 605</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L606"><span class="lineNum"> 606</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L607"><span class="lineNum"> 607</span> : : -1, -1, -1,</span> |
| <span id="L608"><span class="lineNum"> 608</span> : : NULL, },</span> |
| <span id="L609"><span class="lineNum"> 609</span> : : </span> |
| <span id="L610"><span class="lineNum"> 610</span> : : /*</span> |
| <span id="L611"><span class="lineNum"> 611</span> : : * ISAv2.07B Book3S Chapter 7. Timer Facilities</span> |
| <span id="L612"><span class="lineNum"> 612</span> : : * TB, VTB, DEC, HDEC, IC, etc registers and exceptions.</span> |
| <span id="L613"><span class="lineNum"> 613</span> : : * Not including PURR or SPURR registers.</span> |
| <span id="L614"><span class="lineNum"> 614</span> : : */</span> |
| <span id="L615"><span class="lineNum"> 615</span> : : { "timer-facilities",</span> |
| <span id="L616"><span class="lineNum"> 616</span> : : CPU_ALL,</span> |
| <span id="L617"><span class="lineNum"> 617</span> : : ISA_BASE, USABLE_HV|USABLE_OS,</span> |
| <span id="L618"><span class="lineNum"> 618</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L619"><span class="lineNum"> 619</span> : : -1, -1, -1,</span> |
| <span id="L620"><span class="lineNum"> 620</span> : : NULL, },</span> |
| <span id="L621"><span class="lineNum"> 621</span> : : </span> |
| <span id="L622"><span class="lineNum"> 622</span> : : /*</span> |
| <span id="L623"><span class="lineNum"> 623</span> : : * ISAv3.0B Book3S Chapter 7. Timer Facilities</span> |
| <span id="L624"><span class="lineNum"> 624</span> : : * Large decrementer and hypervisor decrementer</span> |
| <span id="L625"><span class="lineNum"> 625</span> : : */</span> |
| <span id="L626"><span class="lineNum"> 626</span> : : { "timer-facilities-v3",</span> |
| <span id="L627"><span class="lineNum"> 627</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L628"><span class="lineNum"> 628</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L629"><span class="lineNum"> 629</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L630"><span class="lineNum"> 630</span> : : -1, -1, -1,</span> |
| <span id="L631"><span class="lineNum"> 631</span> : : "timer-facilities", },</span> |
| <span id="L632"><span class="lineNum"> 632</span> : : </span> |
| <span id="L633"><span class="lineNum"> 633</span> : : /*</span> |
| <span id="L634"><span class="lineNum"> 634</span> : : * ISAv3.0B deliver a random number instruction (darn)</span> |
| <span id="L635"><span class="lineNum"> 635</span> : : */</span> |
| <span id="L636"><span class="lineNum"> 636</span> : : { "random-number-generator",</span> |
| <span id="L637"><span class="lineNum"> 637</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L638"><span class="lineNum"> 638</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L639"><span class="lineNum"> 639</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L640"><span class="lineNum"> 640</span> : : -1, -1, 53,</span> |
| <span id="L641"><span class="lineNum"> 641</span> : : NULL, },</span> |
| <span id="L642"><span class="lineNum"> 642</span> : : </span> |
| <span id="L643"><span class="lineNum"> 643</span> : : /*</span> |
| <span id="L644"><span class="lineNum"> 644</span> : : * ISAv3.0B fixed point instructions and registers</span> |
| <span id="L645"><span class="lineNum"> 645</span> : : * multiply-add, modulo, count trailing zeroes, cmprb, cmpeqb,</span> |
| <span id="L646"><span class="lineNum"> 646</span> : : * extswsli, mfvsrld, mtvsrdd, mtvsrws, addex, CA32, OV32,</span> |
| <span id="L647"><span class="lineNum"> 647</span> : : * mcrxrx, setb</span> |
| <span id="L648"><span class="lineNum"> 648</span> : : */</span> |
| <span id="L649"><span class="lineNum"> 649</span> : : { "fixed-point-v3",</span> |
| <span id="L650"><span class="lineNum"> 650</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L651"><span class="lineNum"> 651</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L652"><span class="lineNum"> 652</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L653"><span class="lineNum"> 653</span> : : -1, -1, -1,</span> |
| <span id="L654"><span class="lineNum"> 654</span> : : NULL, },</span> |
| <span id="L655"><span class="lineNum"> 655</span> : : </span> |
| <span id="L656"><span class="lineNum"> 656</span> : : { "decimal-integer-v3",</span> |
| <span id="L657"><span class="lineNum"> 657</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L658"><span class="lineNum"> 658</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L659"><span class="lineNum"> 659</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L660"><span class="lineNum"> 660</span> : : -1, -1, -1,</span> |
| <span id="L661"><span class="lineNum"> 661</span> : : "fixed-point-v3 decimal-integer", },</span> |
| <span id="L662"><span class="lineNum"> 662</span> : : </span> |
| <span id="L663"><span class="lineNum"> 663</span> : : /*</span> |
| <span id="L664"><span class="lineNum"> 664</span> : : * ISAv3.0B lightweight mffs</span> |
| <span id="L665"><span class="lineNum"> 665</span> : : */</span> |
| <span id="L666"><span class="lineNum"> 666</span> : : { "floating-point-v3",</span> |
| <span id="L667"><span class="lineNum"> 667</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L668"><span class="lineNum"> 668</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L669"><span class="lineNum"> 669</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L670"><span class="lineNum"> 670</span> : : -1, -1, -1,</span> |
| <span id="L671"><span class="lineNum"> 671</span> : : "floating-point", },</span> |
| <span id="L672"><span class="lineNum"> 672</span> : : </span> |
| <span id="L673"><span class="lineNum"> 673</span> : : { "decimal-floating-point-v3",</span> |
| <span id="L674"><span class="lineNum"> 674</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L675"><span class="lineNum"> 675</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L676"><span class="lineNum"> 676</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L677"><span class="lineNum"> 677</span> : : -1, -1, -1,</span> |
| <span id="L678"><span class="lineNum"> 678</span> : : "floating-point-v3 decimal-floating-point", },</span> |
| <span id="L679"><span class="lineNum"> 679</span> : : </span> |
| <span id="L680"><span class="lineNum"> 680</span> : : { "vector-v3",</span> |
| <span id="L681"><span class="lineNum"> 681</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L682"><span class="lineNum"> 682</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L683"><span class="lineNum"> 683</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L684"><span class="lineNum"> 684</span> : : -1, -1, -1,</span> |
| <span id="L685"><span class="lineNum"> 685</span> : : "vector", },</span> |
| <span id="L686"><span class="lineNum"> 686</span> : : </span> |
| <span id="L687"><span class="lineNum"> 687</span> : : { "vector-scalar-v3",</span> |
| <span id="L688"><span class="lineNum"> 688</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L689"><span class="lineNum"> 689</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L690"><span class="lineNum"> 690</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L691"><span class="lineNum"> 691</span> : : -1, -1, -1,</span> |
| <span id="L692"><span class="lineNum"> 692</span> : : "vector-v3 vector-scalar" },</span> |
| <span id="L693"><span class="lineNum"> 693</span> : : </span> |
| <span id="L694"><span class="lineNum"> 694</span> : : { "vector-binary128",</span> |
| <span id="L695"><span class="lineNum"> 695</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L696"><span class="lineNum"> 696</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L697"><span class="lineNum"> 697</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L698"><span class="lineNum"> 698</span> : : -1, -1, 54,</span> |
| <span id="L699"><span class="lineNum"> 699</span> : : "vector-scalar-v3", },</span> |
| <span id="L700"><span class="lineNum"> 700</span> : : </span> |
| <span id="L701"><span class="lineNum"> 701</span> : : { "vector-binary16",</span> |
| <span id="L702"><span class="lineNum"> 702</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L703"><span class="lineNum"> 703</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L704"><span class="lineNum"> 704</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L705"><span class="lineNum"> 705</span> : : -1, -1, -1,</span> |
| <span id="L706"><span class="lineNum"> 706</span> : : "vector-v3", },</span> |
| <span id="L707"><span class="lineNum"> 707</span> : : </span> |
| <span id="L708"><span class="lineNum"> 708</span> : : /*</span> |
| <span id="L709"><span class="lineNum"> 709</span> : : * ISAv3.0B external exception for EBB</span> |
| <span id="L710"><span class="lineNum"> 710</span> : : */</span> |
| <span id="L711"><span class="lineNum"> 711</span> : : { "event-based-branch-v3",</span> |
| <span id="L712"><span class="lineNum"> 712</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L713"><span class="lineNum"> 713</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L714"><span class="lineNum"> 714</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L715"><span class="lineNum"> 715</span> : : -1, -1, -1,</span> |
| <span id="L716"><span class="lineNum"> 716</span> : : "event-based-branch", },</span> |
| <span id="L717"><span class="lineNum"> 717</span> : : </span> |
| <span id="L718"><span class="lineNum"> 718</span> : : /*</span> |
| <span id="L719"><span class="lineNum"> 719</span> : : * ISAv3.0B Atomic Memory Operations (AMO)</span> |
| <span id="L720"><span class="lineNum"> 720</span> : : */</span> |
| <span id="L721"><span class="lineNum"> 721</span> : : { "atomic-memory-operations",</span> |
| <span id="L722"><span class="lineNum"> 722</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L723"><span class="lineNum"> 723</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L724"><span class="lineNum"> 724</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L725"><span class="lineNum"> 725</span> : : -1, -1, -1,</span> |
| <span id="L726"><span class="lineNum"> 726</span> : : NULL, },</span> |
| <span id="L727"><span class="lineNum"> 727</span> : : </span> |
| <span id="L728"><span class="lineNum"> 728</span> : : /*</span> |
| <span id="L729"><span class="lineNum"> 729</span> : : * ISAv3.0B Copy-Paste Facility</span> |
| <span id="L730"><span class="lineNum"> 730</span> : : */</span> |
| <span id="L731"><span class="lineNum"> 731</span> : : { "copy-paste",</span> |
| <span id="L732"><span class="lineNum"> 732</span> : : CPU_P9|CPU_P10|CPU_P11,</span> |
| <span id="L733"><span class="lineNum"> 733</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L734"><span class="lineNum"> 734</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L735"><span class="lineNum"> 735</span> : : -1, -1, -1,</span> |
| <span id="L736"><span class="lineNum"> 736</span> : : NULL, },</span> |
| <span id="L737"><span class="lineNum"> 737</span> : : </span> |
| <span id="L738"><span class="lineNum"> 738</span> : : /*</span> |
| <span id="L739"><span class="lineNum"> 739</span> : : * ISAv3.0B GSR SPR register</span> |
| <span id="L740"><span class="lineNum"> 740</span> : : * POWER9 does not implement it</span> |
| <span id="L741"><span class="lineNum"> 741</span> : : */</span> |
| <span id="L742"><span class="lineNum"> 742</span> : : { "group-start-register",</span> |
| <span id="L743"><span class="lineNum"> 743</span> : : 0,</span> |
| <span id="L744"><span class="lineNum"> 744</span> : : ISA_V3_0B, USABLE_HV|USABLE_OS,</span> |
| <span id="L745"><span class="lineNum"> 745</span> : : HV_NONE, OS_NONE,</span> |
| <span id="L746"><span class="lineNum"> 746</span> : : -1, -1, -1,</span> |
| <span id="L747"><span class="lineNum"> 747</span> : : NULL, },</span> |
| <span id="L748"><span class="lineNum"> 748</span> : : </span> |
| <span id="L749"><span class="lineNum"> 749</span> : : /*</span> |
| <span id="L750"><span class="lineNum"> 750</span> : : * Enable matrix multiply accumulate.</span> |
| <span id="L751"><span class="lineNum"> 751</span> : : */</span> |
| <span id="L752"><span class="lineNum"> 752</span> : : { "matrix-multiply-accumulate",</span> |
| <span id="L753"><span class="lineNum"> 753</span> : : CPU_P10|CPU_P11,</span> |
| <span id="L754"><span class="lineNum"> 754</span> : : ISA_V3_1, USABLE_PR,</span> |
| <span id="L755"><span class="lineNum"> 755</span> : : HV_CUSTOM, OS_CUSTOM,</span> |
| <span id="L756"><span class="lineNum"> 756</span> : : -1, -1, 49,</span> |
| <span id="L757"><span class="lineNum"> 757</span> : : NULL, },</span> |
| <span id="L758"><span class="lineNum"> 758</span> : : </span> |
| <span id="L759"><span class="lineNum"> 759</span> : : /*</span> |
| <span id="L760"><span class="lineNum"> 760</span> : : * Enable prefix instructions. Toolchains assume this is</span> |
| <span id="L761"><span class="lineNum"> 761</span> : : * enabled for when compiling for ISA 3.1.</span> |
| <span id="L762"><span class="lineNum"> 762</span> : : */</span> |
| <span id="L763"><span class="lineNum"> 763</span> : : { "prefix-instructions",</span> |
| <span id="L764"><span class="lineNum"> 764</span> : : CPU_P10|CPU_P11,</span> |
| <span id="L765"><span class="lineNum"> 765</span> : : ISA_V3_1, USABLE_HV|USABLE_OS|USABLE_PR,</span> |
| <span id="L766"><span class="lineNum"> 766</span> : : HV_HFSCR, OS_FSCR,</span> |
| <span id="L767"><span class="lineNum"> 767</span> : : 13, 13, -1,</span> |
| <span id="L768"><span class="lineNum"> 768</span> : : NULL, },</span> |
| <span id="L769"><span class="lineNum"> 769</span> : : </span> |
| <span id="L770"><span class="lineNum"> 770</span> : : /*</span> |
| <span id="L771"><span class="lineNum"> 771</span> : : * Due to hardware bugs in POWER9, the hypervisor needs to assist</span> |
| <span id="L772"><span class="lineNum"> 772</span> : : * guests.</span> |
| <span id="L773"><span class="lineNum"> 773</span> : : *</span> |
| <span id="L774"><span class="lineNum"> 774</span> : : * Presence of this feature indicates presence of the bug.</span> |
| <span id="L775"><span class="lineNum"> 775</span> : : *</span> |
| <span id="L776"><span class="lineNum"> 776</span> : : * See linux kernel commit 4bb3c7a0208f</span> |
| <span id="L777"><span class="lineNum"> 777</span> : : * and linux Documentation/powerpc/transactional_memory.txt</span> |
| <span id="L778"><span class="lineNum"> 778</span> : : */</span> |
| <span id="L779"><span class="lineNum"> 779</span> : : { "tm-suspend-hypervisor-assist",</span> |
| <span id="L780"><span class="lineNum"> 780</span> : : CPU_P9_DD2_2|CPU_P9_DD2_3|CPU_P9P,</span> |
| <span id="L781"><span class="lineNum"> 781</span> : : ISA_V3_0B, USABLE_HV,</span> |
| <span id="L782"><span class="lineNum"> 782</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L783"><span class="lineNum"> 783</span> : : -1, -1, -1,</span> |
| <span id="L784"><span class="lineNum"> 784</span> : : NULL, },</span> |
| <span id="L785"><span class="lineNum"> 785</span> : : </span> |
| <span id="L786"><span class="lineNum"> 786</span> : : /*</span> |
| <span id="L787"><span class="lineNum"> 787</span> : : * Due to hardware bugs in POWER9, the hypervisor can hit</span> |
| <span id="L788"><span class="lineNum"> 788</span> : : * CPU bugs in the operations it needs to do for</span> |
| <span id="L789"><span class="lineNum"> 789</span> : : * tm-suspend-hypervisor-assist.</span> |
| <span id="L790"><span class="lineNum"> 790</span> : : *</span> |
| <span id="L791"><span class="lineNum"> 791</span> : : * Presence of this "feature" means processor is affected by the bug.</span> |
| <span id="L792"><span class="lineNum"> 792</span> : : *</span> |
| <span id="L793"><span class="lineNum"> 793</span> : : * See linux kernel commit 4bb3c7a0208f</span> |
| <span id="L794"><span class="lineNum"> 794</span> : : * and linux Documentation/powerpc/transactional_memory.txt</span> |
| <span id="L795"><span class="lineNum"> 795</span> : : */</span> |
| <span id="L796"><span class="lineNum"> 796</span> : : { "tm-suspend-xer-so-bug",</span> |
| <span id="L797"><span class="lineNum"> 797</span> : : CPU_P9_DD2_2,</span> |
| <span id="L798"><span class="lineNum"> 798</span> : : ISA_V3_0B, USABLE_HV,</span> |
| <span id="L799"><span class="lineNum"> 799</span> : : HV_CUSTOM, OS_NONE,</span> |
| <span id="L800"><span class="lineNum"> 800</span> : : -1, -1, -1,</span> |
| <span id="L801"><span class="lineNum"> 801</span> : : NULL, },</span> |
| <span id="L802"><span class="lineNum"> 802</span> : : };</span> |
| <span id="L803"><span class="lineNum"> 803</span> : : </span> |
| <span id="L804"><span class="lineNum"> 804</span> :<span class="tlaGNC tlaBgGNC"> 432 : static void add_cpu_feature_nodeps(struct dt_node *features,</span></span> |
| <span id="L805"><span class="lineNum"> 805</span> : : const struct cpu_feature *f)</span> |
| <span id="L806"><span class="lineNum"> 806</span> : : {</span> |
| <span id="L807"><span class="lineNum"> 807</span> : : struct dt_node *feature;</span> |
| <span id="L808"><span class="lineNum"> 808</span> : : </span> |
| <span id="L809"><span class="lineNum"> 809</span> :<span class="tlaGNC"> 432 : feature = dt_new(features, f->name);</span></span> |
| <span id="L810"><span class="lineNum"> 810</span> :<span class="tlaGNC"> 432 : assert(feature);</span></span> |
| <span id="L811"><span class="lineNum"> 811</span> : : </span> |
| <span id="L812"><span class="lineNum"> 812</span> :<span class="tlaGNC"> 432 : dt_add_property_cells(feature, "isa", f->isa);</span></span> |
| <span id="L813"><span class="lineNum"> 813</span> :<span class="tlaGNC"> 432 : dt_add_property_cells(feature, "usable-privilege", f->usable_privilege);</span></span> |
| <span id="L814"><span class="lineNum"> 814</span> : : </span> |
| <span id="L815"><span class="lineNum"> 815</span> :<span class="tlaGNC"> 432 : if (f->usable_privilege & USABLE_HV) {</span></span> |
| <span id="L816"><span class="lineNum"> 816</span> :<span class="tlaGNC"> 427 : if (f->hv_support != HV_NONE) {</span></span> |
| <span id="L817"><span class="lineNum"> 817</span> :<span class="tlaGNC"> 287 : uint32_t s = 0;</span></span> |
| <span id="L818"><span class="lineNum"> 818</span> :<span class="tlaGNC"> 287 : if (f->hv_support == HV_HFSCR)</span></span> |
| <span id="L819"><span class="lineNum"> 819</span> :<span class="tlaUNC tlaBgUNC"> 0 : s |= HV_SUPPORT_HFSCR;</span></span> |
| <span id="L820"><span class="lineNum"> 820</span> : : </span> |
| <span id="L821"><span class="lineNum"> 821</span> :<span class="tlaGNC tlaBgGNC"> 287 : dt_add_property_cells(feature, "hv-support", s);</span></span> |
| <span id="L822"><span class="lineNum"> 822</span> :<span class="tlaGNC"> 287 : if (f->hfscr_bit_nr != -1)</span></span> |
| <span id="L823"><span class="lineNum"> 823</span> :<span class="tlaGNC"> 70 : dt_add_property_cells(feature, "hfscr-bit-nr", f->hfscr_bit_nr);</span></span> |
| <span id="L824"><span class="lineNum"> 824</span> : : } else {</span> |
| <span id="L825"><span class="lineNum"> 825</span> :<span class="tlaGNC"> 140 : assert(f->hfscr_bit_nr == -1);</span></span> |
| <span id="L826"><span class="lineNum"> 826</span> : : }</span> |
| <span id="L827"><span class="lineNum"> 827</span> : : }</span> |
| <span id="L828"><span class="lineNum"> 828</span> : : </span> |
| <span id="L829"><span class="lineNum"> 829</span> :<span class="tlaGNC"> 432 : if (f->usable_privilege & USABLE_OS) {</span></span> |
| <span id="L830"><span class="lineNum"> 830</span> :<span class="tlaGNC"> 408 : if (f->os_support != OS_NONE) {</span></span> |
| <span id="L831"><span class="lineNum"> 831</span> :<span class="tlaGNC"> 263 : uint32_t s = 0;</span></span> |
| <span id="L832"><span class="lineNum"> 832</span> :<span class="tlaGNC"> 263 : if (f->os_support == OS_FSCR)</span></span> |
| <span id="L833"><span class="lineNum"> 833</span> :<span class="tlaUNC tlaBgUNC"> 0 : s |= OS_SUPPORT_FSCR;</span></span> |
| <span id="L834"><span class="lineNum"> 834</span> :<span class="tlaGNC tlaBgGNC"> 263 : dt_add_property_cells(feature, "os-support", s);</span></span> |
| <span id="L835"><span class="lineNum"> 835</span> :<span class="tlaGNC"> 263 : if (f->fscr_bit_nr != -1)</span></span> |
| <span id="L836"><span class="lineNum"> 836</span> :<span class="tlaGNC"> 35 : dt_add_property_cells(feature, "fscr-bit-nr", f->fscr_bit_nr);</span></span> |
| <span id="L837"><span class="lineNum"> 837</span> : : } else {</span> |
| <span id="L838"><span class="lineNum"> 838</span> :<span class="tlaGNC"> 145 : assert(f->fscr_bit_nr == -1);</span></span> |
| <span id="L839"><span class="lineNum"> 839</span> : : }</span> |
| <span id="L840"><span class="lineNum"> 840</span> : : }</span> |
| <span id="L841"><span class="lineNum"> 841</span> : : </span> |
| <span id="L842"><span class="lineNum"> 842</span> :<span class="tlaGNC"> 432 : if (f->usable_privilege & USABLE_PR) {</span></span> |
| <span id="L843"><span class="lineNum"> 843</span> :<span class="tlaGNC"> 255 : if (f->hwcap_bit_nr != -1)</span></span> |
| <span id="L844"><span class="lineNum"> 844</span> :<span class="tlaGNC"> 110 : dt_add_property_cells(feature, "hwcap-bit-nr", f->hwcap_bit_nr);</span></span> |
| <span id="L845"><span class="lineNum"> 845</span> : : }</span> |
| <span id="L846"><span class="lineNum"> 846</span> : : </span> |
| <span id="L847"><span class="lineNum"> 847</span> :<span class="tlaGNC"> 432 : if (f->dependencies_names)</span></span> |
| <span id="L848"><span class="lineNum"> 848</span> :<span class="tlaGNC"> 110 : dt_add_property(feature, "dependencies", NULL, 0);</span></span> |
| <span id="L849"><span class="lineNum"> 849</span> :<span class="tlaGNC"> 432 : }</span></span> |
| <span id="L850"><span class="lineNum"> 850</span> : : </span> |
| <span id="L851"><span class="lineNum"> 851</span> :<span class="tlaGNC"> 10 : static void add_cpufeatures_dependencies(struct dt_node *features)</span></span> |
| <span id="L852"><span class="lineNum"> 852</span> : : {</span> |
| <span id="L853"><span class="lineNum"> 853</span> : : struct dt_node *feature;</span> |
| <span id="L854"><span class="lineNum"> 854</span> : : </span> |
| <span id="L855"><span class="lineNum"> 855</span> :<span class="tlaGNC"> 442 : dt_for_each_node(features, feature) {</span></span> |
| <span id="L856"><span class="lineNum"> 856</span> :<span class="tlaGNC"> 432 : const struct cpu_feature *f = NULL;</span></span> |
| <span id="L857"><span class="lineNum"> 857</span> : : const char *deps_names;</span> |
| <span id="L858"><span class="lineNum"> 858</span> : : struct dt_property *deps;</span> |
| <span id="L859"><span class="lineNum"> 859</span> : : int nr_deps;</span> |
| <span id="L860"><span class="lineNum"> 860</span> : : int i;</span> |
| <span id="L861"><span class="lineNum"> 861</span> : : </span> |
| <span id="L862"><span class="lineNum"> 862</span> : : /* Find features with dependencies */</span> |
| <span id="L863"><span class="lineNum"> 863</span> : : </span> |
| <span id="L864"><span class="lineNum"> 864</span> :<span class="tlaGNC"> 432 : deps = __dt_find_property(feature, "dependencies");</span></span> |
| <span id="L865"><span class="lineNum"> 865</span> :<span class="tlaGNC"> 432 : if (!deps)</span></span> |
| <span id="L866"><span class="lineNum"> 866</span> :<span class="tlaGNC"> 322 : continue;</span></span> |
| <span id="L867"><span class="lineNum"> 867</span> : : </span> |
| <span id="L868"><span class="lineNum"> 868</span> : : /* Find the matching cpu table */</span> |
| <span id="L869"><span class="lineNum"> 869</span> :<span class="tlaGNC"> 3780 : for (i = 0; i < ARRAY_SIZE(cpu_features_table); i++) {</span></span> |
| <span id="L870"><span class="lineNum"> 870</span> :<span class="tlaGNC"> 3780 : f = &cpu_features_table[i];</span></span> |
| <span id="L871"><span class="lineNum"> 871</span> :<span class="tlaGNC"> 3780 : if (!strcmp(f->name, feature->name))</span></span> |
| <span id="L872"><span class="lineNum"> 872</span> :<span class="tlaGNC"> 110 : break;</span></span> |
| <span id="L873"><span class="lineNum"> 873</span> : : }</span> |
| <span id="L874"><span class="lineNum"> 874</span> :<span class="tlaGNC"> 110 : assert(f);</span></span> |
| <span id="L875"><span class="lineNum"> 875</span> :<span class="tlaGNC"> 110 : assert(f->dependencies_names);</span></span> |
| <span id="L876"><span class="lineNum"> 876</span> : : </span> |
| <span id="L877"><span class="lineNum"> 877</span> : : /*</span> |
| <span id="L878"><span class="lineNum"> 878</span> : : * Count number of depended features and allocate space</span> |
| <span id="L879"><span class="lineNum"> 879</span> : : * for phandles in the property.</span> |
| <span id="L880"><span class="lineNum"> 880</span> : : */</span> |
| <span id="L881"><span class="lineNum"> 881</span> :<span class="tlaGNC"> 110 : deps_names = f->dependencies_names;</span></span> |
| <span id="L882"><span class="lineNum"> 882</span> :<span class="tlaGNC"> 110 : nr_deps = strcount(deps_names, " ") + 1;</span></span> |
| <span id="L883"><span class="lineNum"> 883</span> :<span class="tlaGNC"> 110 : dt_resize_property(&deps, nr_deps * sizeof(u32));</span></span> |
| <span id="L884"><span class="lineNum"> 884</span> : : </span> |
| <span id="L885"><span class="lineNum"> 885</span> :<span class="tlaGNC"> 110 : DBG("feature %s has %d dependencies (%s)\n", f->name, nr_deps, deps_names);</span></span> |
| <span id="L886"><span class="lineNum"> 886</span> : : /*</span> |
| <span id="L887"><span class="lineNum"> 887</span> : : * For each one, find the depended feature then advance to</span> |
| <span id="L888"><span class="lineNum"> 888</span> : : * next name.</span> |
| <span id="L889"><span class="lineNum"> 889</span> : : */</span> |
| <span id="L890"><span class="lineNum"> 890</span> :<span class="tlaGNC"> 235 : for (i = 0; i < nr_deps; i++) {</span></span> |
| <span id="L891"><span class="lineNum"> 891</span> : : struct dt_node *dep;</span> |
| <span id="L892"><span class="lineNum"> 892</span> : : int len;</span> |
| <span id="L893"><span class="lineNum"> 893</span> : : </span> |
| <span id="L894"><span class="lineNum"> 894</span> :<span class="tlaGNC"> 125 : if (nr_deps - i == 1)</span></span> |
| <span id="L895"><span class="lineNum"> 895</span> :<span class="tlaGNC"> 110 : len = strlen(deps_names);</span></span> |
| <span id="L896"><span class="lineNum"> 896</span> : : else</span> |
| <span id="L897"><span class="lineNum"> 897</span> :<span class="tlaGNC"> 15 : len = strchr(deps_names, ' ') - deps_names;</span></span> |
| <span id="L898"><span class="lineNum"> 898</span> : : </span> |
| <span id="L899"><span class="lineNum"> 899</span> :<span class="tlaGNC"> 3212 : dt_for_each_node(features, dep) {</span></span> |
| <span id="L900"><span class="lineNum"> 900</span> :<span class="tlaGNC"> 3212 : if (!strncmp(deps_names, dep->name, len))</span></span> |
| <span id="L901"><span class="lineNum"> 901</span> :<span class="tlaGNC"> 125 : goto found_dep;</span></span> |
| <span id="L902"><span class="lineNum"> 902</span> : : }</span> |
| <span id="L903"><span class="lineNum"> 903</span> : : </span> |
| <span id="L904"><span class="lineNum"> 904</span> :<span class="tlaUNC tlaBgUNC"> 0 : prlog(PR_ERR, "CPUFT: feature %s dependencies not found\n", f->name);</span></span> |
| <span id="L905"><span class="lineNum"> 905</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L906"><span class="lineNum"> 906</span> :<span class="tlaGNC tlaBgGNC"> 125 : found_dep:</span></span> |
| <span id="L907"><span class="lineNum"> 907</span> :<span class="tlaGNC"> 125 : DBG(" %s found dep (%s)\n", f->name, dep->name);</span></span> |
| <span id="L908"><span class="lineNum"> 908</span> :<span class="tlaGNC"> 125 : dt_property_set_cell(deps, i, dep->phandle);</span></span> |
| <span id="L909"><span class="lineNum"> 909</span> : : </span> |
| <span id="L910"><span class="lineNum"> 910</span> : : /* Advance over the name + delimiter */</span> |
| <span id="L911"><span class="lineNum"> 911</span> :<span class="tlaGNC"> 125 : deps_names += len + 1;</span></span> |
| <span id="L912"><span class="lineNum"> 912</span> : : }</span> |
| <span id="L913"><span class="lineNum"> 913</span> : : }</span> |
| <span id="L914"><span class="lineNum"> 914</span> :<span class="tlaGNC"> 10 : }</span></span> |
| <span id="L915"><span class="lineNum"> 915</span> : : </span> |
| <span id="L916"><span class="lineNum"> 916</span> :<span class="tlaGNC"> 10 : static void add_cpufeatures(struct dt_node *cpus,</span></span> |
| <span id="L917"><span class="lineNum"> 917</span> : : uint32_t cpu_feature_isa, uint32_t cpu_feature_cpu,</span> |
| <span id="L918"><span class="lineNum"> 918</span> : : const char *cpu_name)</span> |
| <span id="L919"><span class="lineNum"> 919</span> : : {</span> |
| <span id="L920"><span class="lineNum"> 920</span> : : struct dt_node *features;</span> |
| <span id="L921"><span class="lineNum"> 921</span> : : int i;</span> |
| <span id="L922"><span class="lineNum"> 922</span> : : </span> |
| <span id="L923"><span class="lineNum"> 923</span> :<span class="tlaGNC"> 10 : DBG("creating cpufeatures for cpu:%d isa:%d\n", cpu_feature_cpu, cpu_feature_isa);</span></span> |
| <span id="L924"><span class="lineNum"> 924</span> : : </span> |
| <span id="L925"><span class="lineNum"> 925</span> :<span class="tlaGNC"> 10 : features = dt_new(cpus, "ibm,powerpc-cpu-features");</span></span> |
| <span id="L926"><span class="lineNum"> 926</span> :<span class="tlaGNC"> 10 : assert(features);</span></span> |
| <span id="L927"><span class="lineNum"> 927</span> : : </span> |
| <span id="L928"><span class="lineNum"> 928</span> :<span class="tlaGNC"> 10 : dt_add_property_cells(features, "isa", cpu_feature_isa);</span></span> |
| <span id="L929"><span class="lineNum"> 929</span> : : </span> |
| <span id="L930"><span class="lineNum"> 930</span> :<span class="tlaGNC"> 10 : dt_add_property_string(features, "device_type", "cpu-features");</span></span> |
| <span id="L931"><span class="lineNum"> 931</span> :<span class="tlaGNC"> 10 : dt_add_property_string(features, "compatible", "ibm,powerpc-cpu-features");</span></span> |
| <span id="L932"><span class="lineNum"> 932</span> :<span class="tlaGNC"> 10 : dt_add_property_string(features, "display-name", cpu_name);</span></span> |
| <span id="L933"><span class="lineNum"> 933</span> : : </span> |
| <span id="L934"><span class="lineNum"> 934</span> : : /* add without dependencies */</span> |
| <span id="L935"><span class="lineNum"> 935</span> :<span class="tlaGNC"> 700 : for (i = 0; i < ARRAY_SIZE(cpu_features_table); i++) {</span></span> |
| <span id="L936"><span class="lineNum"> 936</span> :<span class="tlaGNC"> 690 : const struct cpu_feature *f = &cpu_features_table[i];</span></span> |
| <span id="L937"><span class="lineNum"> 937</span> : : </span> |
| <span id="L938"><span class="lineNum"> 938</span> :<span class="tlaGNC"> 690 : if (f->cpus_supported & cpu_feature_cpu) {</span></span> |
| <span id="L939"><span class="lineNum"> 939</span> :<span class="tlaGNC"> 432 : DBG(" '%s'\n", f->name);</span></span> |
| <span id="L940"><span class="lineNum"> 940</span> :<span class="tlaGNC"> 432 : add_cpu_feature_nodeps(features, f);</span></span> |
| <span id="L941"><span class="lineNum"> 941</span> : : }</span> |
| <span id="L942"><span class="lineNum"> 942</span> : : }</span> |
| <span id="L943"><span class="lineNum"> 943</span> : : </span> |
| <span id="L944"><span class="lineNum"> 944</span> : : /* dependency construction pass */</span> |
| <span id="L945"><span class="lineNum"> 945</span> :<span class="tlaGNC"> 10 : add_cpufeatures_dependencies(features);</span></span> |
| <span id="L946"><span class="lineNum"> 946</span> :<span class="tlaGNC"> 10 : }</span></span> |
| <span id="L947"><span class="lineNum"> 947</span> : : </span> |
| <span id="L948"><span class="lineNum"> 948</span> :<span class="tlaGNC"> 11 : void dt_add_cpufeatures(struct dt_node *root)</span></span> |
| <span id="L949"><span class="lineNum"> 949</span> : : {</span> |
| <span id="L950"><span class="lineNum"> 950</span> : : int version;</span> |
| <span id="L951"><span class="lineNum"> 951</span> :<span class="tlaGNC"> 11 : uint32_t cpu_feature_isa = 0;</span></span> |
| <span id="L952"><span class="lineNum"> 952</span> :<span class="tlaGNC"> 11 : uint32_t cpu_feature_cpu = 0;</span></span> |
| <span id="L953"><span class="lineNum"> 953</span> : : struct dt_node *cpus;</span> |
| <span id="L954"><span class="lineNum"> 954</span> :<span class="tlaGNC"> 11 : const char *cpu_name = NULL;</span></span> |
| <span id="L955"><span class="lineNum"> 955</span> : : </span> |
| <span id="L956"><span class="lineNum"> 956</span> :<span class="tlaGNC"> 11 : version = mfspr(SPR_PVR);</span></span> |
| <span id="L957"><span class="lineNum"> 957</span> :<span class="tlaGNC"> 11 : switch(PVR_TYPE(version)) {</span></span> |
| <span id="L958"><span class="lineNum"> 958</span> :<span class="tlaGNC"> 2 : case PVR_TYPE_P8:</span></span> |
| <span id="L959"><span class="lineNum"> 959</span> :<span class="tlaGNC"> 2 : if (!cpu_name)</span></span> |
| <span id="L960"><span class="lineNum"> 960</span> :<span class="tlaGNC"> 2 : cpu_name = "POWER8";</span></span> |
| <span id="L961"><span class="lineNum"> 961</span> : : /* fallthrough */</span> |
| <span id="L962"><span class="lineNum"> 962</span> : : case PVR_TYPE_P8E:</span> |
| <span id="L963"><span class="lineNum"> 963</span> :<span class="tlaGNC"> 4 : if (!cpu_name)</span></span> |
| <span id="L964"><span class="lineNum"> 964</span> :<span class="tlaGNC"> 2 : cpu_name = "POWER8E";</span></span> |
| <span id="L965"><span class="lineNum"> 965</span> : : /* fallthrough */</span> |
| <span id="L966"><span class="lineNum"> 966</span> :<span class="tlaGNC"> 4 : cpu_feature_isa = ISA_V2_07B;</span></span> |
| <span id="L967"><span class="lineNum"> 967</span> :<span class="tlaGNC"> 4 : if (PVR_VERS_MAJ(version) == 1)</span></span> |
| <span id="L968"><span class="lineNum"> 968</span> :<span class="tlaGNC"> 2 : cpu_feature_cpu = CPU_P8_DD1;</span></span> |
| <span id="L969"><span class="lineNum"> 969</span> : : else</span> |
| <span id="L970"><span class="lineNum"> 970</span> :<span class="tlaGNC"> 2 : cpu_feature_cpu = CPU_P8_DD2;</span></span> |
| <span id="L971"><span class="lineNum"> 971</span> :<span class="tlaGNC"> 4 : break;</span></span> |
| <span id="L972"><span class="lineNum"> 972</span> :<span class="tlaGNC"> 1 : case PVR_TYPE_P8NVL:</span></span> |
| <span id="L973"><span class="lineNum"> 973</span> :<span class="tlaGNC"> 1 : cpu_name = "POWER8NVL";</span></span> |
| <span id="L974"><span class="lineNum"> 974</span> :<span class="tlaGNC"> 1 : cpu_feature_isa = ISA_V2_07B;</span></span> |
| <span id="L975"><span class="lineNum"> 975</span> :<span class="tlaGNC"> 1 : cpu_feature_cpu = CPU_P8_DD2;</span></span> |
| <span id="L976"><span class="lineNum"> 976</span> :<span class="tlaGNC"> 1 : break;</span></span> |
| <span id="L977"><span class="lineNum"> 977</span> :<span class="tlaGNC"> 4 : case PVR_TYPE_P9:</span></span> |
| <span id="L978"><span class="lineNum"> 978</span> :<span class="tlaGNC"> 4 : if (!cpu_name)</span></span> |
| <span id="L979"><span class="lineNum"> 979</span> :<span class="tlaGNC"> 4 : cpu_name = "POWER9";</span></span> |
| <span id="L980"><span class="lineNum"> 980</span> : : </span> |
| <span id="L981"><span class="lineNum"> 981</span> :<span class="tlaGNC"> 4 : cpu_feature_isa = ISA_V3_0B;</span></span> |
| <span id="L982"><span class="lineNum"> 982</span> :<span class="tlaGNC"> 4 : if (is_power9n(version) &&</span></span> |
| <span id="L983"><span class="lineNum"> 983</span> :<span class="tlaGNC"> 4 : (PVR_VERS_MAJ(version) == 2)) {</span></span> |
| <span id="L984"><span class="lineNum"> 984</span> : : /* P9N DD2.x */</span> |
| <span id="L985"><span class="lineNum"> 985</span> :<span class="tlaGNC"> 4 : switch (PVR_VERS_MIN(version)) {</span></span> |
| <span id="L986"><span class="lineNum"> 986</span> :<span class="tlaGNC"> 2 : case 0:</span></span> |
| <span id="L987"><span class="lineNum"> 987</span> : : case 1:</span> |
| <span id="L988"><span class="lineNum"> 988</span> :<span class="tlaGNC"> 2 : cpu_feature_cpu = CPU_P9_DD2_0_1;</span></span> |
| <span id="L989"><span class="lineNum"> 989</span> :<span class="tlaGNC"> 2 : break;</span></span> |
| <span id="L990"><span class="lineNum"> 990</span> :<span class="tlaGNC"> 1 : case 2:</span></span> |
| <span id="L991"><span class="lineNum"> 991</span> :<span class="tlaGNC"> 1 : cpu_feature_cpu = CPU_P9_DD2_2;</span></span> |
| <span id="L992"><span class="lineNum"> 992</span> :<span class="tlaGNC"> 1 : break;</span></span> |
| <span id="L993"><span class="lineNum"> 993</span> :<span class="tlaGNC"> 1 : case 3:</span></span> |
| <span id="L994"><span class="lineNum"> 994</span> :<span class="tlaGNC"> 1 : cpu_feature_cpu = CPU_P9_DD2_3;</span></span> |
| <span id="L995"><span class="lineNum"> 995</span> :<span class="tlaGNC"> 1 : break;</span></span> |
| <span id="L996"><span class="lineNum"> 996</span> :<span class="tlaUNC tlaBgUNC"> 0 : default:</span></span> |
| <span id="L997"><span class="lineNum"> 997</span> :<span class="tlaUNC"> 0 : assert(0);</span></span> |
| <span id="L998"><span class="lineNum"> 998</span> : : }</span> |
| <span id="L999"><span class="lineNum"> 999</span> :<span class="tlaUNC"> 0 : } else if (is_power9c(version) &&</span></span> |
| <span id="L1000"><span class="lineNum"> 1000</span> :<span class="tlaUNC"> 0 : (PVR_VERS_MAJ(version) == 1)) {</span></span> |
| <span id="L1001"><span class="lineNum"> 1001</span> : : /* P9C DD1.x */</span> |
| <span id="L1002"><span class="lineNum"> 1002</span> :<span class="tlaUNC"> 0 : switch (PVR_VERS_MIN(version)) {</span></span> |
| <span id="L1003"><span class="lineNum"> 1003</span> :<span class="tlaUNC"> 0 : case 1:</span></span> |
| <span id="L1004"><span class="lineNum"> 1004</span> : : /* Cumulus DD1.1 => Nimbus DD2.1 */</span> |
| <span id="L1005"><span class="lineNum"> 1005</span> :<span class="tlaUNC"> 0 : cpu_feature_cpu = CPU_P9_DD2_0_1;</span></span> |
| <span id="L1006"><span class="lineNum"> 1006</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L1007"><span class="lineNum"> 1007</span> :<span class="tlaUNC"> 0 : case 2:</span></span> |
| <span id="L1008"><span class="lineNum"> 1008</span> : : /* Cumulus DD1.2 */</span> |
| <span id="L1009"><span class="lineNum"> 1009</span> :<span class="tlaUNC"> 0 : cpu_feature_cpu = CPU_P9_DD2_2;</span></span> |
| <span id="L1010"><span class="lineNum"> 1010</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L1011"><span class="lineNum"> 1011</span> :<span class="tlaUNC"> 0 : case 3:</span></span> |
| <span id="L1012"><span class="lineNum"> 1012</span> : : /* Cumulus DD1.3 */</span> |
| <span id="L1013"><span class="lineNum"> 1013</span> :<span class="tlaUNC"> 0 : cpu_feature_cpu = CPU_P9_DD2_3;</span></span> |
| <span id="L1014"><span class="lineNum"> 1014</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L1015"><span class="lineNum"> 1015</span> :<span class="tlaUNC"> 0 : default:</span></span> |
| <span id="L1016"><span class="lineNum"> 1016</span> :<span class="tlaUNC"> 0 : assert(0);</span></span> |
| <span id="L1017"><span class="lineNum"> 1017</span> : : }</span> |
| <span id="L1018"><span class="lineNum"> 1018</span> : : } else {</span> |
| <span id="L1019"><span class="lineNum"> 1019</span> :<span class="tlaUNC"> 0 : assert(0);</span></span> |
| <span id="L1020"><span class="lineNum"> 1020</span> : : }</span> |
| <span id="L1021"><span class="lineNum"> 1021</span> : : </span> |
| <span id="L1022"><span class="lineNum"> 1022</span> :<span class="tlaGNC tlaBgGNC"> 4 : break;</span></span> |
| <span id="L1023"><span class="lineNum"> 1023</span> :<span class="tlaGNC"> 1 : case PVR_TYPE_P9P:</span></span> |
| <span id="L1024"><span class="lineNum"> 1024</span> :<span class="tlaGNC"> 1 : if (!cpu_name)</span></span> |
| <span id="L1025"><span class="lineNum"> 1025</span> :<span class="tlaGNC"> 1 : cpu_name = "POWER9P";</span></span> |
| <span id="L1026"><span class="lineNum"> 1026</span> : : </span> |
| <span id="L1027"><span class="lineNum"> 1027</span> :<span class="tlaGNC"> 1 : cpu_feature_isa = ISA_V3_0B;</span></span> |
| <span id="L1028"><span class="lineNum"> 1028</span> :<span class="tlaGNC"> 1 : cpu_feature_cpu = CPU_P9P;</span></span> |
| <span id="L1029"><span class="lineNum"> 1029</span> :<span class="tlaGNC"> 1 : break;</span></span> |
| <span id="L1030"><span class="lineNum"> 1030</span> :<span class="tlaUNC tlaBgUNC"> 0 : case PVR_TYPE_P10:</span></span> |
| <span id="L1031"><span class="lineNum"> 1031</span> :<span class="tlaUNC"> 0 : if (!cpu_name)</span></span> |
| <span id="L1032"><span class="lineNum"> 1032</span> :<span class="tlaUNC"> 0 : cpu_name = "POWER10";</span></span> |
| <span id="L1033"><span class="lineNum"> 1033</span> : : </span> |
| <span id="L1034"><span class="lineNum"> 1034</span> :<span class="tlaUNC"> 0 : cpu_feature_isa = ISA_V3_1;</span></span> |
| <span id="L1035"><span class="lineNum"> 1035</span> :<span class="tlaUNC"> 0 : cpu_feature_cpu = CPU_P10;</span></span> |
| <span id="L1036"><span class="lineNum"> 1036</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L1037"><span class="lineNum"> 1037</span> :<span class="tlaUNC"> 0 : case PVR_TYPE_P11:</span></span> |
| <span id="L1038"><span class="lineNum"> 1038</span> :<span class="tlaUNC"> 0 : if (!cpu_name)</span></span> |
| <span id="L1039"><span class="lineNum"> 1039</span> :<span class="tlaUNC"> 0 : cpu_name = "Power11";</span></span> |
| <span id="L1040"><span class="lineNum"> 1040</span> : : </span> |
| <span id="L1041"><span class="lineNum"> 1041</span> :<span class="tlaUNC"> 0 : cpu_feature_isa = ISA_V3_1;</span></span> |
| <span id="L1042"><span class="lineNum"> 1042</span> :<span class="tlaUNC"> 0 : cpu_feature_cpu = CPU_P11;</span></span> |
| <span id="L1043"><span class="lineNum"> 1043</span> :<span class="tlaUNC"> 0 : break;</span></span> |
| <span id="L1044"><span class="lineNum"> 1044</span> :<span class="tlaGNC tlaBgGNC"> 1 : default:</span></span> |
| <span id="L1045"><span class="lineNum"> 1045</span> :<span class="tlaGNC"> 1 : return;</span></span> |
| <span id="L1046"><span class="lineNum"> 1046</span> : : }</span> |
| <span id="L1047"><span class="lineNum"> 1047</span> : : </span> |
| <span id="L1048"><span class="lineNum"> 1048</span> :<span class="tlaGNC"> 10 : cpus = dt_new_check(root, "cpus");</span></span> |
| <span id="L1049"><span class="lineNum"> 1049</span> : : </span> |
| <span id="L1050"><span class="lineNum"> 1050</span> :<span class="tlaGNC"> 10 : add_cpufeatures(cpus, cpu_feature_isa, cpu_feature_cpu, cpu_name);</span></span> |
| <span id="L1051"><span class="lineNum"> 1051</span> : : }</span> |
| </pre> |
| </td> |
| </tr> |
| </table> |
| <br> |
| |
| <table width="100%" border=0 cellspacing=0 cellpadding=0> |
| <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr> |
| <tr><td class="versionInfo">Generated by: <a href="https://github.com//linux-test-project/lcov" target="_parent">LCOV version 2.0-1</a></td></tr> |
| </table> |
| <br> |
| |
| </body> |
| </html> |
