1. c9410a6 RISC-V: Adding XTheadBa ISA extension by Christoph Müllner · 2 years, 1 month ago
  2. 134c3ff RISC-V: Adding XTheadSync ISA extension by Christoph Müllner · 2 years, 1 month ago
  3. 49a7f3a RISC-V: Adding XTheadCmo ISA extension by Christoph Müllner · 2 years, 1 month ago
  4. 26934f9 target/riscv: set tval for triggered watchpoints by Sergey Matyukevich · 2 years, 1 month ago
  5. f008a2d target/riscv: Ensure opcode is saved for all relevant instructions by Anup Patel · 2 years, 1 month ago
  6. ae0edf2 target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX by Anup Patel · 2 years, 1 month ago
  7. 14cb78b target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP by Anup Patel · 2 years, 1 month ago
  8. 2cfb3b6 target/riscv: Update VS timer whenever htimedelta changes by Anup Patel · 2 years, 1 month ago
  9. f251c01 target/riscv: Remove helper_set_rod_rounding_mode by Richard Henderson · 2 years, 1 month ago
  10. 3ceeb19 target/riscv: Introduce helper_set_rounding_mode_chkfrm by Richard Henderson · 2 years, 1 month ago
  11. e471a8c target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 by Andrew Bresticker · 2 years, 2 months ago
  12. 06d85c2 target/riscv: Fix up masking of vsip/vsie accesses by Andrew Bresticker · 2 years, 2 months ago
  13. 877a3a3 target/riscv: Use TARGET_FMT_lx for env->mhartid by Bin Meng · 2 years, 1 month ago
  14. 5ab1095 target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() by Daniel Henrique Barboza · 2 years, 1 month ago
  15. c66ffcd target/riscv/cpu: set cpu->cfg in register_cpu_props() by Daniel Henrique Barboza · 2 years, 1 month ago
  16. 44e7372 target/riscv/cpu.c: Fix elen check by Dongxue Zhang · 2 years, 2 months ago
  17. 1237c2d hw/char: riscv_htif: Move registers from CPUArchState to HTIFState by Bin Meng · 2 years, 2 months ago
  18. 883f2c5 bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx by Philippe Mathieu-Daudé · 2 years, 1 month ago
  19. 052e653 Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging by Peter Maydell · 2 years, 1 month ago
  20. 260b594 RISC-V: Add Zawrs ISA extension support by Christoph Muellner · 2 years, 5 months ago
  21. 0ff430a target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ by Bin Meng · 2 years, 2 months ago
  22. 2bfec53 target/riscv: Simplify helper_sret() a little bit by Bin Meng · 2 years, 2 months ago
  23. ec2918b target/riscv: Set pc_succ_insn for !rvc illegal insn by Richard Henderson · 2 years, 3 months ago
  24. 4c48aad target/riscv: Fix mret exception cause when no pmp rule is configured by Bin Meng · 2 years, 2 months ago
  25. bc7dca1 target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() by Bin Meng · 2 years, 3 months ago
  26. eacd03c target/riscv: support cache-related PMU events in virtual mode by Jim Shu · 2 years, 3 months ago
  27. 6535a44 target/riscv: Typo fix in sstc() predicate by Anup Patel · 2 years, 3 months ago
  28. 577f028 target/riscv: Add itrigger_enabled field to CPURISCVState by LIU Zhiwei · 2 years, 4 months ago
  29. 9180959 target/riscv: Enable native debug itrigger by LIU Zhiwei · 2 years, 4 months ago
  30. 5a4ae64 target/riscv: Add itrigger support when icount is enabled by LIU Zhiwei · 2 years, 4 months ago
  31. 2c9d747 target/riscv: Add itrigger support when icount is not enabled by LIU Zhiwei · 2 years, 4 months ago
  32. fb3f373 target/riscv: generate virtual instruction exception by Mayuresh Chitale · 2 years, 4 months ago
  33. 252b06f target/riscv: smstateen check for h/s/envcfg by Mayuresh Chitale · 2 years, 4 months ago
  34. 3bee0e4 target/riscv: Add smstateen support by Mayuresh Chitale · 2 years, 4 months ago
  35. 824cac6 target/riscv: Fix PMP propagation for tlb by LIU Zhiwei · 2 years, 4 months ago
  36. b3eb5b8 target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip by Richard Henderson · 2 years, 3 months ago
  37. 4fa485a target/riscv: Convert to 3-phase reset by Peter Maydell · 2 years, 3 months ago
  38. 66997c4 cleanup: Tweak and re-run return_directly.cocci by Markus Armbruster · 2 years, 3 months ago
  39. 08a5d04 Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging by Stefan Hajnoczi · 2 years, 4 months ago
  40. ad1e84f target/riscv: Convert to tcg_ops restore_state_to_opc by Richard Henderson · 2 years, 4 months ago
  41. c1dadb8 treewide: Remove the unnecessary space before semicolon by Bin Meng · 2 years, 4 months ago
  42. 4756642 target/riscv: pmp: Fixup TLB size calculation by Alistair Francis · 2 years, 4 months ago
  43. bb76f8e Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging by Stefan Hajnoczi · 2 years, 4 months ago
  44. 3dba0a3 kvm: allow target-specific accelerator properties by Paolo Bonzini · 2 years, 5 months ago
  45. 1af0006 dump: Replace opaque DumpState pointer with a typed one by Janosch Frank · 2 years, 6 months ago
  46. fbf59aa accel/tcg: Introduce tb_pc and log_pc by Richard Henderson · 2 years, 6 months ago
  47. e4fdf9d hw/core: Add CPUClass.get_pc by Richard Henderson · 2 years, 5 months ago
  48. a3ab69f target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered by Yang Liu · 2 years, 6 months ago
  49. 5bda21c target/riscv: rvv-1.0: Simplify vfwredsum code by Yang Liu · 2 years, 6 months ago
  50. c472c14 target/riscv: debug: Add initial support of type 6 trigger by Frank Chang · 2 years, 5 months ago
  51. c32461d target/riscv: debug: Check VU/VS modes for type 2 trigger by Frank Chang · 2 years, 5 months ago
  52. d1c1114 target/riscv: debug: Create common trigger actions function by Frank Chang · 2 years, 5 months ago
  53. 31b9798 target/riscv: debug: Introduce tinfo CSR by Frank Chang · 2 years, 5 months ago
  54. 6ea8d3f target/riscv: debug: Restrict the range of tselect value can be written by Frank Chang · 2 years, 5 months ago
  55. 9495c48 target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs by Frank Chang · 2 years, 5 months ago
  56. 9d5a84d target/riscv: debug: Introduce build_tdata1() to build tdata1 register content by Frank Chang · 2 years, 5 months ago
  57. a42bd00 target/riscv: debug: Determine the trigger type from tdata1.type by Frank Chang · 2 years, 5 months ago
  58. 9e37653 target/riscv: Check the correct exception cause in vector GDB stub by Frank Chang · 2 years, 5 months ago
  59. 277b210 target/riscv: Set the CPU resetvec directly by Alistair Francis · 2 years, 5 months ago
  60. 94452ac target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml by Andrew Burgess · 2 years, 6 months ago
  61. a412829 target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} by Weiwei Li · 2 years, 6 months ago
  62. 513eb43 target/riscv: Remove sideleg and sedeleg by Rahul Pathak · 2 years, 6 months ago
  63. 7d7fb11 target/riscv: Honour -semihosting-config userspace=on and enable=on by Peter Maydell · 2 years, 6 months ago
  64. f055156 target/riscv: Update the privilege field for sscofpmf CSRs by Atish Patra · 2 years, 6 months ago
  65. abd9a20 hw/riscv: virt: Add PMU DT node to the device tree by Atish Patra · 2 years, 6 months ago
  66. 892320f target/riscv: Add few cache related PMU events by Atish Patra · 2 years, 6 months ago
  67. ade445e target/riscv: Simplify counter predicate function by Atish Patra · 2 years, 6 months ago
  68. 1466448 target/riscv: Add sscofpmf extension support by Atish Patra · 2 years, 6 months ago
  69. 3ec0fe1 target/riscv: Add vstimecmp support by Atish Patra · 2 years, 6 months ago
  70. 43888c2 target/riscv: Add stimecmp support by Atish Patra · 2 years, 6 months ago
  71. 7cbcc53 hw/intc: Move mtimer/mtimecmp to aclint by Atish Patra · 2 years, 6 months ago
  72. dc9acc9 target/riscv: Use official extension names for AIA CSRs by Anup Patel · 2 years, 6 months ago
  73. e0dea2f target/riscv: Add xicondops in ISA entry by Rahul Pathak · 2 years, 6 months ago
  74. 240b363 target/riscv: Remove additional priv version check for mcountinhibit by Atish Patra · 2 years, 6 months ago
  75. eacaf44 target/riscv: Fix priority of csr related check in riscv_csrrw_check by Weiwei Li · 2 years, 7 months ago
  76. 4696f0a target/riscv: Add Zihintpause support by Dao Lu · 2 years, 7 months ago
  77. 1ad3f9b target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior by eopXD · 2 years, 8 months ago
  78. edabcd0 target/riscv: rvv: Add mask agnostic for vector permutation instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  79. 35f2d79 target/riscv: rvv: Add mask agnostic for vector mask instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  80. 5b448f4 target/riscv: rvv: Add mask agnostic for vector floating-point instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  81. 72e17a9 target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  82. 6e11d7e target/riscv: rvv: Add mask agnostic for vector integer comparison instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  83. fd93045 target/riscv: rvv: Add mask agnostic for vector integer shift instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  84. bce9a63 target/riscv: rvv: Add mask agnostic for vx instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  85. 265ecd4 target/riscv: rvv: Add mask agnostic for vector load / store instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  86. 355d558 target/riscv: rvv: Add mask agnostic for vv instructions by Yueh-Ting (eop) Chen · 2 years, 8 months ago
  87. dec19f6 target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V by Alexey Baturo · 2 years, 7 months ago
  88. 5de1245 target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check by Weiwei Li · 2 years, 7 months ago
  89. 62a09b9 target/riscv: Fix checks in hmode/hmode32 by Weiwei Li · 2 years, 7 months ago
  90. c126f83 target/riscv: Add check for csrs existed with U extension by Weiwei Li · 2 years, 7 months ago
  91. 108c4f2 target/riscv: Fix checkpatch warning may triggered in csr_ops table by Weiwei Li · 2 years, 7 months ago
  92. 756b037 target/riscv: H extension depends on I extension by Weiwei Li · 2 years, 7 months ago
  93. 0b572c8 target/riscv: Add check for supported privilege mode combinations by Weiwei Li · 2 years, 7 months ago
  94. 6d00ffa target/riscv: move zmmul out of the experimental properties by Weiwei Li · 2 years, 7 months ago
  95. 3363277 target/riscv: fix shifts shamt value for rv128c by Frédéric Pétrot · 2 years, 7 months ago
  96. 9a1f054 target/riscv: Force disable extensions if priv spec version does not match by Anup Patel · 2 years, 8 months ago
  97. 8e2aa21 target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() by Anup Patel · 2 years, 8 months ago
  98. 00c0734 target/riscv: Make translator stop before the end of a page by Richard Henderson · 2 years, 6 months ago
  99. ef6e987 target/riscv: Add MAX_INSN_LEN and insn_len by Richard Henderson · 2 years, 6 months ago
  100. 306c872 accel/tcg: Add pc and host_pc params to gen_intermediate_code by Richard Henderson · 2 years, 6 months ago