43888c2f1823212b1064a6a94d65d8acaf954478 - qemu

commit	43888c2f1823212b1064a6a94d65d8acaf954478	[log] [tgz]
author	Atish Patra <atishp@rivosinc.com>	Wed Aug 24 15:13:56 2022 -0700
committer	Alistair Francis <alistair.francis@wdc.com>	Wed Sep 07 09:19:15 2022 +0200
tree	f9cccb009819382f3133fe9a2516f3420fc9acb4
parent	7cbcc538f4b3040db1e39a6547efa501a8a44907 [diff]

target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/cpu.c[diff]
target/riscv/cpu.h[diff]
target/riscv/cpu_bits.h[diff]
target/riscv/csr.c[diff]
target/riscv/machine.c[diff]
target/riscv/meson.build[diff]
target/riscv/time_helper.c[Added - diff]
target/riscv/time_helper.h[Added - diff]

8 files changed

tree: f9cccb009819382f3133fe9a2516f3420fc9acb4