tree f9cccb009819382f3133fe9a2516f3420fc9acb4
parent 7cbcc538f4b3040db1e39a6547efa501a8a44907
author Atish Patra <atishp@rivosinc.com> 1661379236 -0700
committer Alistair Francis <alistair.francis@wdc.com> 1662535155 +0200

target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>