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qemu
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547db24a17c22c47f762aae3a0a6f518f574e7f2
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target
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riscv
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translate.c
d77c340
RISC-V: Add misa.MAFD checks to translate
by Michael Clark
· 6 years ago
db9f3fd
RISC-V: Add misa to DisasContext
by Michael Clark
· 6 years ago
d75377b
RISC-V: Add priv_ver to DisasContext
by Alistair Francis
· 6 years ago
533b8f8
RISC-V: Mark mstatus.fs dirty
by Richard Henderson
· 6 years ago
83a7171
RISC-V: Split out mstatus_fs from tb_flags
by Richard Henderson
· 6 years ago
3502dc8
RISC-V: Respect fences for user-only emulators
by Palmer Dabbelt
· 6 years ago
6573777
target/riscv: Fix sfence.vm/a both available in any priv version
by Bastian Koppelmann
· 6 years ago
40cf6a5
target/riscv: Fix FCLASS_D being treated as RV64 only
by Bastian Koppelmann
· 6 years ago
ccf08e4
target/riscv: call gen_goto_tb on DISAS_TOO_MANY
by Emilio G. Cota
· 7 years ago
3070543
target/riscv: optimize indirect branches
by Emilio G. Cota
· 7 years ago
6dbebd5
target/riscv: optimize cross-page direct jumps in softmmu
by Emilio G. Cota
· 7 years ago
07ea28b
tcg: Pass tb and index to tcg_gen_exit_tb separately
by Richard Henderson
· 7 years ago
f5583c5
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging
by Peter Maydell
· 7 years ago
3e281df
target/riscv: Use new atomic min/max expanders
by Richard Henderson
· 7 years ago
5b4f1d2
target/riscv: convert to TranslatorOps
by Emilio G. Cota
· 7 years ago
0114db1
target/riscv: convert to DisasContextBase
by Emilio G. Cota
· 7 years ago
b2e3202
target/riscv: convert to DisasJumpType
by Emilio G. Cota
· 7 years ago
3357226
target/riscv: avoid integer overflow in next_page PC check
by Emilio G. Cota
· 7 years ago
6fce529
RISC-V: Add mcycle/minstret support for -icount auto
by Michael Clark
· 7 years ago
8d196c4
RISC-V: Remove erroneous comment from translate.c
by Michael Clark
· 7 years ago
55c2a12
RISC-V TCG Code Generation
by Michael Clark
· 7 years ago