commit | db9f3fd69d5bccfd25f84d5cec805308406b7b8f | [log] [tgz] |
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author | Michael Clark <mjc@sifive.com> | Mon Jan 14 23:58:42 2019 +0000 |
committer | Palmer Dabbelt <palmer@sifive.com> | Mon Feb 11 15:56:22 2019 -0800 |
tree | cee5f026997c7f3a4b9537d2dc846bbb86e4149d | |
parent | d75377bf7bffc21f3d2b4779d8121ccab349d335 [diff] |
RISC-V: Add misa to DisasContext gen methods should access state from DisasContext. Add misa field to the DisasContext struct and remove CPURISCVState argument from all gen methods. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>