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52e60cdd342dc48116edb81b443ba8c0a0c6f1a3
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target-arm
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cpu.h
a65f1de
target-arm: Implement AArch64 SPSR_EL1
by Peter Maydell
· 11 years ago
f502cfc
target-arm: Implement SP_EL0, SP_EL1
by Peter Maydell
· 11 years ago
a0618a1
target-arm: Add AArch64 ELR_EL1 register.
by Peter Maydell
· 11 years ago
6cd8a26
target-arm: Implement AArch64 views of fault status and data registers
by Rob Herring
· 11 years ago
7e09797
target-arm: Use dedicated CPU state fields for ARM946 access bit registers
by Peter Maydell
· 11 years ago
aca3f40
target-arm: A64: Implement DC ZVA
by Peter Maydell
· 11 years ago
2c7ffc4
target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
by Peter Maydell
· 11 years ago
8c6afa6
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
by Peter Maydell
· 11 years ago
abf1172
target-arm: Define exception record for AArch64 exceptions
by Peter Maydell
· 11 years ago
c2b820f
target-arm: Implement AArch64 DAIF system register
by Peter Maydell
· 11 years ago
ccd3808
target-arm: Split out private-to-target functions into internals.h
by Peter Maydell
· 11 years ago
7510454
cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
by Andreas Färber
· 11 years ago
8c2e1b0
cpu: Turn cpu_has_work() into a CPUClass hook
by Andreas Färber
· 11 years ago
7c2cb42
target-arm: Implements the ARM PMCCNTR register
by Alistair Francis
· 11 years ago
eb0ecd5
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
by Will Newton
· 11 years ago
1f79ee3
target-arm: Add utility function for checking AA32/64 state of an EL
by Peter Maydell
· 11 years ago
34222fb
target-arm: Implement AArch64 view of CPACR
by Peter Maydell
· 11 years ago
4cc3561
target-arm: Store AIF bits in env->pstate for AArch32
by Peter Maydell
· 11 years ago
d9ea7d2
target-arm: Get MMU index information correct for A64 code
by Peter Maydell
· 11 years ago
0b45451
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
by Peter Maydell
· 11 years ago
a7adc4b
target-arm: Implement AArch64 generic timers
by Peter Maydell
· 11 years ago
327ed10
target-arm: Implement AArch64 TTBR*
by Peter Maydell
· 11 years ago
a505d7f
target-arm: Implement AArch64 VBAR_EL1
by Peter Maydell
· 11 years ago
cb2e37d
target-arm: Implement AArch64 TCR_EL1
by Peter Maydell
· 11 years ago
5ebafdf
target-arm: Implement AArch64 SCTLR_EL1
by Peter Maydell
· 11 years ago
b0fe242
target-arm: Implement AArch64 memory attribute registers
by Peter Maydell
· 11 years ago
0eef9d9
target-arm: Implement AArch64 CurrentEL sysreg
by Peter Maydell
· 11 years ago
7da845b
target-arm: A64: Make cache ID registers visible to AArch64
by Peter Maydell
· 11 years ago
67ed771
target-arm: Fix raw read and write functions on AArch64 registers
by Peter Maydell
· 11 years ago
c4241c7
target-arm: Drop success/fail return from cpreg read and write functions
by Peter Maydell
· 11 years ago
f59df3f
target-arm: Split cpreg access checks out from read/write functions
by Peter Maydell
· 11 years ago
1456364
target-arm: Remove unused ARMCPUState sr substruct
by Peter Maydell
· 11 years ago
76e3e1b
target-arm: Define names for SCTLR bits
by Peter Maydell
· 11 years ago
9972da6
target-arm: Move arm_rmode_to_sf to a shared location.
by Will Newton
· 11 years ago
5cd8a11
arm: fix compile on bigendian host
by Alexey Kardashevskiy
· 11 years ago
4d3da0f
target-arm: Give the FPSCR rounding modes names
by Alexander Graf
· 11 years ago
03d05e2
target-arm: Widen exclusive-access support struct fields to 64 bits
by Peter Maydell
· 11 years ago
e4fe830
target-arm: Widen thread-local register state fields to 64 bits
by Peter Maydell
· 11 years ago
b0d2b7d
target-arm: A64: Implement minimal set of EL0-visible sysregs
by Peter Maydell
· 11 years ago
60322b3
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
by Peter Maydell
· 11 years ago
f5a0a5a
target-arm: Update generic cpreg code for AArch64
by Peter Maydell
· 11 years ago
f903fa2
target-arm: A64: provide functions for accessing FPCR and FPSR
by Peter Maydell
· 11 years ago
d356312
target-arm: Clean up handling of AArch64 PSTATE
by Peter Maydell
· 11 years ago
d8ba780
target-arm: Define and use ARM_FEATURE_CBAR
by Peter Crosthwaite
· 11 years ago
9d93550
target-arm: add support for v8 AES instructions
by Ard Biesheuvel
· 11 years ago
72b0cd3
target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM
by Peter Maydell
· 11 years ago
8641136
target-arm: Add CP15 VBAR support
by Nathan Rossi
· 11 years ago
3926cc8
target-arm: Prepare translation for AArch64 code
by Alexander Graf
· 11 years ago
0a2461f
target-arm: Fix target_ulong/uint32_t confusions
by Alexander Graf
· 11 years ago
78dbbbe
target-arm: Avoid "1 << 31" undefined behaviour
by Peter Maydell
· 11 years ago
55d284a
target-arm: Implement the generic timer
by Peter Maydell
· 11 years ago
2452731
target-arm: Support coprocessor registers which do I/O
by Peter Maydell
· 11 years ago
7c1840b
target-arm: Make IRQ and FIQ gpio lines on the CPU object
by Peter Maydell
· 11 years ago
bdf7ae5
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
by Andreas Färber
· 12 years ago
81e69fb
target-arm: add feature flag for ARMv8
by Mans Rullgard
· 12 years ago
6291ad7
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
by Peter Maydell
· 12 years ago
721fae1
target-arm: Convert TCG to using (index,value) list for cp migration
by Peter Maydell
· 12 years ago
7023ec7
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
by Peter Maydell
· 12 years ago
34affee
target-arm: Allow special cpregs to have flags set
by Peter Maydell
· 12 years ago
3cc1d20
target-arm: port ARM CPU save/load to use VMState
by Juan Quintela
· 12 years ago
97a8ea5
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
by Andreas Färber
· 12 years ago
259186a
cpu: Move halted and interrupt_request fields to CPUState
by Andreas Färber
· 12 years ago
494b00c
ARM: KVM: Add support for KVM on ARM architecture
by Christoffer Dall
· 12 years ago
1496926
target-arm: Update ARMCPU to QOM realizefn
by Andreas Färber
· 12 years ago
6b4c305
fpu: move public header file to include/fpu
by Paolo Bonzini
· 12 years ago
022c62c
exec: move include files to include/exec/
by Paolo Bonzini
· 12 years ago
3993c6b
cpus: Pass CPUState to [qemu_]cpu_has_work()
by Andreas Färber
· 13 years ago
1273d9c
target-arm: Drop unused DECODE_CPREG_CRN macro
by Peter Maydell
· 12 years ago
d31dd73
target-arm: final conversion to AREG0 free mode
by Blue Swirl
· 12 years ago
b90372a
target-arm: Fix typos in comments
by Peter Maydell
· 12 years ago
891a2fe
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
by Peter Maydell
· 13 years ago
918f5dc
target-arm: Extend feature flags to 64 bits
by Peter Maydell
· 13 years ago
de9b05b
target-arm: Implement privileged-execute-never (PXN)
by Peter Maydell
· 13 years ago
3cc0cd6
ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
by Peter Maydell
· 13 years ago
b2d06f9
target-arm: Remove ARM_CPUID_* macros
by Peter Maydell
· 13 years ago
b22af02
target-arm: Remove c0_cachetype CPUARMState field
by Peter Maydell
· 13 years ago
81bdde9
target-arm: Convert MPIDR
by Peter Maydell
· 13 years ago
776d4e5
target-arm: Convert cp15 cache ID registers
by Peter Maydell
· 13 years ago
8515a09
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
by Peter Maydell
· 13 years ago
c480421
target-arm: convert cp15 crn=7 registers
by Peter Maydell
· 13 years ago
1047b9d
target-arm: Convert cp15 crn=15 registers
by Peter Maydell
· 13 years ago
e8070a2
target-arm: Remove old cpu_arm_set_cp_io infrastructure
by Peter Maydell
· 13 years ago
4b6a83f
target-arm: initial coprocessor register framework
by Peter Maydell
· 13 years ago
ad37ad5
target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL
by Peter Maydell
· 13 years ago
778c3a0
target-arm: Change cpu_arm_init() return type to ARMCPU
by Andreas Färber
· 13 years ago
581be09
target-arm: Move feature bit settings to CPU init fns
by Peter Maydell
· 13 years ago
ce854d7
target-arm: remind to keep arm features in sync with linux-user/elfload.c
by Benoit Canet
· 13 years ago
d8fd295
Userspace ARM BE8 support
by Paul Brook
· 13 years ago
06ed5d6
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
by Andrew Towers
· 13 years ago
dec9c2d
target-arm: Minimalistic CPU QOM'ification
by Andreas Färber
· 13 years ago
0bcd08b
target-arm: Drop cpu_arm_close()
by Andreas Färber
· 13 years ago
9349b4f
Rename CPUState -> CPUArchState
by Andreas Färber
· 13 years ago
0ecb72a
target-arm: Don't overuse CPUState
by Andreas Färber
· 13 years ago
0b03bdf
Add Cortex-A15 CPU definition
by Peter Maydell
· 13 years ago
0383ac0
Add dummy implementation of generic timer cp15 registers
by Peter Maydell
· 13 years ago
2be2762
arm: Add dummy support for co-processor 15's secure config register
by Rob Herring
· 13 years ago
7da362d
arm: add dummy A9-specific cp15 registers
by Mark Langsdorf
· 13 years ago
da97f52
target-arm: Implement VFPv4 fused multiply-accumulate insns
by Peter Maydell
· 13 years ago
b8b8ea0
target-arm: Add ARM UDIV/SDIV support
by Peter Maydell
· 13 years ago
4778999
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
by Peter Maydell
· 13 years ago
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