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target-arm
2ef6175
tcg: Invert the inclusion of helper.h
by Richard Henderson
· 11 years ago
a1ba125
target-arm: A64: Register VBAR_EL3
by Edgar E. Iglesias
· 11 years ago
d42e3c2
target-arm: A64: Register VBAR_EL2
by Edgar E. Iglesias
· 11 years ago
855ea66
target-arm: Make vbar_write writeback to any CPREG
by Edgar E. Iglesias
· 11 years ago
61d4b21
target-arm: A64: Generalize update_spsel for the various ELs
by Edgar E. Iglesias
· 11 years ago
db6c3cd
target-arm: A64: Generalize ERET to various ELs
by Edgar E. Iglesias
· 11 years ago
14c521d
target-arm: A64: Trap ERET from EL0 at translation time
by Edgar E. Iglesias
· 11 years ago
7ab6c10
target-arm: A64: Forbid ERET to higher or unimplemented ELs
by Edgar E. Iglesias
· 11 years ago
81547d6
target-arm: Register EL3 versions of ELR and SPSR
by Edgar E. Iglesias
· 11 years ago
3b685ba
target-arm: Register EL2 versions of ELR and SPSR
by Edgar E. Iglesias
· 11 years ago
1fe8141
target-arm: Add a feature flag for EL3
by Edgar E. Iglesias
· 11 years ago
cca7c2f
target-arm: Add a feature flag for EL2
by Edgar E. Iglesias
· 11 years ago
2a923c4
target-arm: A64: Introduce aarch64_banked_spsr_index()
by Edgar E. Iglesias
· 11 years ago
28c9457
target-arm: Add SPSR entries for EL2/HYP and EL3/MON
by Edgar E. Iglesias
· 11 years ago
1b17423
target-arm: A64: Add ELR entries for EL2 and 3
by Edgar E. Iglesias
· 11 years ago
73fb3b7
target-arm: A64: Add SP entries for EL2 and 3
by Edgar E. Iglesias
· 11 years ago
68fdb6c
target-arm: c12_vbar -> vbar_el[]
by Edgar E. Iglesias
· 11 years ago
d81c519
target-arm: Make esr_el1 an array
by Edgar E. Iglesias
· 11 years ago
6947f05
target-arm: Make elr_el1 an array
by Edgar E. Iglesias
· 11 years ago
f79fbf3
target-arm: Use a 1:1 mapping between EL and MMU index
by Edgar E. Iglesias
· 11 years ago
6ce2faf
target-arm: A32: Use get_mem_index for load/stores
by Edgar E. Iglesias
· 11 years ago
c119779
target-arm/translate.c: Use get_mem_index() for SRS memory accesses
by Peter Maydell
· 11 years ago
a99caa4
target-arm/translate.c: Clean up mmu index handling for ldrt/strt
by Peter Maydell
· 11 years ago
9d4c4e8
target-arm: Move get_mem_index to translate.h
by Edgar E. Iglesias
· 11 years ago
f0aff25
target-arm: implement CPACR register logic for ARMv7
by Fabian Aggeler
· 11 years ago
00d0f7c
target-arm: Fix segfault on startup when KVM enabled
by Christoffer Dall
· 11 years ago
6b7aa99
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging
by Peter Maydell
· 11 years ago
2f0d863
target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged
by Peter Maydell
· 11 years ago
8f1e884
savevm: Remove all the unneeded version_minimum_id_old (arm)
by Juan Quintela
· 11 years ago
50a2c6e
kvm: reset state from the CPU's reset method
by Paolo Bonzini
· 12 years ago
3476436
vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/
by Michael S. Tsirkin
· 11 years ago
37f0806
target-arm: Correct a comment refering to EL0
by Edgar E. Iglesias
· 11 years ago
6ab9f49
target-arm: A64: Fix a typo when declaring TLBI ops
by Edgar E. Iglesias
· 11 years ago
1b505f9
target-arm: A64: Handle blr lr
by Edgar E. Iglesias
· 11 years ago
fed3ffb
target-arm: Make vbar_write 64bit friendly on 32bit hosts
by Edgar E. Iglesias
· 11 years ago
252ec40
target-arm: implement WFE/YIELD as a yield for AArch64
by Rob Herring
· 11 years ago
3b77157
target-arm: Implement XScale cache lockdown operations as NOPs
by Peter Maydell
· 11 years ago
e44a90c
target-arm: A64: fix unallocated test of scalar SQXTUN
by Alex Bennée
· 11 years ago
33bbd75
arm: translate.c: Fix smlald Instruction
by Peter Crosthwaite
· 11 years ago
b5cde1d
target-arm/gdbstub64.c: remove useless 'break' statement.
by Chen Gang
· 11 years ago
1773111
target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
by Peter Maydell
· 11 years ago
7633378
target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
by Peter Maydell
· 11 years ago
c29f9a0
target-arm: Make Cortex-A15 CBAR read-only
by Peter Maydell
· 11 years ago
f318cec
target-arm: Implement CBAR for Cortex-A57
by Peter Maydell
· 11 years ago
377a44e
target-arm: Implement Cortex-A57 implementation-defined system registers
by Peter Maydell
· 11 years ago
3933443
target-arm: Implement RVBAR register
by Peter Maydell
· 11 years ago
1952552
target-arm: Implement AArch64 address translation operations
by Peter Maydell
· 11 years ago
f32cdad
target-arm: Implement auxiliary fault status registers
by Peter Maydell
· 11 years ago
9449fdf
target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8
by Peter Maydell
· 11 years ago
00a29f3
target-arm: Don't expose wildcard ID register definitions for ARMv8
by Peter Maydell
· 11 years ago
85acfa9
target-arm: Remove THUMB2EE feature from AArch64 'any' CPU
by Peter Maydell
· 11 years ago
1090b9c
target-arm: Implement ISR_EL1 register
by Peter Maydell
· 11 years ago
2eef0bf
target-arm: Implement AArch64 view of ACTLR
by Peter Maydell
· 11 years ago
014406b
target-arm: Implement AArch64 view of CONTEXTIDR
by Peter Maydell
· 11 years ago
0ff644a
target-arm: Implement AArch64 views of AArch32 ID registers
by Peter Maydell
· 11 years ago
cb1fa94
target-arm: Add Cortex-A57 processor
by Peter Maydell
· 11 years ago
a50c0f5
target-arm: Implement ARMv8 MVFR registers
by Peter Maydell
· 11 years ago
52e60cd
target-arm: Implement AArch64 EL1 exception handling
by Rob Herring
· 11 years ago
2f2a00a
target-arm: Move arm_log_exception() into internals.h
by Peter Maydell
· 11 years ago
a65f1de
target-arm: Implement AArch64 SPSR_EL1
by Peter Maydell
· 11 years ago
f502cfc
target-arm: Implement SP_EL0, SP_EL1
by Peter Maydell
· 11 years ago
a0618a1
target-arm: Add AArch64 ELR_EL1 register.
by Peter Maydell
· 11 years ago
6cd8a26
target-arm: Implement AArch64 views of fault status and data registers
by Rob Herring
· 11 years ago
7e09797
target-arm: Use dedicated CPU state fields for ARM946 access bit registers
by Peter Maydell
· 11 years ago
aca3f40
target-arm: A64: Implement DC ZVA
by Peter Maydell
· 11 years ago
9225d73
target-arm: Don't mention PMU in debug feature register
by Peter Maydell
· 11 years ago
2c8dd31
target-arm: Add v8 mmu translation support
by Rob Herring
· 11 years ago
2c7ffc4
target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
by Peter Maydell
· 11 years ago
90e4963
target-arm: A64: Add assertion that FP access was checked
by Peter Maydell
· 11 years ago
8c6afa6
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
by Peter Maydell
· 11 years ago
0089238
target-arm: Provide syndrome information for MMU faults
by Rob Herring
· 11 years ago
d4a2dc6
target-arm: Add support for generating exceptions with syndrome information
by Peter Maydell
· 11 years ago
8bcbf37
target-arm: Provide correct syndrome information for cpreg access traps
by Peter Maydell
· 11 years ago
abf1172
target-arm: Define exception record for AArch64 exceptions
by Peter Maydell
· 11 years ago
c2b820f
target-arm: Implement AArch64 DAIF system register
by Peter Maydell
· 11 years ago
ccd3808
target-arm: Split out private-to-target functions into internals.h
by Peter Maydell
· 11 years ago
6df05bd
target-arm: Add missing 'static' attribute
by Stefan Weil
· 11 years ago
d108609
target-arm: Fix A64 Neon MLS
by Peter Maydell
· 11 years ago
09e0373
target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
by Alex Bennée
· 11 years ago
0a79bc8
target-arm: A64: Add saturating int ops (SQNEG/SQABS)
by Alex Bennée
· 11 years ago
c2fb418
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
by Alex Bennée
· 11 years ago
5553955
target-arm: A64: Implement FCVTXN
by Peter Maydell
· 11 years ago
5201c13
target-arm: A64: Implement scalar saturating narrow ops
by Alex Bennée
· 11 years ago
8b092ca
target-arm: A64: Move handle_2misc_narrow function
by Alex Bennée
· 11 years ago
b6d4443
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
by Alex Bennée
· 11 years ago
2ed3ea1
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
by Peter Maydell
· 11 years ago
a847f32
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
by Peter Maydell
· 11 years ago
03df01e
target-arm: A64: Implement FRINT*
by Peter Maydell
· 11 years ago
37a706a
target-arm: A64: Implement SRI
by Peter Maydell
· 11 years ago
8f0c675
target-arm: A64: Add FRECPX (reciprocal exponent)
by Alex Bennée
· 11 years ago
a566da1
target-arm: A64: List unsupported shift-imm opcodes
by Peter Maydell
· 11 years ago
931c8cc
target-arm: A64: Implement FCVTL
by Peter Maydell
· 11 years ago
261a5b4
target-arm: A64: Implement FCVTN
by Peter Maydell
· 11 years ago
04c7c6c
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
by Peter Maydell
· 11 years ago
73a81d1
target-arm: A64: Implement SHLL, SHLL2
by Peter Maydell
· 11 years ago
6781fa1
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
by Peter Maydell
· 11 years ago
c1b876b
target-arm: A64: Saturating and narrowing shift ops
by Alex Bennée
· 11 years ago
b05c306
target-arm: A64: Add remaining CLS/Z vector ops
by Alex Bennée
· 11 years ago
f612537
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
by Alex Bennée
· 11 years ago
10113b6
target-arm: A64: Add last AdvSIMD Integer to FP ops
by Alex Bennée
· 11 years ago
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