Google Git
Sign in
qemu / qemu / 42a268c241183877192c376d03bd9b6d527407c7 / target-mips / translate.c
  1. 42a268c tcg: Change translator-side labels to a pointer by Richard Henderson · 10 years ago
  2. 5e88759 target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction by Leon Alrae · 10 years ago
  3. d3b1979 target-mips: use CP0EnLo_XI instead of magic number by Leon Alrae · 10 years ago
  4. fe23729 target-mips: fix detection of the end of the page during translation by Leon Alrae · 10 years ago
  5. fe700ad tcg: Introduce tcg_op_buf_count and tcg_op_buf_full by Richard Henderson · 11 years ago
  6. 0a7df5d tcg: Move emit of INDEX_op_end into gen_tb_end by Richard Henderson · 11 years ago
  7. b6f3b23 target-mips: Clean up switch fall through after commit fecd264 by Markus Armbruster · 10 years ago
  8. cd42d5b gen-icount: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
  9. bd79255 translate: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
  10. 00fb4a1 target-mips: convert single case switch into if statement by Leon Alrae · 10 years ago
  11. 66991d1 target-mips: Fix DisasContext's ulri member initialization by Maciej W. Rozycki · 10 years ago
  12. bb962386 target-mips: Add missing calls to synchronise SoftFloat status by Maciej W. Rozycki · 10 years ago
  13. c48245f target-mips: Correct 32-bit address space wrapping by Maciej W. Rozycki · 10 years ago
  14. d922445 target-mips: Tighten ISA level checks by Maciej W. Rozycki · 10 years ago
  15. 90f12d7 target-mips: Fix CP0.Config3.ISAOnExc write accesses by Maciej W. Rozycki · 10 years ago
  16. 27e1fb1 target-mips: Output CP0.Config2-5 in the register dump by Maciej W. Rozycki · 10 years ago
  17. 7215d7e target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP by Maciej W. Rozycki · 10 years ago
  18. c357747 target-mips: Correct MIPS16/microMIPS branch size calculation by Maciej W. Rozycki · 10 years ago
  19. d2bfa6e target-mips: Fix formatting in `decode_opc' by Maciej W. Rozycki · 10 years ago
  20. d75de74 target-mips: Fix formatting in `decode_extended_mips16_opc' by Maciej W. Rozycki · 10 years ago
  21. cb269f2 target-mips: fix multiple TCG registers covering same data by Yongbok Kim · 10 years ago
  22. 342368a mips: Ensure PC update with MTC0 single-stepping by Maciej W. Rozycki · 10 years ago
  23. 8547957 target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ by Leon Alrae · 10 years ago
  24. 272f458 mips: Respect CP0.Status.CU1 for microMIPS FP branches by Maciej W. Rozycki · 10 years ago
  25. f768587 target-mips: add MSA MI10 format instructions by Yongbok Kim · 10 years ago
  26. 3bdeb68 target-mips: add MSA 2RF format instructions by Yongbok Kim · 10 years ago
  27. cbe50b9 target-mips: add MSA VEC/2R format instructions by Yongbok Kim · 10 years ago
  28. 7d05b9c target-mips: add MSA 3RF format instructions by Yongbok Kim · 10 years ago
  29. 1e608ec target-mips: add MSA ELM format instructions by Yongbok Kim · 10 years ago
  30. 28f99f0 target-mips: add MSA 3R format instructions by Yongbok Kim · 10 years ago
  31. d4cf28d target-mips: add MSA BIT format instructions by Yongbok Kim · 10 years ago
  32. 80e7159 target-mips: add MSA I5 format instruction by Yongbok Kim · 10 years ago
  33. 4c78954 target-mips: add MSA I8 format instructions by Yongbok Kim · 10 years ago
  34. 5692c6e target-mips: add MSA branch instructions by Yongbok Kim · 10 years ago
  35. 863f264 target-mips: add msa_reset(), global msa register by Yongbok Kim · 10 years ago
  36. 239dfeb target-mips: add MSA opcode enum by Yongbok Kim · 10 years ago
  37. 4cf8a45 target-mips: stop translation after ctc1 by Yongbok Kim · 10 years ago
  38. f31b035 target-mips: correctly handle access to unimplemented CP0 register by Leon Alrae · 11 years ago
  39. 339cd2a target-mips: implement forbidden slot by Leon Alrae · 11 years ago
  40. faf1f68 target-mips: add Config5.SBRI by Leon Alrae · 11 years ago
  41. aea1409 target-mips: add BadInstr and BadInstrP support by Leon Alrae · 11 years ago
  42. 9456c2f target-mips: add TLBINV support by Leon Alrae · 11 years ago
  43. 7207c7f target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1} by Leon Alrae · 11 years ago
  44. e98c0d1 target-mips: add KScratch registers by Leon Alrae · 11 years ago
  45. 340fff7 target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX by Peter Maydell · 10 years ago
  46. c7986fd target-mips/translate.c: Add ifdef guard around check_mips64() by Peter Maydell · 10 years ago
  47. b231c10 target-mips: fix broken MIPS16 and microMIPS by Yongbok Kim · 11 years ago
  48. a83bddd6 target-mips/translate.c: Update OPC_SYNCI by Dongxue Zhang · 11 years ago
  49. 0aefa33 target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions by Yongbok Kim · 11 years ago
  50. ddc584b target-mips: do not allow Status.FR=0 mode in 64-bit FPU by Leon Alrae · 11 years ago
  51. 3f49388 target-mips: add new Floating Point Comparison instructions by Yongbok Kim · 11 years ago
  52. e7f16ab target-mips: add new Floating Point instructions by Leon Alrae · 11 years ago
  53. d4ea6ac target-mips: add AUI, LSA and PCREL instruction families by Leon Alrae · 11 years ago
  54. 31837be target-mips: add compact and CP1 branches by Yongbok Kim · 11 years ago
  55. 15eacb9 target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions by Yongbok Kim · 11 years ago
  56. 01f7288 target-mips: Status.UX/SX/KX enable 32-bit address wrapping by Leon Alrae · 11 years ago
  57. 4267d3e target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 by Leon Alrae · 11 years ago
  58. b42ee5e target-mips: redefine Integer Multiply and Divide instructions by Leon Alrae · 11 years ago
  59. bf7910c target-mips: move PREF, CACHE, LLD and SCD instructions by Leon Alrae · 11 years ago
  60. fac5a07 target-mips: signal RI Exception on DSP and Loongson instructions by Leon Alrae · 11 years ago
  61. 10dc65d target-mips: split decode_opc_special* into *_r6 and *_legacy by Leon Alrae · 11 years ago
  62. 099e5b4 target-mips: extract decode_opc_special* from decode_opc by Leon Alrae · 11 years ago
  63. 4368b29 target-mips: move LL and SC instructions by Leon Alrae · 11 years ago
  64. b691d9d target-mips: add SELEQZ and SELNEZ instructions by Leon Alrae · 11 years ago
  65. fecd264 target-mips: signal RI Exception on instructions removed in R6 by Leon Alrae · 11 years ago
  66. a7e30d8 trace: [tcg] Include TCG-tracing header on all targets by Lluís Vilanova · 11 years ago
  67. 62eb3b9 target-mips/translate.c: Free TCG in OPC_DINSV by Dongxue Zhang · 11 years ago
  68. 0a2672b mips/kvm: Init EBase to correct KSEG0 by James Hogan · 11 years ago
  69. 5ab5c04 target-mips: copy CP0_Config1 into DisasContext by Aurelien Jarno · 11 years ago
  70. d70a319 Merge remote-tracking branch 'remotes/kvm/uq/master' into staging by Peter Maydell · 11 years ago
  71. d279279 target-mips: implement UserLocal Register by Petar Jovanovic · 11 years ago
  72. 4b69c7e target-mips: Reset CPU timer consistently by James Hogan · 11 years ago
  73. f08b617 softmmu: introduce cpu_ldst.h by Paolo Bonzini · 11 years ago
  74. 2ef6175 tcg: Invert the inclusion of helper.h by Richard Henderson · 11 years ago
  75. 7f6613c target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode by Petar Jovanovic · 11 years ago
  76. f0c3c50 cpu: Move breakpoints field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  77. 2710342 cpu: Move exception_index field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  78. 736d120 target-mips: add user-mode FR switch support for MIPS32r5 by Petar Jovanovic · 11 years ago
  79. b4dd99a target-mips: add support for CP0_Config5 by Petar Jovanovic · 11 years ago
  80. b4160af target-mips: add support for CP0_Config4 by Petar Jovanovic · 11 years ago
  81. 5f68f5a target-mips: Use new qemu_ld/st opcodes by Aurelien Jarno · 11 years ago
  82. 4d66261 target-mips: fix 64-bit FPU config for user-mode emulation by Petar Jovanovic · 11 years ago
  83. ab1eb72 Merge remote-tracking branch 'rth/tcg-pull' into staging by Anthony Liguori · 11 years ago
  84. 5cd8f62 tcg: Move helper registration into tcg_context_init by Richard Henderson · 11 years ago
  85. 51fb256 cpu: Drop cpu_model_str from CPU_COMMON by Andreas Färber · 12 years ago
  86. 8cfd049 tcg: Change tcg_gen_exit_tb argument to uintptr_t by Richard Henderson · 12 years ago
  87. a1fc624 target-mips: fix decoding of microMIPS POOL32Axf instructions by Leon Alrae · 12 years ago
  88. 240ce26 target-mips: fix branch in likely delay slot tcg assert by James Hogan · 12 years ago
  89. ed2803d cpu: Move singlestep_enabled field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  90. 6429db3 target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU by Andreas Färber · 12 years ago
  91. 878096e cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks by Andreas Färber · 12 years ago
  92. 639eadb target-mips: add missing check_dspr2 for multiply instructions by Petar Jovanovic · 12 years ago
  93. 259186a cpu: Move halted and interrupt_request fields to CPUState by Andreas Färber · 12 years ago
  94. 68473f1 mips64-linux-user: Enable 64-bit address mode and fpu by Richard Henderson · 12 years ago
  95. 26135ea target-mips: Fix accumulator selection for MIPS16 and microMIPS by Richard Sandiford · 12 years ago
  96. 806f352 gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end by Peter Maydell · 12 years ago
  97. ce1dd5d target-mips: Use mul[us]2 in [D]MULT[U] insns by Richard Henderson · 12 years ago
  98. 78ce64f target-mips: Move TCG initialization to MIPSCPU initfn by Andreas Färber · 12 years ago
  99. c1caf1d target-mips: Introduce QOM realizefn for MIPSCPU by Andreas Färber · 12 years ago
  100. 6f0af30 target-mips: enable access to DSP ASE if implemented by Petar Jovanovic · 12 years ago