commit | bf7910c6b1bc47517a9d7a6049d97d056e014eb0 | [log] [tgz] |
---|---|---|
author | Leon Alrae <leon.alrae@imgtec.com> | Fri Jun 27 08:49:03 2014 +0100 |
committer | Leon Alrae <leon.alrae@imgtec.com> | Mon Oct 13 12:38:24 2014 +0100 |
tree | e78c66baf97b61ac6540dbb2dd90aa580d5b8777 | |
parent | fac5a0733013f4e148b406056526f2208464d799 [diff] |
target-mips: move PREF, CACHE, LLD and SCD instructions The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6. Additionally, the hint codes in PREF instruction greater than or equal to 24 generate Reserved Instruction Exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>