- 55ea473 target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf by Daniel Henrique Barboza · 1 year, 6 months ago
- a47842d riscv: Add support for the Zfa extension by Christoph Müllner · 1 year, 7 months ago
- 56f0e99 target/riscv/cpu.c: create KVM mock properties by Daniel Henrique Barboza · 1 year, 7 months ago
- 63c7eed target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() by Daniel Henrique Barboza · 1 year, 7 months ago
- b71f9dc target/riscv/cpu.c: add satp_mode properties earlier by Daniel Henrique Barboza · 1 year, 7 months ago
- f7a69fa target/riscv/kvm.c: add multi-letter extension KVM properties by Daniel Henrique Barboza · 1 year, 7 months ago
- 92becce target/riscv: add KVM specific MISA properties by Daniel Henrique Barboza · 1 year, 7 months ago
- ed7e618 target/riscv/cpu: add misa_ext_info_arr[] by Daniel Henrique Barboza · 1 year, 7 months ago
- 492265a target/riscv: use KVM scratch CPUs to init KVM properties by Daniel Henrique Barboza · 1 year, 7 months ago
- d6a427e target/riscv/cpu.c: restrict 'marchid' value by Daniel Henrique Barboza · 1 year, 7 months ago
- a1863ad target/riscv/cpu.c: restrict 'mimpid' value by Daniel Henrique Barboza · 1 year, 7 months ago
- 1e34150 target/riscv/cpu.c: restrict 'mvendorid' value by Daniel Henrique Barboza · 1 year, 7 months ago
- eddabb6 target/riscv: skip features setup for KVM CPUs by Daniel Henrique Barboza · 1 year, 7 months ago
- 889caa4 target/riscv: Expose properties for BF16 extensions by Weiwei Li · 1 year, 8 months ago
- 4556fda target/riscv: Add properties for BF16 extensions by Weiwei Li · 1 year, 8 months ago
- b227f6a target/riscv: Add RVV registers to log by Ivan Klokov · 1 year, 7 months ago
- 029f5fe target/riscv/cpu.c: fix veyron-v1 CPU properties by Daniel Henrique Barboza · 1 year, 7 months ago
- 94692c3 target/riscv: Use xl instead of mxl for disassemble by LIU Zhiwei · 1 year, 8 months ago
- 9638cbd target/riscv: Restrict KVM-specific fields from ArchCPU by Philippe Mathieu-Daudé · 1 year, 10 months ago
- 356c13f target/riscv: Enable PC-relative translation by Weiwei Li · 1 year, 8 months ago
- 454c220 target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info by Weiwei Li · 1 year, 8 months ago
- 3594e3e target/riscv: smstateen knobs by Mayuresh Chitale · 1 year, 8 months ago
- faf3b5d target/riscv: rework write_misa() by Daniel Henrique Barboza · 1 year, 8 months ago
- 7f0bdfb target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() by Daniel Henrique Barboza · 1 year, 8 months ago
- e2fa85f target/riscv/cpu.c: validate extensions before riscv_timer_init() by Daniel Henrique Barboza · 1 year, 8 months ago
- f566406 target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() by Daniel Henrique Barboza · 1 year, 8 months ago
- bd30559 target/riscv/cpu.c: add priv_spec validate/disable_exts helpers by Daniel Henrique Barboza · 1 year, 8 months ago
- 61a33ea target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version by Weiwei Li · 1 year, 8 months ago
- b9a2b98 target/riscv: add PRIV_VERSION_LATEST by Daniel Henrique Barboza · 1 year, 8 months ago
- 8c6eeb5 target/riscv/cpu.c: remove set_priv_version() by Daniel Henrique Barboza · 1 year, 8 months ago
- 2238c9d target/riscv/cpu.c: remove set_vext_version() by Daniel Henrique Barboza · 1 year, 8 months ago
- d63be18 target/riscv/cpu.c: add riscv_cpu_validate_v() by Daniel Henrique Barboza · 1 year, 8 months ago
- 6672e29 target/riscv: Move zc* out of the experimental properties by Weiwei Li · 1 year, 9 months ago
- e1d084a target/riscv: add Ventana's Veyron V1 CPU by Rahul Pathak · 1 year, 9 months ago
- 9e1a30d target/riscv: add TYPE_RISCV_DYNAMIC_CPU by Daniel Henrique Barboza · 1 year, 10 months ago
- 42967f4 target/riscv: Add a general status enum for extensions by LIU Zhiwei · 1 year, 10 months ago
- 9ba63f9 target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx by Weiwei Li · 1 year, 10 months ago
- dd8f244 target/riscv/cpu.c: redesign register_cpu_props() by Daniel Henrique Barboza · 1 year, 10 months ago
- 4f13abc target/riscv: add RVG and remove cpu->cfg.ext_g by Daniel Henrique Barboza · 1 year, 10 months ago
- 8ef67c6 target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() by Daniel Henrique Barboza · 1 year, 10 months ago
- 7295b18 target/riscv: remove riscv_cpu_sync_misa_cfg() by Daniel Henrique Barboza · 1 year, 10 months ago
- 3e7674f target/riscv: remove cpu->cfg.ext_v by Daniel Henrique Barboza · 1 year, 10 months ago
- 64f4b54 target/riscv: remove cpu->cfg.ext_j by Daniel Henrique Barboza · 1 year, 10 months ago
- b5c042e target/riscv: remove cpu->cfg.ext_h by Daniel Henrique Barboza · 1 year, 10 months ago
- e17801e target/riscv: remove cpu->cfg.ext_u by Daniel Henrique Barboza · 1 year, 10 months ago
- f1ea2a5 target/riscv: remove cpu->cfg.ext_s by Daniel Henrique Barboza · 1 year, 10 months ago
- 1a36e23 target/riscv: remove cpu->cfg.ext_m by Daniel Henrique Barboza · 1 year, 10 months ago
- 427d8e7 target/riscv: remove cpu->cfg.ext_e by Daniel Henrique Barboza · 1 year, 10 months ago
- 74828ea target/riscv: remove cpu->cfg.ext_i by Daniel Henrique Barboza · 1 year, 10 months ago
- 4b33598 target/riscv: remove cpu->cfg.ext_f by Daniel Henrique Barboza · 1 year, 10 months ago
- ffffd95 target/riscv: remove cpu->cfg.ext_d by Daniel Henrique Barboza · 1 year, 10 months ago
- c00226e target/riscv: remove cpu->cfg.ext_c by Daniel Henrique Barboza · 1 year, 10 months ago
- 4c75994 target/riscv: remove cpu->cfg.ext_a by Daniel Henrique Barboza · 1 year, 10 months ago
- b3df64c target/riscv: introduce riscv_cpu_add_misa_properties() by Daniel Henrique Barboza · 1 year, 10 months ago
- ccc84a7 target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data by Daniel Henrique Barboza · 1 year, 10 months ago
- 6508272 target/riscv: remove MISA properties from isa_edata_arr[] by Daniel Henrique Barboza · 1 year, 10 months ago
- 1ffa805 target/riscv: sync env->misa_ext* with cpu->cfg in realize() by Daniel Henrique Barboza · 1 year, 10 months ago
- 246f879 target/riscv: Fix lines with over 80 characters by Weiwei Li · 1 year, 10 months ago
- 3b57254 target/riscv: Fix format for comments by Weiwei Li · 1 year, 10 months ago
- c45eff3 target/riscv: Fix format for indentation by Weiwei Li · 1 year, 10 months ago
- 3825652 target/riscv: Remove riscv_cpu_virt_enabled() by Weiwei Li · 1 year, 10 months ago
- 00d312b target/riscv: Add support for Zce by Weiwei Li · 1 year, 11 months ago
- d364c0a target/riscv: expose properties for Zc* extension by Weiwei Li · 1 year, 11 months ago
- 2288a5c target/riscv: add cfg properties for Zc* extension by Weiwei Li · 1 year, 11 months ago
- bbb9fc2 target/riscv: Simplify type conversion for CPURISCVState by Weiwei Li · 1 year, 11 months ago
- 662ed9c target/riscv: Fix priv version dependency for vector and zfh by LIU Zhiwei · 1 year, 10 months ago
- 6df3747 riscv: Introduce satp mode hw capabilities by Alexandre Ghiti · 1 year, 11 months ago
- 6f23aae riscv: Allow user to set the satp mode by Alexandre Ghiti · 1 year, 11 months ago
- c01756a riscv: Pass Object to register_cpu_props instead of DeviceState by Alexandre Ghiti · 1 year, 11 months ago
- f1bd6f8 target/riscv: cpu: Implement get_arch_id callback by Mayuresh Chitale · 1 year, 11 months ago
- e05da09 target/riscv: implement Zicbom extension by Christoph Muellner · 1 year, 11 months ago
- a939c50 target/riscv: implement Zicboz extension by Christoph Muellner · 1 year, 11 months ago
- 76116e2 Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu into staging by Peter Maydell · 1 year, 11 months ago
- 8e5aded Merge patch series "target/riscv: Add support for Svadu extension" by Palmer Dabbelt · 1 year, 11 months ago
- 62108f0 target/riscv: Export Svadu property by Weiwei Li · 1 year, 11 months ago
- 0af3f11 target/riscv: Add *envcfg.HADE related check in address translation by Weiwei Li · 1 year, 11 months ago
- 7a6613d target/riscv: Add *envcfg.PBMTE related check in address translation by Weiwei Li · 1 year, 11 months ago
- b8e1f32 target/riscv: Add support for Zicond extension by Weiwei Li · 1 year, 11 months ago
- 312f632 Merge patch series "target/riscv: Some updates to float point related extensions" by Palmer Dabbelt · 1 year, 11 months ago
- 058d9d3 target/riscv: Expose properties for Zv* extensions by Weiwei Li · 2 years ago
- 51f3308 target/riscv: Indent fixes in cpu.c by Weiwei Li · 2 years ago
- 2e60f9e target/riscv: Add property check for Zvfh{min} extensions by Weiwei Li · 2 years ago
- e7f0a80 target/riscv: Fix relationship between V, Zve*, F and D by Weiwei Li · 2 years ago
- a0d805f target/riscv: Fix the relationship between Zhinxmin and Zhinx by Weiwei Li · 2 years ago
- 1d2cb5a target/riscv: Fix the relationship between Zfhmin and Zfh by Weiwei Li · 2 years ago
- dcf654a target/riscv: remove RISCV_FEATURE_MMU by Daniel Henrique Barboza · 1 year, 11 months ago
- 3fe40ef target/riscv: remove RISCV_FEATURE_PMP by Daniel Henrique Barboza · 1 year, 11 months ago
- 6a3ffda target/riscv: remove RISCV_FEATURE_EPMP by Daniel Henrique Barboza · 1 year, 11 months ago
- 0963144 target/riscv/cpu.c: error out if EPMP is enabled without PMP by Daniel Henrique Barboza · 1 year, 11 months ago
- cdfb290 target/riscv: remove RISCV_FEATURE_DEBUG by Daniel Henrique Barboza · 1 year, 11 months ago
- 54bd9b6 target/riscv: allow MISA writes as experimental by Daniel Henrique Barboza · 1 year, 11 months ago
- 0489d5b target/riscv: Replace `tb_pc()` with `tb->pc` by Anton Johansson · 1 year, 11 months ago
- 0e66014 target/riscv: Remove privileged spec version restriction for RVV by Frank Chang · 2 years ago
- 578086b RISC-V: Adding XTheadFmv ISA extension by Christoph Müllner · 2 years ago
- 95bd8da RISC-V: Add initial support for T-Head C906 by Christoph Müllner · 2 years ago
- 7ad2878 RISC-V: Set minimum priv version for Zfh to 1.11 by Christoph Müllner · 2 years ago
- d4d9011 RISC-V: Adding T-Head FMemIdx extension by Christoph Müllner · 2 years ago
- 45f9df8 RISC-V: Adding T-Head MemIdx extension by Christoph Müllner · 2 years ago
- af99aa7 RISC-V: Adding T-Head MemPair extension by Christoph Müllner · 2 years ago
- b8a5832 RISC-V: Adding T-Head multiply-accumulate instructions by Christoph Müllner · 2 years ago