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qemu / qemu / 2f5f70fa5f41e3893a781c065be76e56db4f2e32 / target-arm
  1. a7e30d8 trace: [tcg] Include TCG-tracing header on all targets by Lluís Vilanova · 11 years ago
  2. dbb1fb2 target-arm: A64: fix TLB flush instructions by Alex Bennée · 11 years ago
  3. dcd82c1 target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault by Alex Bennée · 11 years ago
  4. cdcf140 target-arm: Fix bit test in sp_el0_access by Stefan Weil · 11 years ago
  5. 63b6055 target-arm: Add FAR_EL2 and 3 by Edgar E. Iglesias · 11 years ago
  6. f2c30f4 target-arm: Add ESR_EL2 and 3 by Edgar E. Iglesias · 11 years ago
  7. 2f0180c target-arm: Make far_el1 an array by Edgar E. Iglesias · 11 years ago
  8. f151b12 target-arm: A64: Respect SPSEL when taking exceptions by Edgar E. Iglesias · 11 years ago
  9. 98ea561 target-arm: A64: Respect SPSEL in ERET SP restore by Edgar E. Iglesias · 11 years ago
  10. 9208b96 target-arm: A64: Break out aarch64_save/restore_sp by Edgar E. Iglesias · 11 years ago
  11. 75c9a1a target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs by Peter Maydell · 11 years ago
  12. 5d831be Fix new typos (found by codespell) by Stefan Weil · 11 years ago
  13. dd032e3 target-arm: Introduce per-CPU field for PSCI version by Pranavkumar Sawargaonkar · 11 years ago
  14. 73542cf target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64 by Pranavkumar Sawargaonkar · 11 years ago
  15. 7cd62e5 target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible by Pranavkumar Sawargaonkar · 11 years ago
  16. 228d5e0 target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 by Pranavkumar Sawargaonkar · 11 years ago
  17. 4063452 target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv() by Peter Maydell · 11 years ago
  18. 220ad4c target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() by Peter Maydell · 11 years ago
  19. 5661ae6 target-arm: Add ULL suffix to calculation of page size by Peter Maydell · 11 years ago
  20. e389be1 target-arm: implement PD0/PD1 bits for TTBCR by Fabian Aggeler · 11 years ago
  21. 59dcd29 target-arm: Use Common Tables in AES Instructions by Tom Musta · 11 years ago
  22. 3b1a413 target-arm: Delete unused iwmmxt_msadb helper by Peter Maydell · 11 years ago
  23. d3afacc target-arm: Fix errors in writes to generic timer control registers by Peter Maydell · 11 years ago
  24. f6fe04d target-arm: A64: Implement two-register SHA instructions by Peter Maydell · 11 years ago
  25. be56f04 target-arm: A64: Implement 3-register SHA instructions by Peter Maydell · 11 years ago
  26. 5acc765 target-arm: A64: Implement AES instructions by Peter Maydell · 11 years ago
  27. aa63346 target-arm: A32/T32: Mask CRC value in calling code, not helper by Peter Maydell · 11 years ago
  28. 130f2e7 target-arm: A64: Implement CRC instructions by Peter Maydell · 11 years ago
  29. da5141f target-arm: VFPv4 implies half-precision extension by Peter Maydell · 11 years ago
  30. 25f748e target-arm: Clean up handling of ARMv8 optional feature bits by Peter Maydell · 11 years ago
  31. fb8ad9f target-arm: Remove unnecessary setting of feature bits by Peter Maydell · 11 years ago
  32. 46d9dfd target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 by Peter Maydell · 11 years ago
  33. 411bdc7 target-arm: A64: Use PMULL feature bit for PMULL by Peter Maydell · 11 years ago
  34. 4e624ed target-arm: add support for v8 VMULL.P64 instruction by Peter Maydell · 11 years ago
  35. 526d009 target-arm: Allow 3reg_wide undefreq to encode more bad size options by Peter Maydell · 11 years ago
  36. f1ecb91 target-arm: add support for v8 SHA1 and SHA256 instructions by Ard Biesheuvel · 11 years ago
  37. d615efa target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables by Ian Campbell · 11 years ago
  38. 8d5c773 target-arm: Prepare cpreg writefns/readfns for EL3/SecExt by Fabian Aggeler · 11 years ago
  39. bf01601 target-arm/cpu64.c: Actually register Cortex-A57 impdef registers by Peter Maydell · 11 years ago
  40. f08b617 softmmu: introduce cpu_ldst.h by Paolo Bonzini · 11 years ago
  41. 1d85476 target-arm: move arm_*_code to a separate file by Paolo Bonzini · 11 years ago
  42. 0f590e74 softmmu: commonize helper definitions by Paolo Bonzini · 11 years ago
  43. 2ef6175 tcg: Invert the inclusion of helper.h by Richard Henderson · 11 years ago
  44. a1ba125 target-arm: A64: Register VBAR_EL3 by Edgar E. Iglesias · 11 years ago
  45. d42e3c2 target-arm: A64: Register VBAR_EL2 by Edgar E. Iglesias · 11 years ago
  46. 855ea66 target-arm: Make vbar_write writeback to any CPREG by Edgar E. Iglesias · 11 years ago
  47. 61d4b21 target-arm: A64: Generalize update_spsel for the various ELs by Edgar E. Iglesias · 11 years ago
  48. db6c3cd target-arm: A64: Generalize ERET to various ELs by Edgar E. Iglesias · 11 years ago
  49. 14c521d target-arm: A64: Trap ERET from EL0 at translation time by Edgar E. Iglesias · 11 years ago
  50. 7ab6c10 target-arm: A64: Forbid ERET to higher or unimplemented ELs by Edgar E. Iglesias · 11 years ago
  51. 81547d6 target-arm: Register EL3 versions of ELR and SPSR by Edgar E. Iglesias · 11 years ago
  52. 3b685ba target-arm: Register EL2 versions of ELR and SPSR by Edgar E. Iglesias · 11 years ago
  53. 1fe8141 target-arm: Add a feature flag for EL3 by Edgar E. Iglesias · 11 years ago
  54. cca7c2f target-arm: Add a feature flag for EL2 by Edgar E. Iglesias · 11 years ago
  55. 2a923c4 target-arm: A64: Introduce aarch64_banked_spsr_index() by Edgar E. Iglesias · 11 years ago
  56. 28c9457 target-arm: Add SPSR entries for EL2/HYP and EL3/MON by Edgar E. Iglesias · 11 years ago
  57. 1b17423 target-arm: A64: Add ELR entries for EL2 and 3 by Edgar E. Iglesias · 11 years ago
  58. 73fb3b7 target-arm: A64: Add SP entries for EL2 and 3 by Edgar E. Iglesias · 11 years ago
  59. 68fdb6c target-arm: c12_vbar -> vbar_el[] by Edgar E. Iglesias · 11 years ago
  60. d81c519 target-arm: Make esr_el1 an array by Edgar E. Iglesias · 11 years ago
  61. 6947f05 target-arm: Make elr_el1 an array by Edgar E. Iglesias · 11 years ago
  62. f79fbf3 target-arm: Use a 1:1 mapping between EL and MMU index by Edgar E. Iglesias · 11 years ago
  63. 6ce2faf target-arm: A32: Use get_mem_index for load/stores by Edgar E. Iglesias · 11 years ago
  64. c119779 target-arm/translate.c: Use get_mem_index() for SRS memory accesses by Peter Maydell · 11 years ago
  65. a99caa4 target-arm/translate.c: Clean up mmu index handling for ldrt/strt by Peter Maydell · 11 years ago
  66. 9d4c4e8 target-arm: Move get_mem_index to translate.h by Edgar E. Iglesias · 11 years ago
  67. f0aff25 target-arm: implement CPACR register logic for ARMv7 by Fabian Aggeler · 11 years ago
  68. 00d0f7c target-arm: Fix segfault on startup when KVM enabled by Christoffer Dall · 11 years ago
  69. 6b7aa99 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging by Peter Maydell · 11 years ago
  70. 2f0d863 target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged by Peter Maydell · 11 years ago
  71. 8f1e884 savevm: Remove all the unneeded version_minimum_id_old (arm) by Juan Quintela · 11 years ago
  72. 50a2c6e kvm: reset state from the CPU's reset method by Paolo Bonzini · 12 years ago
  73. 3476436 vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/ by Michael S. Tsirkin · 11 years ago
  74. 37f0806 target-arm: Correct a comment refering to EL0 by Edgar E. Iglesias · 11 years ago
  75. 6ab9f49 target-arm: A64: Fix a typo when declaring TLBI ops by Edgar E. Iglesias · 11 years ago
  76. 1b505f9 target-arm: A64: Handle blr lr by Edgar E. Iglesias · 11 years ago
  77. fed3ffb target-arm: Make vbar_write 64bit friendly on 32bit hosts by Edgar E. Iglesias · 11 years ago
  78. 252ec40 target-arm: implement WFE/YIELD as a yield for AArch64 by Rob Herring · 11 years ago
  79. 3b77157 target-arm: Implement XScale cache lockdown operations as NOPs by Peter Maydell · 11 years ago
  80. e44a90c target-arm: A64: fix unallocated test of scalar SQXTUN by Alex Bennée · 11 years ago
  81. 33bbd75 arm: translate.c: Fix smlald Instruction by Peter Crosthwaite · 11 years ago
  82. b5cde1d target-arm/gdbstub64.c: remove useless 'break' statement. by Chen Gang · 11 years ago
  83. 1773111 target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 by Peter Maydell · 11 years ago
  84. 7633378 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc by Peter Maydell · 11 years ago
  85. c29f9a0 target-arm: Make Cortex-A15 CBAR read-only by Peter Maydell · 11 years ago
  86. f318cec target-arm: Implement CBAR for Cortex-A57 by Peter Maydell · 11 years ago
  87. 377a44e target-arm: Implement Cortex-A57 implementation-defined system registers by Peter Maydell · 11 years ago
  88. 3933443 target-arm: Implement RVBAR register by Peter Maydell · 11 years ago
  89. 1952552 target-arm: Implement AArch64 address translation operations by Peter Maydell · 11 years ago
  90. f32cdad target-arm: Implement auxiliary fault status registers by Peter Maydell · 11 years ago
  91. 9449fdf target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8 by Peter Maydell · 11 years ago
  92. 00a29f3 target-arm: Don't expose wildcard ID register definitions for ARMv8 by Peter Maydell · 11 years ago
  93. 85acfa9 target-arm: Remove THUMB2EE feature from AArch64 'any' CPU by Peter Maydell · 11 years ago
  94. 1090b9c target-arm: Implement ISR_EL1 register by Peter Maydell · 11 years ago
  95. 2eef0bf target-arm: Implement AArch64 view of ACTLR by Peter Maydell · 11 years ago
  96. 014406b target-arm: Implement AArch64 view of CONTEXTIDR by Peter Maydell · 11 years ago
  97. 0ff644a target-arm: Implement AArch64 views of AArch32 ID registers by Peter Maydell · 11 years ago
  98. cb1fa94 target-arm: Add Cortex-A57 processor by Peter Maydell · 11 years ago
  99. a50c0f5 target-arm: Implement ARMv8 MVFR registers by Peter Maydell · 11 years ago
  100. 52e60cd target-arm: Implement AArch64 EL1 exception handling by Rob Herring · 11 years ago