1. ad80e36 hw, target: Add ResetType argument to hold and exit phase methods by Peter Maydell · 11 months ago
  2. 2f6cab0 hw/char: Constify VMState by Richard Henderson · 1 year, 2 months ago
  3. 66997c4 cleanup: Tweak and re-run return_directly.cocci by Markus Armbruster · 2 years, 3 months ago
  4. 6a03349 hw/char: sifive_uart: Register device in 'input' category by Bin Meng · 3 years, 5 months ago
  5. 6ee7ba1 hw/char: QOMify sifive_uart by Lukas Jünger · 3 years, 9 months ago
  6. 244a9fc hw/char: Consistent function names for sifive_uart by Lukas Jünger · 3 years, 9 months ago
  7. f6527ea hw: Do not include hw/sysbus.h if it is not necessary by Thomas Huth · 4 years ago
  8. e060543 hw: Remove superfluous includes of hw/hw.h by Thomas Huth · 4 years ago
  9. b609b7e hw/riscv: Move sifive_uart model to hw/char by Bin Meng · 4 years, 6 months ago[Renamed (98%) from hw/riscv/sifive_uart.c]
  10. 083b266 chardev: Use QEMUChrEvent enum in IOEventHandler typedef by Philippe Mathieu-Daudé · 5 years ago
  11. 131f093 riscv: hw: Remove the unnecessary include of target/riscv/cpu.h by Bin Meng · 5 years ago
  12. a2360c8 riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead by Bin Meng · 5 years ago
  13. 650d103 Include hw/hw.h exactly where needed by Markus Armbruster · 6 years ago
  14. 64552b6 Include hw/irq.h a lot less by Markus Armbruster · 6 years ago
  15. 4e85ea8 riscv: sifive_uart: Generate TX interrupt by Bin Meng · 6 years ago
  16. 40061ac sifive_uart: Implement interrupt pending register by Nathaniel Graff · 6 years ago
  17. bb72692 SiFive RISC-V UART Device by Michael Clark · 7 years ago