Google Git
Sign in
qemu / qemu / 0971f1bed21b16e59eb5d15cd03180f110a1e8c0 / target-arm
  1. 6b7aa99 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging by Peter Maydell · 11 years ago
  2. 2f0d863 target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged by Peter Maydell · 11 years ago
  3. 8f1e884 savevm: Remove all the unneeded version_minimum_id_old (arm) by Juan Quintela · 11 years ago
  4. 50a2c6e kvm: reset state from the CPU's reset method by Paolo Bonzini · 12 years ago
  5. 3476436 vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/ by Michael S. Tsirkin · 11 years ago
  6. 37f0806 target-arm: Correct a comment refering to EL0 by Edgar E. Iglesias · 11 years ago
  7. 6ab9f49 target-arm: A64: Fix a typo when declaring TLBI ops by Edgar E. Iglesias · 11 years ago
  8. 1b505f9 target-arm: A64: Handle blr lr by Edgar E. Iglesias · 11 years ago
  9. fed3ffb target-arm: Make vbar_write 64bit friendly on 32bit hosts by Edgar E. Iglesias · 11 years ago
  10. 252ec40 target-arm: implement WFE/YIELD as a yield for AArch64 by Rob Herring · 11 years ago
  11. 3b77157 target-arm: Implement XScale cache lockdown operations as NOPs by Peter Maydell · 11 years ago
  12. e44a90c target-arm: A64: fix unallocated test of scalar SQXTUN by Alex Bennée · 11 years ago
  13. 33bbd75 arm: translate.c: Fix smlald Instruction by Peter Crosthwaite · 11 years ago
  14. b5cde1d target-arm/gdbstub64.c: remove useless 'break' statement. by Chen Gang · 11 years ago
  15. 1773111 target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 by Peter Maydell · 11 years ago
  16. 7633378 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc by Peter Maydell · 11 years ago
  17. c29f9a0 target-arm: Make Cortex-A15 CBAR read-only by Peter Maydell · 11 years ago
  18. f318cec target-arm: Implement CBAR for Cortex-A57 by Peter Maydell · 11 years ago
  19. 377a44e target-arm: Implement Cortex-A57 implementation-defined system registers by Peter Maydell · 11 years ago
  20. 3933443 target-arm: Implement RVBAR register by Peter Maydell · 11 years ago
  21. 1952552 target-arm: Implement AArch64 address translation operations by Peter Maydell · 11 years ago
  22. f32cdad target-arm: Implement auxiliary fault status registers by Peter Maydell · 11 years ago
  23. 9449fdf target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8 by Peter Maydell · 11 years ago
  24. 00a29f3 target-arm: Don't expose wildcard ID register definitions for ARMv8 by Peter Maydell · 11 years ago
  25. 85acfa9 target-arm: Remove THUMB2EE feature from AArch64 'any' CPU by Peter Maydell · 11 years ago
  26. 1090b9c target-arm: Implement ISR_EL1 register by Peter Maydell · 11 years ago
  27. 2eef0bf target-arm: Implement AArch64 view of ACTLR by Peter Maydell · 11 years ago
  28. 014406b target-arm: Implement AArch64 view of CONTEXTIDR by Peter Maydell · 11 years ago
  29. 0ff644a target-arm: Implement AArch64 views of AArch32 ID registers by Peter Maydell · 11 years ago
  30. cb1fa94 target-arm: Add Cortex-A57 processor by Peter Maydell · 11 years ago
  31. a50c0f5 target-arm: Implement ARMv8 MVFR registers by Peter Maydell · 11 years ago
  32. 52e60cd target-arm: Implement AArch64 EL1 exception handling by Rob Herring · 11 years ago
  33. 2f2a00a target-arm: Move arm_log_exception() into internals.h by Peter Maydell · 11 years ago
  34. a65f1de target-arm: Implement AArch64 SPSR_EL1 by Peter Maydell · 11 years ago
  35. f502cfc target-arm: Implement SP_EL0, SP_EL1 by Peter Maydell · 11 years ago
  36. a0618a1 target-arm: Add AArch64 ELR_EL1 register. by Peter Maydell · 11 years ago
  37. 6cd8a26 target-arm: Implement AArch64 views of fault status and data registers by Rob Herring · 11 years ago
  38. 7e09797 target-arm: Use dedicated CPU state fields for ARM946 access bit registers by Peter Maydell · 11 years ago
  39. aca3f40 target-arm: A64: Implement DC ZVA by Peter Maydell · 11 years ago
  40. 9225d73 target-arm: Don't mention PMU in debug feature register by Peter Maydell · 11 years ago
  41. 2c8dd31 target-arm: Add v8 mmu translation support by Rob Herring · 11 years ago
  42. 2c7ffc4 target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1 by Peter Maydell · 11 years ago
  43. 90e4963 target-arm: A64: Add assertion that FP access was checked by Peter Maydell · 11 years ago
  44. 8c6afa6 target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set by Peter Maydell · 11 years ago
  45. 0089238 target-arm: Provide syndrome information for MMU faults by Rob Herring · 11 years ago
  46. d4a2dc6 target-arm: Add support for generating exceptions with syndrome information by Peter Maydell · 11 years ago
  47. 8bcbf37 target-arm: Provide correct syndrome information for cpreg access traps by Peter Maydell · 11 years ago
  48. abf1172 target-arm: Define exception record for AArch64 exceptions by Peter Maydell · 11 years ago
  49. c2b820f target-arm: Implement AArch64 DAIF system register by Peter Maydell · 11 years ago
  50. ccd3808 target-arm: Split out private-to-target functions into internals.h by Peter Maydell · 11 years ago
  51. 6df05bd target-arm: Add missing 'static' attribute by Stefan Weil · 11 years ago
  52. d108609 target-arm: Fix A64 Neon MLS by Peter Maydell · 11 years ago
  53. 09e0373 target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD) by Alex Bennée · 11 years ago
  54. 0a79bc8 target-arm: A64: Add saturating int ops (SQNEG/SQABS) by Alex Bennée · 11 years ago
  55. c2fb418 target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) by Alex Bennée · 11 years ago
  56. 5553955 target-arm: A64: Implement FCVTXN by Peter Maydell · 11 years ago
  57. 5201c13 target-arm: A64: Implement scalar saturating narrow ops by Alex Bennée · 11 years ago
  58. 8b092ca target-arm: A64: Move handle_2misc_narrow function by Alex Bennée · 11 years ago
  59. b6d4443 target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE by Alex Bennée · 11 years ago
  60. 2ed3ea1 target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories by Peter Maydell · 11 years ago
  61. a847f32 target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL by Peter Maydell · 11 years ago
  62. 03df01e target-arm: A64: Implement FRINT* by Peter Maydell · 11 years ago
  63. 37a706a target-arm: A64: Implement SRI by Peter Maydell · 11 years ago
  64. 8f0c675 target-arm: A64: Add FRECPX (reciprocal exponent) by Alex Bennée · 11 years ago
  65. a566da1 target-arm: A64: List unsupported shift-imm opcodes by Peter Maydell · 11 years ago
  66. 931c8cc target-arm: A64: Implement FCVTL by Peter Maydell · 11 years ago
  67. 261a5b4 target-arm: A64: Implement FCVTN by Peter Maydell · 11 years ago
  68. 04c7c6c target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions by Peter Maydell · 11 years ago
  69. 73a81d1 target-arm: A64: Implement SHLL, SHLL2 by Peter Maydell · 11 years ago
  70. 6781fa1 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP by Peter Maydell · 11 years ago
  71. c1b876b target-arm: A64: Saturating and narrowing shift ops by Alex Bennée · 11 years ago
  72. b05c306 target-arm: A64: Add remaining CLS/Z vector ops by Alex Bennée · 11 years ago
  73. f612537 target-arm: A64: Add FSQRT to C3.6.17 (two misc) by Alex Bennée · 11 years ago
  74. 10113b6 target-arm: A64: Add last AdvSIMD Integer to FP ops by Alex Bennée · 11 years ago
  75. cf4ab1a target-arm: A64: Fix bug in add_sub_ext handling of rn by Alex Bennée · 11 years ago
  76. a984e42 target-arm: A64: Implement PMULL instruction by Peter Maydell · 11 years ago
  77. d6d6058 target-arm: Add ARM_CP_IO notation to PMCR reginfo by Peter Maydell · 11 years ago
  78. 3b163b0 misc: Fix typos in comments by Stefan Weil · 11 years ago
  79. 0c591eb cputlb: Change tlb_set_page() argument to CPUState by Andreas Färber · 12 years ago
  80. 00c8cb0 cputlb: Change tlb_flush() argument to CPUState by Andreas Färber · 12 years ago
  81. 31b030d cputlb: Change tlb_flush_page() argument to CPUState by Andreas Färber · 12 years ago
  82. a47dddd exec: Change cpu_abort() argument to CPUState by Andreas Färber · 12 years ago
  83. 3f38f30 translate-all: Change cpu_restore_state() argument to CPUState by Andreas Färber · 12 years ago
  84. 5638d18 cpu-exec: Change cpu_loop_exit() argument to CPUState by Andreas Färber · 12 years ago
  85. d5a11fe exec: Change tlb_fill() argument to CPUState by Andreas Färber · 12 years ago
  86. f0c3c50 cpu: Move breakpoints field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  87. 0429a97 cpu: Move opaque field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  88. 2710342 cpu: Move exception_index field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  89. 7510454 cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook by Andreas Färber · 12 years ago
  90. 9262685 cpu: Factor out cpu_generic_init() by Andreas Färber · 11 years ago
  91. 8c2e1b0 cpu: Turn cpu_has_work() into a CPUClass hook by Andreas Färber · 12 years ago
  92. 70d7466 target-arm: Clean up ENV_GET_CPU() usage by Andreas Färber · 11 years ago
  93. 72c1d3a target-arm: Implement WFE as a yield operation by Peter Maydell · 11 years ago
  94. 0624976 target-arm: Fix intptr_t vs tcg_target_long by Richard Henderson · 11 years ago
  95. 7c2cb42 target-arm: Implements the ARM PMCCNTR register by Alistair Francis · 11 years ago
  96. af51993 target-arm: Fix incorrect setting of E bit in CPSR by Peter Maydell · 11 years ago
  97. eb0ecd5 target-arm: Add support for AArch32 ARMv8 CRC32 instructions by Will Newton · 11 years ago
  98. 1f79ee3 target-arm: Add utility function for checking AA32/64 state of an EL by Peter Maydell · 11 years ago
  99. 34222fb target-arm: Implement AArch64 view of CPACR by Peter Maydell · 11 years ago
  100. 9cfa0b4 target-arm: A64: Implement MSR (immediate) instructions by Peter Maydell · 11 years ago