pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM Nested Vectored Interrupt Controller |
| 3 | * |
| 4 | * Copyright (c) 2006-2007 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the GPL. |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8 | * |
| 9 | * The ARMv7M System controller is fairly tightly tied in with the |
| 10 | * NVIC. Much of that is also implemented here. |
| 11 | */ |
| 12 | |
Peter Maydell | 8ef94f0 | 2016-01-26 18:17:05 +0000 | [diff] [blame] | 13 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 14 | #include "qapi/error.h" |
Paolo Bonzini | 4771d75 | 2016-01-19 21:51:44 +0100 | [diff] [blame] | 15 | #include "qemu-common.h" |
Paolo Bonzini | 33c1187 | 2016-03-15 16:58:45 +0100 | [diff] [blame] | 16 | #include "cpu.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 17 | #include "hw/sysbus.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 18 | #include "qemu/timer.h" |
Peter Maydell | bd2be15 | 2013-04-09 15:26:55 +0100 | [diff] [blame] | 19 | #include "hw/arm/arm.h" |
Peter Maydell | 6bf436c | 2017-02-20 15:35:56 +0000 | [diff] [blame] | 20 | #include "hw/arm/armv7m_nvic.h" |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 21 | #include "target/arm/cpu.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 22 | #include "qemu/log.h" |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 23 | #include "trace.h" |
| 24 | |
| 25 | /* IRQ number counting: |
| 26 | * |
| 27 | * the num-irq property counts the number of external IRQ lines |
| 28 | * |
| 29 | * NVICState::num_irq counts the total number of exceptions |
| 30 | * (external IRQs, the 15 internal exceptions including reset, |
| 31 | * and one for the unused exception number 0). |
| 32 | * |
| 33 | * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines. |
| 34 | * |
| 35 | * NVIC_MAX_VECTORS is the highest permitted number of exceptions. |
| 36 | * |
| 37 | * Iterating through all exceptions should typically be done with |
| 38 | * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0. |
| 39 | * |
| 40 | * The external qemu_irq lines are the NVIC's external IRQ lines, |
| 41 | * so line 0 is exception 16. |
| 42 | * |
| 43 | * In the terminology of the architecture manual, "interrupts" are |
| 44 | * a subcategory of exception referring to the external interrupts |
| 45 | * (which are exception numbers NVIC_FIRST_IRQ and upward). |
| 46 | * For historical reasons QEMU tends to use "interrupt" and |
| 47 | * "exception" more or less interchangeably. |
| 48 | */ |
| 49 | #define NVIC_FIRST_IRQ 16 |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 50 | #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ) |
| 51 | |
| 52 | /* Effective running priority of the CPU when no exception is active |
| 53 | * (higher than the highest possible priority value) |
| 54 | */ |
| 55 | #define NVIC_NOEXC_PRIO 0x100 |
| 56 | |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 57 | static const uint8_t nvic_id[] = { |
| 58 | 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 |
| 59 | }; |
| 60 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 61 | static int nvic_pending_prio(NVICState *s) |
| 62 | { |
| 63 | /* return the priority of the current pending interrupt, |
| 64 | * or NVIC_NOEXC_PRIO if no interrupt is pending |
| 65 | */ |
| 66 | return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO; |
| 67 | } |
| 68 | |
| 69 | /* Return the value of the ISCR RETTOBASE bit: |
| 70 | * 1 if there is exactly one active exception |
| 71 | * 0 if there is more than one active exception |
| 72 | * UNKNOWN if there are no active exceptions (we choose 1, |
| 73 | * which matches the choice Cortex-M3 is documented as making). |
| 74 | * |
| 75 | * NB: some versions of the documentation talk about this |
| 76 | * counting "active exceptions other than the one shown by IPSR"; |
| 77 | * this is only different in the obscure corner case where guest |
| 78 | * code has manually deactivated an exception and is about |
| 79 | * to fail an exception-return integrity check. The definition |
| 80 | * above is the one from the v8M ARM ARM and is also in line |
| 81 | * with the behaviour documented for the Cortex-M3. |
| 82 | */ |
| 83 | static bool nvic_rettobase(NVICState *s) |
| 84 | { |
| 85 | int irq, nhand = 0; |
| 86 | |
| 87 | for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { |
| 88 | if (s->vectors[irq].active) { |
| 89 | nhand++; |
| 90 | if (nhand == 2) { |
| 91 | return 0; |
| 92 | } |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | return 1; |
| 97 | } |
| 98 | |
| 99 | /* Return the value of the ISCR ISRPENDING bit: |
| 100 | * 1 if an external interrupt is pending |
| 101 | * 0 if no external interrupt is pending |
| 102 | */ |
| 103 | static bool nvic_isrpending(NVICState *s) |
| 104 | { |
| 105 | int irq; |
| 106 | |
| 107 | /* We can shortcut if the highest priority pending interrupt |
| 108 | * happens to be external or if there is nothing pending. |
| 109 | */ |
| 110 | if (s->vectpending > NVIC_FIRST_IRQ) { |
| 111 | return true; |
| 112 | } |
| 113 | if (s->vectpending == 0) { |
| 114 | return false; |
| 115 | } |
| 116 | |
| 117 | for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { |
| 118 | if (s->vectors[irq].pending) { |
| 119 | return true; |
| 120 | } |
| 121 | } |
| 122 | return false; |
| 123 | } |
| 124 | |
| 125 | /* Return a mask word which clears the subpriority bits from |
| 126 | * a priority value for an M-profile exception, leaving only |
| 127 | * the group priority. |
| 128 | */ |
| 129 | static inline uint32_t nvic_gprio_mask(NVICState *s) |
| 130 | { |
| 131 | return ~0U << (s->prigroup + 1); |
| 132 | } |
| 133 | |
| 134 | /* Recompute vectpending and exception_prio */ |
| 135 | static void nvic_recompute_state(NVICState *s) |
| 136 | { |
| 137 | int i; |
| 138 | int pend_prio = NVIC_NOEXC_PRIO; |
| 139 | int active_prio = NVIC_NOEXC_PRIO; |
| 140 | int pend_irq = 0; |
| 141 | |
| 142 | for (i = 1; i < s->num_irq; i++) { |
| 143 | VecInfo *vec = &s->vectors[i]; |
| 144 | |
| 145 | if (vec->enabled && vec->pending && vec->prio < pend_prio) { |
| 146 | pend_prio = vec->prio; |
| 147 | pend_irq = i; |
| 148 | } |
| 149 | if (vec->active && vec->prio < active_prio) { |
| 150 | active_prio = vec->prio; |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | s->vectpending = pend_irq; |
| 155 | s->exception_prio = active_prio & nvic_gprio_mask(s); |
| 156 | |
| 157 | trace_nvic_recompute_state(s->vectpending, s->exception_prio); |
| 158 | } |
| 159 | |
| 160 | /* Return the current execution priority of the CPU |
| 161 | * (equivalent to the pseudocode ExecutionPriority function). |
| 162 | * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO. |
| 163 | */ |
| 164 | static inline int nvic_exec_prio(NVICState *s) |
| 165 | { |
| 166 | CPUARMState *env = &s->cpu->env; |
| 167 | int running; |
| 168 | |
| 169 | if (env->daif & PSTATE_F) { /* FAULTMASK */ |
| 170 | running = -1; |
| 171 | } else if (env->daif & PSTATE_I) { /* PRIMASK */ |
| 172 | running = 0; |
| 173 | } else if (env->v7m.basepri > 0) { |
| 174 | running = env->v7m.basepri & nvic_gprio_mask(s); |
| 175 | } else { |
| 176 | running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ |
| 177 | } |
| 178 | /* consider priority of active handler */ |
| 179 | return MIN(running, s->exception_prio); |
| 180 | } |
| 181 | |
Peter Maydell | 7ecdaa4 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 182 | bool armv7m_nvic_can_take_pending_exception(void *opaque) |
| 183 | { |
| 184 | NVICState *s = opaque; |
| 185 | |
| 186 | return nvic_exec_prio(s) > nvic_pending_prio(s); |
| 187 | } |
| 188 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 189 | /* caller must call nvic_irq_update() after this */ |
| 190 | static void set_prio(NVICState *s, unsigned irq, uint8_t prio) |
| 191 | { |
| 192 | assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ |
| 193 | assert(irq < s->num_irq); |
| 194 | |
| 195 | s->vectors[irq].prio = prio; |
| 196 | |
| 197 | trace_nvic_set_prio(irq, prio); |
| 198 | } |
| 199 | |
| 200 | /* Recompute state and assert irq line accordingly. |
| 201 | * Must be called after changes to: |
| 202 | * vec->active, vec->enabled, vec->pending or vec->prio for any vector |
| 203 | * prigroup |
| 204 | */ |
| 205 | static void nvic_irq_update(NVICState *s) |
| 206 | { |
| 207 | int lvl; |
| 208 | int pend_prio; |
| 209 | |
| 210 | nvic_recompute_state(s); |
| 211 | pend_prio = nvic_pending_prio(s); |
| 212 | |
| 213 | /* Raise NVIC output if this IRQ would be taken, except that we |
| 214 | * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which |
| 215 | * will be checked for in arm_v7m_cpu_exec_interrupt()); changes |
| 216 | * to those CPU registers don't cause us to recalculate the NVIC |
| 217 | * pending info. |
| 218 | */ |
| 219 | lvl = (pend_prio < s->exception_prio); |
| 220 | trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl); |
| 221 | qemu_set_irq(s->excpout, lvl); |
| 222 | } |
| 223 | |
| 224 | static void armv7m_nvic_clear_pending(void *opaque, int irq) |
| 225 | { |
| 226 | NVICState *s = (NVICState *)opaque; |
| 227 | VecInfo *vec; |
| 228 | |
| 229 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); |
| 230 | |
| 231 | vec = &s->vectors[irq]; |
| 232 | trace_nvic_clear_pending(irq, vec->enabled, vec->prio); |
| 233 | if (vec->pending) { |
| 234 | vec->pending = 0; |
| 235 | nvic_irq_update(s); |
| 236 | } |
| 237 | } |
| 238 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 239 | void armv7m_nvic_set_pending(void *opaque, int irq) |
| 240 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 241 | NVICState *s = (NVICState *)opaque; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 242 | VecInfo *vec; |
| 243 | |
| 244 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); |
| 245 | |
| 246 | vec = &s->vectors[irq]; |
| 247 | trace_nvic_set_pending(irq, vec->enabled, vec->prio); |
Michael Davidsaver | a73c98e | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 248 | |
| 249 | |
| 250 | if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { |
| 251 | /* If a synchronous exception is pending then it may be |
| 252 | * escalated to HardFault if: |
| 253 | * * it is equal or lower priority to current execution |
| 254 | * * it is disabled |
| 255 | * (ie we need to take it immediately but we can't do so). |
| 256 | * Asynchronous exceptions (and interrupts) simply remain pending. |
| 257 | * |
| 258 | * For QEMU, we don't have any imprecise (asynchronous) faults, |
| 259 | * so we can assume that PREFETCH_ABORT and DATA_ABORT are always |
| 260 | * synchronous. |
| 261 | * Debug exceptions are awkward because only Debug exceptions |
| 262 | * resulting from the BKPT instruction should be escalated, |
| 263 | * but we don't currently implement any Debug exceptions other |
| 264 | * than those that result from BKPT, so we treat all debug exceptions |
| 265 | * as needing escalation. |
| 266 | * |
| 267 | * This all means we can identify whether to escalate based only on |
| 268 | * the exception number and don't (yet) need the caller to explicitly |
| 269 | * tell us whether this exception is synchronous or not. |
| 270 | */ |
| 271 | int running = nvic_exec_prio(s); |
| 272 | bool escalate = false; |
| 273 | |
| 274 | if (vec->prio >= running) { |
| 275 | trace_nvic_escalate_prio(irq, vec->prio, running); |
| 276 | escalate = true; |
| 277 | } else if (!vec->enabled) { |
| 278 | trace_nvic_escalate_disabled(irq); |
| 279 | escalate = true; |
| 280 | } |
| 281 | |
| 282 | if (escalate) { |
| 283 | if (running < 0) { |
| 284 | /* We want to escalate to HardFault but we can't take a |
| 285 | * synchronous HardFault at this point either. This is a |
| 286 | * Lockup condition due to a guest bug. We don't model |
| 287 | * Lockup, so report via cpu_abort() instead. |
| 288 | */ |
| 289 | cpu_abort(&s->cpu->parent_obj, |
| 290 | "Lockup: can't escalate %d to HardFault " |
| 291 | "(current priority %d)\n", irq, running); |
| 292 | } |
| 293 | |
| 294 | /* We can do the escalation, so we take HardFault instead */ |
| 295 | irq = ARMV7M_EXCP_HARD; |
| 296 | vec = &s->vectors[irq]; |
| 297 | s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; |
| 298 | } |
| 299 | } |
| 300 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 301 | if (!vec->pending) { |
| 302 | vec->pending = 1; |
| 303 | nvic_irq_update(s); |
| 304 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* Make pending IRQ active. */ |
Peter Maydell | a5d8235 | 2017-02-28 12:08:18 +0000 | [diff] [blame] | 308 | void armv7m_nvic_acknowledge_irq(void *opaque) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 309 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 310 | NVICState *s = (NVICState *)opaque; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 311 | CPUARMState *env = &s->cpu->env; |
| 312 | const int pending = s->vectpending; |
| 313 | const int running = nvic_exec_prio(s); |
| 314 | int pendgroupprio; |
| 315 | VecInfo *vec; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 316 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 317 | assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); |
| 318 | |
| 319 | vec = &s->vectors[pending]; |
| 320 | |
| 321 | assert(vec->enabled); |
| 322 | assert(vec->pending); |
| 323 | |
| 324 | pendgroupprio = vec->prio & nvic_gprio_mask(s); |
| 325 | assert(pendgroupprio < running); |
| 326 | |
| 327 | trace_nvic_acknowledge_irq(pending, vec->prio); |
| 328 | |
| 329 | vec->active = 1; |
| 330 | vec->pending = 0; |
| 331 | |
| 332 | env->v7m.exception = s->vectpending; |
| 333 | |
| 334 | nvic_irq_update(s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 335 | } |
| 336 | |
Peter Maydell | aa488fe | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 337 | int armv7m_nvic_complete_irq(void *opaque, int irq) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 338 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 339 | NVICState *s = (NVICState *)opaque; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 340 | VecInfo *vec; |
Peter Maydell | aa488fe | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 341 | int ret; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 342 | |
| 343 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); |
| 344 | |
| 345 | vec = &s->vectors[irq]; |
| 346 | |
| 347 | trace_nvic_complete_irq(irq); |
| 348 | |
Peter Maydell | aa488fe | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 349 | if (!vec->active) { |
| 350 | /* Tell the caller this was an illegal exception return */ |
| 351 | return -1; |
| 352 | } |
| 353 | |
| 354 | ret = nvic_rettobase(s); |
| 355 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 356 | vec->active = 0; |
| 357 | if (vec->level) { |
| 358 | /* Re-pend the exception if it's still held high; only |
| 359 | * happens for extenal IRQs |
| 360 | */ |
| 361 | assert(irq >= NVIC_FIRST_IRQ); |
| 362 | vec->pending = 1; |
| 363 | } |
| 364 | |
| 365 | nvic_irq_update(s); |
Peter Maydell | aa488fe | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 366 | |
| 367 | return ret; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | /* callback when external interrupt line is changed */ |
| 371 | static void set_irq_level(void *opaque, int n, int level) |
| 372 | { |
| 373 | NVICState *s = opaque; |
| 374 | VecInfo *vec; |
| 375 | |
| 376 | n += NVIC_FIRST_IRQ; |
| 377 | |
| 378 | assert(n >= NVIC_FIRST_IRQ && n < s->num_irq); |
| 379 | |
| 380 | trace_nvic_set_irq_level(n, level); |
| 381 | |
| 382 | /* The pending status of an external interrupt is |
| 383 | * latched on rising edge and exception handler return. |
| 384 | * |
| 385 | * Pulsing the IRQ will always run the handler |
| 386 | * once, and the handler will re-run until the |
| 387 | * level is low when the handler completes. |
| 388 | */ |
| 389 | vec = &s->vectors[n]; |
| 390 | if (level != vec->level) { |
| 391 | vec->level = level; |
| 392 | if (level) { |
| 393 | armv7m_nvic_set_pending(s, n); |
| 394 | } |
| 395 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 396 | } |
| 397 | |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 398 | static uint32_t nvic_readl(NVICState *s, uint32_t offset) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 399 | { |
Michael Davidsaver | d713ea6 | 2017-01-27 15:20:22 +0000 | [diff] [blame] | 400 | ARMCPU *cpu = s->cpu; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 401 | uint32_t val; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 402 | |
| 403 | switch (offset) { |
| 404 | case 4: /* Interrupt Control Type. */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 405 | return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 406 | case 0xd00: /* CPUID Base. */ |
Rabin Vincent | e3da992 | 2014-05-01 15:24:44 +0100 | [diff] [blame] | 407 | return cpu->midr; |
Peter Maydell | e03ba13 | 2013-04-09 12:48:19 +0100 | [diff] [blame] | 408 | case 0xd04: /* Interrupt Control State. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 409 | /* VECTACTIVE */ |
Peter Maydell | b06c262 | 2015-09-08 17:38:42 +0100 | [diff] [blame] | 410 | val = cpu->env.v7m.exception; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 411 | /* VECTPENDING */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 412 | val |= (s->vectpending & 0xff) << 12; |
| 413 | /* ISRPENDING - set if any external IRQ is pending */ |
| 414 | if (nvic_isrpending(s)) { |
| 415 | val |= (1 << 22); |
| 416 | } |
| 417 | /* RETTOBASE - set if only one handler is active */ |
| 418 | if (nvic_rettobase(s)) { |
| 419 | val |= (1 << 11); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 420 | } |
| 421 | /* PENDSTSET */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 422 | if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 423 | val |= (1 << 26); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 424 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 425 | /* PENDSVSET */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 426 | if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 427 | val |= (1 << 28); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 428 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 429 | /* NMIPENDSET */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 430 | if (s->vectors[ARMV7M_EXCP_NMI].pending) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 431 | val |= (1 << 31); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 432 | } |
| 433 | /* ISRPREEMPT not implemented */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 434 | return val; |
| 435 | case 0xd08: /* Vector Table Offset. */ |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 436 | return cpu->env.v7m.vecbase; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 437 | case 0xd0c: /* Application Interrupt/Reset Control. */ |
Peter Maydell | 1004102 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 438 | return 0xfa050000 | (s->prigroup << 8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 439 | case 0xd10: /* System Control. */ |
| 440 | /* TODO: Implement SLEEPONEXIT. */ |
| 441 | return 0; |
| 442 | case 0xd14: /* Configuration Control. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 443 | return cpu->env.v7m.ccr; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 444 | case 0xd24: /* System Handler Status. */ |
| 445 | val = 0; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 446 | if (s->vectors[ARMV7M_EXCP_MEM].active) { |
| 447 | val |= (1 << 0); |
| 448 | } |
| 449 | if (s->vectors[ARMV7M_EXCP_BUS].active) { |
| 450 | val |= (1 << 1); |
| 451 | } |
| 452 | if (s->vectors[ARMV7M_EXCP_USAGE].active) { |
| 453 | val |= (1 << 3); |
| 454 | } |
| 455 | if (s->vectors[ARMV7M_EXCP_SVC].active) { |
| 456 | val |= (1 << 7); |
| 457 | } |
| 458 | if (s->vectors[ARMV7M_EXCP_DEBUG].active) { |
| 459 | val |= (1 << 8); |
| 460 | } |
| 461 | if (s->vectors[ARMV7M_EXCP_PENDSV].active) { |
| 462 | val |= (1 << 10); |
| 463 | } |
| 464 | if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { |
| 465 | val |= (1 << 11); |
| 466 | } |
| 467 | if (s->vectors[ARMV7M_EXCP_USAGE].pending) { |
| 468 | val |= (1 << 12); |
| 469 | } |
| 470 | if (s->vectors[ARMV7M_EXCP_MEM].pending) { |
| 471 | val |= (1 << 13); |
| 472 | } |
| 473 | if (s->vectors[ARMV7M_EXCP_BUS].pending) { |
| 474 | val |= (1 << 14); |
| 475 | } |
| 476 | if (s->vectors[ARMV7M_EXCP_SVC].pending) { |
| 477 | val |= (1 << 15); |
| 478 | } |
| 479 | if (s->vectors[ARMV7M_EXCP_MEM].enabled) { |
| 480 | val |= (1 << 16); |
| 481 | } |
| 482 | if (s->vectors[ARMV7M_EXCP_BUS].enabled) { |
| 483 | val |= (1 << 17); |
| 484 | } |
| 485 | if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { |
| 486 | val |= (1 << 18); |
| 487 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 488 | return val; |
| 489 | case 0xd28: /* Configurable Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 490 | return cpu->env.v7m.cfsr; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 491 | case 0xd2c: /* Hard Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 492 | return cpu->env.v7m.hfsr; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 493 | case 0xd30: /* Debug Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 494 | return cpu->env.v7m.dfsr; |
| 495 | case 0xd34: /* MMFAR MemManage Fault Address */ |
| 496 | return cpu->env.v7m.mmfar; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 497 | case 0xd38: /* Bus Fault Address. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 498 | return cpu->env.v7m.bfar; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 499 | case 0xd3c: /* Aux Fault Status. */ |
| 500 | /* TODO: Implement fault status registers. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 501 | qemu_log_mask(LOG_UNIMP, |
| 502 | "Aux Fault status registers unimplemented\n"); |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 503 | return 0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 504 | case 0xd40: /* PFR0. */ |
| 505 | return 0x00000030; |
| 506 | case 0xd44: /* PRF1. */ |
| 507 | return 0x00000200; |
| 508 | case 0xd48: /* DFR0. */ |
| 509 | return 0x00100000; |
| 510 | case 0xd4c: /* AFR0. */ |
| 511 | return 0x00000000; |
| 512 | case 0xd50: /* MMFR0. */ |
| 513 | return 0x00000030; |
| 514 | case 0xd54: /* MMFR1. */ |
| 515 | return 0x00000000; |
| 516 | case 0xd58: /* MMFR2. */ |
| 517 | return 0x00000000; |
| 518 | case 0xd5c: /* MMFR3. */ |
| 519 | return 0x00000000; |
| 520 | case 0xd60: /* ISAR0. */ |
| 521 | return 0x01141110; |
| 522 | case 0xd64: /* ISAR1. */ |
| 523 | return 0x02111000; |
| 524 | case 0xd68: /* ISAR2. */ |
| 525 | return 0x21112231; |
| 526 | case 0xd6c: /* ISAR3. */ |
| 527 | return 0x01111110; |
| 528 | case 0xd70: /* ISAR4. */ |
| 529 | return 0x01310102; |
| 530 | /* TODO: Implement debug registers. */ |
| 531 | default: |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 532 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); |
| 533 | return 0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 537 | static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 538 | { |
Michael Davidsaver | d713ea6 | 2017-01-27 15:20:22 +0000 | [diff] [blame] | 539 | ARMCPU *cpu = s->cpu; |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 540 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 541 | switch (offset) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 542 | case 0xd04: /* Interrupt Control State. */ |
| 543 | if (value & (1 << 31)) { |
| 544 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI); |
| 545 | } |
| 546 | if (value & (1 << 28)) { |
| 547 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV); |
| 548 | } else if (value & (1 << 27)) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 549 | armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 550 | } |
| 551 | if (value & (1 << 26)) { |
| 552 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); |
| 553 | } else if (value & (1 << 25)) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 554 | armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 555 | } |
| 556 | break; |
| 557 | case 0xd08: /* Vector Table Offset. */ |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 558 | cpu->env.v7m.vecbase = value & 0xffffff80; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 559 | break; |
| 560 | case 0xd0c: /* Application Interrupt/Reset Control. */ |
| 561 | if ((value >> 16) == 0x05fa) { |
Michael Davidsaver | e192bec | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 562 | if (value & 4) { |
| 563 | qemu_irq_pulse(s->sysresetreq); |
| 564 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 565 | if (value & 2) { |
Michael Davidsaver | 14790f7 | 2017-02-28 12:08:18 +0000 | [diff] [blame] | 566 | qemu_log_mask(LOG_GUEST_ERROR, |
| 567 | "Setting VECTCLRACTIVE when not in DEBUG mode " |
| 568 | "is UNPREDICTABLE\n"); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 569 | } |
Michael Davidsaver | e192bec | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 570 | if (value & 1) { |
Michael Davidsaver | 14790f7 | 2017-02-28 12:08:18 +0000 | [diff] [blame] | 571 | qemu_log_mask(LOG_GUEST_ERROR, |
| 572 | "Setting VECTRESET when not in DEBUG mode " |
| 573 | "is UNPREDICTABLE\n"); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 574 | } |
Peter Maydell | 1004102 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 575 | s->prigroup = extract32(value, 8, 3); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 576 | nvic_irq_update(s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 577 | } |
| 578 | break; |
| 579 | case 0xd10: /* System Control. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 580 | /* TODO: Implement control registers. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 581 | qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); |
| 582 | break; |
| 583 | case 0xd14: /* Configuration Control. */ |
| 584 | /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ |
| 585 | value &= (R_V7M_CCR_STKALIGN_MASK | |
| 586 | R_V7M_CCR_BFHFNMIGN_MASK | |
| 587 | R_V7M_CCR_DIV_0_TRP_MASK | |
| 588 | R_V7M_CCR_UNALIGN_TRP_MASK | |
| 589 | R_V7M_CCR_USERSETMPEND_MASK | |
| 590 | R_V7M_CCR_NONBASETHRDENA_MASK); |
| 591 | |
| 592 | cpu->env.v7m.ccr = value; |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 593 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 594 | case 0xd24: /* System Handler Control. */ |
Peter Maydell | 5db53e3 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 595 | s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; |
| 596 | s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; |
| 597 | s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; |
| 598 | s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; |
| 599 | s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; |
| 600 | s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; |
| 601 | s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; |
| 602 | s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; |
| 603 | s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; |
| 604 | s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; |
| 605 | s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 606 | s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; |
| 607 | s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; |
| 608 | s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; |
| 609 | nvic_irq_update(s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 610 | break; |
| 611 | case 0xd28: /* Configurable Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 612 | cpu->env.v7m.cfsr &= ~value; /* W1C */ |
| 613 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 614 | case 0xd2c: /* Hard Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 615 | cpu->env.v7m.hfsr &= ~value; /* W1C */ |
| 616 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 617 | case 0xd30: /* Debug Fault Status. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 618 | cpu->env.v7m.dfsr &= ~value; /* W1C */ |
| 619 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 620 | case 0xd34: /* Mem Manage Address. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 621 | cpu->env.v7m.mmfar = value; |
| 622 | return; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 623 | case 0xd38: /* Bus Fault Address. */ |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 624 | cpu->env.v7m.bfar = value; |
| 625 | return; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 626 | case 0xd3c: /* Aux Fault Status. */ |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 627 | qemu_log_mask(LOG_UNIMP, |
Michael Davidsaver | e6b3320 | 2017-01-27 15:20:23 +0000 | [diff] [blame] | 628 | "NVIC: Aux fault status registers unimplemented\n"); |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 629 | break; |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 630 | case 0xf00: /* Software Triggered Interrupt Register */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 631 | { |
Michael Davidsaver | bdd04fc | 2017-01-27 15:20:24 +0000 | [diff] [blame] | 632 | /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 633 | int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; |
| 634 | if (excnum < s->num_irq && |
Michael Davidsaver | bdd04fc | 2017-01-27 15:20:24 +0000 | [diff] [blame] | 635 | (arm_current_el(&cpu->env) || |
| 636 | (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 637 | armv7m_nvic_set_pending(s, excnum); |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 638 | } |
| 639 | break; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 640 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 641 | default: |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 642 | qemu_log_mask(LOG_GUEST_ERROR, |
| 643 | "NVIC: Bad write offset 0x%x\n", offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 644 | } |
| 645 | } |
| 646 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 647 | static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 648 | unsigned size) |
| 649 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 650 | NVICState *s = (NVICState *)opaque; |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 651 | uint32_t offset = addr; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 652 | unsigned i, startvec, end; |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 653 | uint32_t val; |
| 654 | |
| 655 | switch (offset) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 656 | /* reads of set and clear both return the status */ |
| 657 | case 0x100 ... 0x13f: /* NVIC Set enable */ |
| 658 | offset += 0x80; |
| 659 | /* fall through */ |
| 660 | case 0x180 ... 0x1bf: /* NVIC Clear enable */ |
| 661 | val = 0; |
| 662 | startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ |
| 663 | |
| 664 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
| 665 | if (s->vectors[startvec + i].enabled) { |
| 666 | val |= (1 << i); |
| 667 | } |
| 668 | } |
| 669 | break; |
| 670 | case 0x200 ... 0x23f: /* NVIC Set pend */ |
| 671 | offset += 0x80; |
| 672 | /* fall through */ |
| 673 | case 0x280 ... 0x2bf: /* NVIC Clear pend */ |
| 674 | val = 0; |
| 675 | startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ |
| 676 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
| 677 | if (s->vectors[startvec + i].pending) { |
| 678 | val |= (1 << i); |
| 679 | } |
| 680 | } |
| 681 | break; |
| 682 | case 0x300 ... 0x33f: /* NVIC Active */ |
| 683 | val = 0; |
| 684 | startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ |
| 685 | |
| 686 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
| 687 | if (s->vectors[startvec + i].active) { |
| 688 | val |= (1 << i); |
| 689 | } |
| 690 | } |
| 691 | break; |
| 692 | case 0x400 ... 0x5ef: /* NVIC Priority */ |
| 693 | val = 0; |
| 694 | startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */ |
| 695 | |
| 696 | for (i = 0; i < size && startvec + i < s->num_irq; i++) { |
| 697 | val |= s->vectors[startvec + i].prio << (8 * i); |
| 698 | } |
| 699 | break; |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 700 | case 0xd18 ... 0xd23: /* System Handler Priority. */ |
| 701 | val = 0; |
| 702 | for (i = 0; i < size; i++) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 703 | val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8); |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 704 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 705 | break; |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 706 | case 0xfe0 ... 0xfff: /* ID. */ |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 707 | if (offset & 3) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 708 | val = 0; |
| 709 | } else { |
| 710 | val = nvic_id[(offset - 0xfe0) >> 2]; |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 711 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 712 | break; |
| 713 | default: |
| 714 | if (size == 4) { |
| 715 | val = nvic_readl(s, offset); |
| 716 | } else { |
| 717 | qemu_log_mask(LOG_GUEST_ERROR, |
| 718 | "NVIC: Bad read of size %d at offset 0x%x\n", |
| 719 | size, offset); |
| 720 | val = 0; |
| 721 | } |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 722 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 723 | |
| 724 | trace_nvic_sysreg_read(addr, val, size); |
| 725 | return val; |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 726 | } |
| 727 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 728 | static void nvic_sysreg_write(void *opaque, hwaddr addr, |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 729 | uint64_t value, unsigned size) |
| 730 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 731 | NVICState *s = (NVICState *)opaque; |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 732 | uint32_t offset = addr; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 733 | unsigned i, startvec, end; |
| 734 | unsigned setval = 0; |
| 735 | |
| 736 | trace_nvic_sysreg_write(addr, value, size); |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 737 | |
| 738 | switch (offset) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 739 | case 0x100 ... 0x13f: /* NVIC Set enable */ |
| 740 | offset += 0x80; |
| 741 | setval = 1; |
| 742 | /* fall through */ |
| 743 | case 0x180 ... 0x1bf: /* NVIC Clear enable */ |
| 744 | startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; |
| 745 | |
| 746 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
| 747 | if (value & (1 << i)) { |
| 748 | s->vectors[startvec + i].enabled = setval; |
| 749 | } |
| 750 | } |
| 751 | nvic_irq_update(s); |
| 752 | return; |
| 753 | case 0x200 ... 0x23f: /* NVIC Set pend */ |
| 754 | /* the special logic in armv7m_nvic_set_pending() |
| 755 | * is not needed since IRQs are never escalated |
| 756 | */ |
| 757 | offset += 0x80; |
| 758 | setval = 1; |
| 759 | /* fall through */ |
| 760 | case 0x280 ... 0x2bf: /* NVIC Clear pend */ |
| 761 | startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ |
| 762 | |
| 763 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
| 764 | if (value & (1 << i)) { |
| 765 | s->vectors[startvec + i].pending = setval; |
| 766 | } |
| 767 | } |
| 768 | nvic_irq_update(s); |
| 769 | return; |
| 770 | case 0x300 ... 0x33f: /* NVIC Active */ |
| 771 | return; /* R/O */ |
| 772 | case 0x400 ... 0x5ef: /* NVIC Priority */ |
| 773 | startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ |
| 774 | |
| 775 | for (i = 0; i < size && startvec + i < s->num_irq; i++) { |
| 776 | set_prio(s, startvec + i, (value >> (i * 8)) & 0xff); |
| 777 | } |
| 778 | nvic_irq_update(s); |
| 779 | return; |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 780 | case 0xd18 ... 0xd23: /* System Handler Priority. */ |
| 781 | for (i = 0; i < size; i++) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 782 | unsigned hdlidx = (offset - 0xd14) + i; |
| 783 | set_prio(s, hdlidx, (value >> (i * 8)) & 0xff); |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 784 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 785 | nvic_irq_update(s); |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 786 | return; |
| 787 | } |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 788 | if (size == 4) { |
Andre Beckus | 0e8153d | 2012-10-30 07:45:07 +0000 | [diff] [blame] | 789 | nvic_writel(s, offset, value); |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 790 | return; |
| 791 | } |
Peter Maydell | e72e3ff | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 792 | qemu_log_mask(LOG_GUEST_ERROR, |
| 793 | "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 794 | } |
| 795 | |
| 796 | static const MemoryRegionOps nvic_sysreg_ops = { |
| 797 | .read = nvic_sysreg_read, |
| 798 | .write = nvic_sysreg_write, |
| 799 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 800 | }; |
| 801 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 802 | static int nvic_post_load(void *opaque, int version_id) |
| 803 | { |
| 804 | NVICState *s = opaque; |
| 805 | unsigned i; |
| 806 | |
| 807 | /* Check for out of range priority settings */ |
| 808 | if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 || |
| 809 | s->vectors[ARMV7M_EXCP_NMI].prio != -2 || |
| 810 | s->vectors[ARMV7M_EXCP_HARD].prio != -1) { |
| 811 | return 1; |
| 812 | } |
| 813 | for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) { |
| 814 | if (s->vectors[i].prio & ~0xff) { |
| 815 | return 1; |
| 816 | } |
| 817 | } |
| 818 | |
| 819 | nvic_recompute_state(s); |
| 820 | |
| 821 | return 0; |
| 822 | } |
| 823 | |
| 824 | static const VMStateDescription vmstate_VecInfo = { |
| 825 | .name = "armv7m_nvic_info", |
| 826 | .version_id = 1, |
| 827 | .minimum_version_id = 1, |
| 828 | .fields = (VMStateField[]) { |
| 829 | VMSTATE_INT16(prio, VecInfo), |
| 830 | VMSTATE_UINT8(enabled, VecInfo), |
| 831 | VMSTATE_UINT8(pending, VecInfo), |
| 832 | VMSTATE_UINT8(active, VecInfo), |
| 833 | VMSTATE_UINT8(level, VecInfo), |
| 834 | VMSTATE_END_OF_LIST() |
| 835 | } |
| 836 | }; |
| 837 | |
Juan Quintela | 0797226 | 2010-12-02 02:17:33 +0100 | [diff] [blame] | 838 | static const VMStateDescription vmstate_nvic = { |
| 839 | .name = "armv7m_nvic", |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 840 | .version_id = 4, |
| 841 | .minimum_version_id = 4, |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 842 | .post_load = &nvic_post_load, |
Juan Quintela | 8f1e884 | 2014-05-13 16:09:35 +0100 | [diff] [blame] | 843 | .fields = (VMStateField[]) { |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 844 | VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1, |
| 845 | vmstate_VecInfo, VecInfo), |
Peter Maydell | 1004102 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 846 | VMSTATE_UINT32(prigroup, NVICState), |
Juan Quintela | 0797226 | 2010-12-02 02:17:33 +0100 | [diff] [blame] | 847 | VMSTATE_END_OF_LIST() |
| 848 | } |
| 849 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 850 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 851 | static Property props_nvic[] = { |
| 852 | /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ |
| 853 | DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), |
| 854 | DEFINE_PROP_END_OF_LIST() |
| 855 | }; |
| 856 | |
Peter Maydell | aecff69 | 2012-04-13 11:39:09 +0000 | [diff] [blame] | 857 | static void armv7m_nvic_reset(DeviceState *dev) |
| 858 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 859 | NVICState *s = NVIC(dev); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 860 | |
| 861 | s->vectors[ARMV7M_EXCP_NMI].enabled = 1; |
| 862 | s->vectors[ARMV7M_EXCP_HARD].enabled = 1; |
| 863 | /* MEM, BUS, and USAGE are enabled through |
| 864 | * the System Handler Control register |
Peter Maydell | b3387ed | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 865 | */ |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 866 | s->vectors[ARMV7M_EXCP_SVC].enabled = 1; |
| 867 | s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; |
| 868 | s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; |
| 869 | s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; |
| 870 | |
| 871 | s->vectors[ARMV7M_EXCP_RESET].prio = -3; |
| 872 | s->vectors[ARMV7M_EXCP_NMI].prio = -2; |
| 873 | s->vectors[ARMV7M_EXCP_HARD].prio = -1; |
| 874 | |
| 875 | /* Strictly speaking the reset handler should be enabled. |
| 876 | * However, we don't simulate soft resets through the NVIC, |
| 877 | * and the reset vector should never be pended. |
| 878 | * So we leave it disabled to catch logic errors. |
| 879 | */ |
| 880 | |
| 881 | s->exception_prio = NVIC_NOEXC_PRIO; |
| 882 | s->vectpending = 0; |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 883 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 884 | |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 885 | static void nvic_systick_trigger(void *opaque, int n, int level) |
| 886 | { |
| 887 | NVICState *s = opaque; |
| 888 | |
| 889 | if (level) { |
| 890 | /* SysTick just asked us to pend its exception. |
| 891 | * (This is different from an external interrupt line's |
| 892 | * behaviour.) |
| 893 | */ |
| 894 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); |
| 895 | } |
Peter Maydell | aecff69 | 2012-04-13 11:39:09 +0000 | [diff] [blame] | 896 | } |
| 897 | |
Peter Maydell | 5311118 | 2013-03-05 00:34:42 +0000 | [diff] [blame] | 898 | static void armv7m_nvic_realize(DeviceState *dev, Error **errp) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 899 | { |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 900 | NVICState *s = NVIC(dev); |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 901 | SysBusDevice *systick_sbd; |
| 902 | Error *err = NULL; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 903 | |
Michael Davidsaver | d713ea6 | 2017-01-27 15:20:22 +0000 | [diff] [blame] | 904 | s->cpu = ARM_CPU(qemu_get_cpu(0)); |
| 905 | assert(s->cpu); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 906 | |
| 907 | if (s->num_irq > NVIC_MAX_IRQ) { |
| 908 | error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); |
Peter Maydell | 5311118 | 2013-03-05 00:34:42 +0000 | [diff] [blame] | 909 | return; |
| 910 | } |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 911 | |
| 912 | qdev_init_gpio_in(dev, set_irq_level, s->num_irq); |
| 913 | |
| 914 | /* include space for internal exception vectors */ |
| 915 | s->num_irq += NVIC_FIRST_IRQ; |
| 916 | |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 917 | object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); |
| 918 | if (err != NULL) { |
| 919 | error_propagate(errp, err); |
| 920 | return; |
| 921 | } |
| 922 | systick_sbd = SYS_BUS_DEVICE(&s->systick); |
| 923 | sysbus_connect_irq(systick_sbd, 0, |
| 924 | qdev_get_gpio_in_named(dev, "systick-trigger", 0)); |
| 925 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 926 | /* The NVIC and System Control Space (SCS) starts at 0xe000e000 |
| 927 | * and looks like this: |
| 928 | * 0x004 - ICTR |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 929 | * 0x010 - 0xff - systick |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 930 | * 0x100..0x7ec - NVIC |
| 931 | * 0x7f0..0xcff - Reserved |
| 932 | * 0xd00..0xd3c - SCS registers |
| 933 | * 0xd40..0xeff - Reserved or Not implemented |
| 934 | * 0xf00 - STIR |
| 935 | * |
| 936 | * At the moment there is only one thing in the container region, |
| 937 | * but we leave it in place to allow us to pull systick out into |
| 938 | * its own device object later. |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 939 | */ |
Paolo Bonzini | 1437c94 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 940 | memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 941 | /* The system register region goes at the bottom of the priority |
| 942 | * stack as it covers the whole page. |
| 943 | */ |
Paolo Bonzini | 1437c94 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 944 | memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, |
Peter Maydell | 2a29dde | 2012-05-02 16:49:39 +0000 | [diff] [blame] | 945 | "nvic_sysregs", 0x1000); |
| 946 | memory_region_add_subregion(&s->container, 0, &s->sysregmem); |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 947 | memory_region_add_subregion_overlap(&s->container, 0x10, |
| 948 | sysbus_mmio_get_region(systick_sbd, 0), |
| 949 | 1); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 950 | |
Peter Maydell | 98957a9 | 2017-02-20 15:36:00 +0000 | [diff] [blame] | 951 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 952 | } |
Paul Brook | fe7e875 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 953 | |
Peter Maydell | 55e00a1 | 2012-08-13 11:04:05 +0100 | [diff] [blame] | 954 | static void armv7m_nvic_instance_init(Object *obj) |
| 955 | { |
| 956 | /* We have a different default value for the num-irq property |
| 957 | * than our superclass. This function runs after qdev init |
| 958 | * has set the defaults from the Property array and before |
| 959 | * any user-specified property setting, so just modify the |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 960 | * value in the GICState struct. |
Peter Maydell | 55e00a1 | 2012-08-13 11:04:05 +0100 | [diff] [blame] | 961 | */ |
Michael Davidsaver | e192bec | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 962 | DeviceState *dev = DEVICE(obj); |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 963 | NVICState *nvic = NVIC(obj); |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 964 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 965 | |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 966 | object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); |
| 967 | qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); |
| 968 | |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 969 | sysbus_init_irq(sbd, &nvic->excpout); |
Michael Davidsaver | e192bec | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 970 | qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); |
Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame^] | 971 | qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1); |
Peter Maydell | 55e00a1 | 2012-08-13 11:04:05 +0100 | [diff] [blame] | 972 | } |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 973 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 974 | static void armv7m_nvic_class_init(ObjectClass *klass, void *data) |
| 975 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 976 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 977 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 978 | dc->vmsd = &vmstate_nvic; |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 979 | dc->props = props_nvic; |
Peter Maydell | aecff69 | 2012-04-13 11:39:09 +0000 | [diff] [blame] | 980 | dc->reset = armv7m_nvic_reset; |
Peter Maydell | 5311118 | 2013-03-05 00:34:42 +0000 | [diff] [blame] | 981 | dc->realize = armv7m_nvic_realize; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 982 | } |
| 983 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 984 | static const TypeInfo armv7m_nvic_info = { |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 985 | .name = TYPE_NVIC, |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 986 | .parent = TYPE_SYS_BUS_DEVICE, |
Peter Maydell | 55e00a1 | 2012-08-13 11:04:05 +0100 | [diff] [blame] | 987 | .instance_init = armv7m_nvic_instance_init, |
Peter Maydell | f797c07 | 2017-02-28 12:08:16 +0000 | [diff] [blame] | 988 | .instance_size = sizeof(NVICState), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 989 | .class_init = armv7m_nvic_class_init, |
Michael Davidsaver | da6d674 | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 990 | .class_size = sizeof(SysBusDeviceClass), |
Mark Langsdorf | a32134a | 2012-01-17 10:54:07 +0000 | [diff] [blame] | 991 | }; |
| 992 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 993 | static void armv7m_nvic_register_types(void) |
Paul Brook | fe7e875 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 994 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 995 | type_register_static(&armv7m_nvic_info); |
Paul Brook | fe7e875 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 996 | } |
| 997 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 998 | type_init(armv7m_nvic_register_types) |