blob: 086811e602122b91e40364d0d10f9bb453bb44d0 [file] [log] [blame]
John Snow1cd10312014-08-21 13:44:32 -04001/*
2 * AHCI test cases
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
Peter Maydell53239262016-01-26 18:17:09 +000025#include "qemu/osdep.h"
John Snow8840a842014-08-21 13:44:34 -040026#include <getopt.h>
John Snow1cd10312014-08-21 13:44:32 -040027
28#include "libqtest.h"
John Snow90e5add2015-01-19 15:15:55 -050029#include "libqos/libqos-pc.h"
John Snow90fc5e02015-01-19 15:15:50 -050030#include "libqos/ahci.h"
John Snow1cd10312014-08-21 13:44:32 -040031#include "libqos/pci-pc.h"
John Snow1cd10312014-08-21 13:44:32 -040032
33#include "qemu-common.h"
Markus Armbruster452fcdb2018-02-01 12:18:39 +010034#include "qapi/qmp/qdict.h"
John Snow1cd10312014-08-21 13:44:32 -040035#include "qemu/host-utils.h"
36
37#include "hw/pci/pci_ids.h"
38#include "hw/pci/pci_regs.h"
39
Markus Armbruster055a1ef2018-08-06 08:53:25 +020040/* TODO actually test the results and get rid of this */
Eric Blakea189a932017-09-11 12:20:02 -050041#define qmp_discard_response(s, ...) qobject_unref(qtest_qmp(s, __VA_ARGS__))
Markus Armbruster055a1ef2018-08-06 08:53:25 +020042
John Snow917158d2015-11-13 14:31:43 -050043/* Test images sizes in MB */
44#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
45#define TEST_IMAGE_SIZE_MB_SMALL 64
John Snow1cd10312014-08-21 13:44:32 -040046
John Snow1cd10312014-08-21 13:44:32 -040047/*** Globals ***/
John Snow1cd10312014-08-21 13:44:32 -040048static char tmp_path[] = "/tmp/qtest.XXXXXX";
John Snowcf5aa892015-04-28 15:27:51 -040049static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
John Snow6d9e7292015-11-13 14:31:42 -050050static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
John Snow8840a842014-08-21 13:44:34 -040051static bool ahci_pedantic;
John Snowb236b612015-11-13 14:31:42 -050052static const char *imgfmt;
John Snow917158d2015-11-13 14:31:43 -050053static unsigned test_image_size_mb;
John Snow8840a842014-08-21 13:44:34 -040054
John Snow1cd10312014-08-21 13:44:32 -040055/*** Function Declarations ***/
John Snow8d5eece2015-01-19 15:15:57 -050056static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
John Snow6100ddb2015-01-19 15:15:56 -050057static void ahci_test_pci_spec(AHCIQState *ahci);
58static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
John Snow8840a842014-08-21 13:44:34 -040059 uint8_t offset);
John Snow6100ddb2015-01-19 15:15:56 -050060static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
61static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
62static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
John Snow1cd10312014-08-21 13:44:32 -040063
64/*** Utilities ***/
65
John Snow917158d2015-11-13 14:31:43 -050066static uint64_t mb_to_sectors(uint64_t image_size_mb)
67{
68 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
69}
70
John Snow0fa781e2014-08-21 13:44:39 -040071static void string_bswap16(uint16_t *s, size_t bytes)
72{
73 g_assert_cmphex((bytes & 1), ==, 0);
74 bytes /= 2;
75
76 while (bytes--) {
77 *s = bswap16(*s);
78 s++;
79 }
80}
81
John Snow278128a2015-05-22 14:13:43 -040082/**
83 * Verify that the transfer did not corrupt our state at all.
84 */
David Gibsone7c85262016-10-24 15:50:22 +110085static void verify_state(AHCIQState *ahci, uint64_t hba_old)
John Snow278128a2015-05-22 14:13:43 -040086{
87 int i, j;
88 uint32_t ahci_fingerprint;
89 uint64_t hba_base;
John Snow278128a2015-05-22 14:13:43 -040090 AHCICommandHeader cmd;
91
92 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
93 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
94
95 /* If we haven't initialized, this is as much as can be validated. */
David Gibsone7c85262016-10-24 15:50:22 +110096 if (!ahci->enabled) {
John Snow278128a2015-05-22 14:13:43 -040097 return;
98 }
99
100 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
David Gibsone7c85262016-10-24 15:50:22 +1100101 g_assert_cmphex(hba_base, ==, hba_old);
John Snow278128a2015-05-22 14:13:43 -0400102
103 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
104 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
105
106 for (i = 0; i < 32; i++) {
107 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
108 ahci->port[i].fb);
109 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
110 ahci->port[i].clb);
111 for (j = 0; j < 32; j++) {
112 ahci_get_command_header(ahci, i, j, &cmd);
113 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
114 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
115 }
116 }
117}
118
119static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
120{
121 QOSState *tmp = to->parent;
122 QPCIDevice *dev = to->dev;
John Snow6d9e7292015-11-13 14:31:42 -0500123 char *uri_local = NULL;
David Gibsone7c85262016-10-24 15:50:22 +1100124 uint64_t hba_old;
John Snow6d9e7292015-11-13 14:31:42 -0500125
John Snow278128a2015-05-22 14:13:43 -0400126 if (uri == NULL) {
John Snow6d9e7292015-11-13 14:31:42 -0500127 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
128 uri = uri_local;
John Snow278128a2015-05-22 14:13:43 -0400129 }
130
David Gibsone7c85262016-10-24 15:50:22 +1100131 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
132
John Snow278128a2015-05-22 14:13:43 -0400133 /* context will be 'to' after completion. */
134 migrate(from->parent, to->parent, uri);
135
136 /* We'd like for the AHCIState objects to still point
137 * to information specific to its specific parent
138 * instance, but otherwise just inherit the new data. */
139 memcpy(to, from, sizeof(AHCIQState));
140 to->parent = tmp;
141 to->dev = dev;
142
143 tmp = from->parent;
144 dev = from->dev;
145 memset(from, 0x00, sizeof(AHCIQState));
146 from->parent = tmp;
147 from->dev = dev;
148
David Gibsone7c85262016-10-24 15:50:22 +1100149 verify_state(to, hba_old);
John Snow6d9e7292015-11-13 14:31:42 -0500150 g_free(uri_local);
John Snow278128a2015-05-22 14:13:43 -0400151}
152
John Snow1cd10312014-08-21 13:44:32 -0400153/*** Test Setup & Teardown ***/
154
155/**
John Snow1cd10312014-08-21 13:44:32 -0400156 * Start a Q35 machine and bookmark a handle to the AHCI device.
157 */
John Snowdebaaa12015-04-28 15:27:51 -0400158static AHCIQState *ahci_vboot(const char *cli, va_list ap)
John Snow1cd10312014-08-21 13:44:32 -0400159{
John Snowdd0029c2015-01-19 15:15:51 -0500160 AHCIQState *s;
John Snowdd0029c2015-01-19 15:15:51 -0500161
Marc-André Lureau790bbb92017-10-06 20:49:56 -0300162 s = g_new0(AHCIQState, 1);
John Snowdebaaa12015-04-28 15:27:51 -0400163 s->parent = qtest_pc_vboot(cli, ap);
Paolo Bonzinieb5937b2018-11-29 12:37:04 +0100164 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT);
John Snow1cd10312014-08-21 13:44:32 -0400165
166 /* Verify that we have an AHCI device present. */
Eric Blakee5d17302017-09-11 12:19:52 -0500167 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
John Snowdd0029c2015-01-19 15:15:51 -0500168
John Snowdd0029c2015-01-19 15:15:51 -0500169 return s;
John Snow1cd10312014-08-21 13:44:32 -0400170}
171
172/**
John Snowdebaaa12015-04-28 15:27:51 -0400173 * Start a Q35 machine and bookmark a handle to the AHCI device.
174 */
175static AHCIQState *ahci_boot(const char *cli, ...)
176{
177 AHCIQState *s;
178 va_list ap;
179
180 if (cli) {
181 va_start(ap, cli);
182 s = ahci_vboot(cli, ap);
183 va_end(ap);
184 } else {
Kevin Wolf572023f2018-06-13 11:01:30 +0200185 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
John Snowdebaaa12015-04-28 15:27:51 -0400186 " -M q35 "
187 "-device ide-hd,drive=drive0 "
Kevin Wolf572023f2018-06-13 11:01:30 +0200188 "-global ide-hd.serial=%s "
John Snowdebaaa12015-04-28 15:27:51 -0400189 "-global ide-hd.ver=%s";
Kevin Wolf572023f2018-06-13 11:01:30 +0200190 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version");
John Snowdebaaa12015-04-28 15:27:51 -0400191 }
192
193 return s;
194}
195
196/**
John Snow1cd10312014-08-21 13:44:32 -0400197 * Clean up the PCI device, then terminate the QEMU instance.
198 */
John Snowdd0029c2015-01-19 15:15:51 -0500199static void ahci_shutdown(AHCIQState *ahci)
John Snow1cd10312014-08-21 13:44:32 -0400200{
John Snowdd0029c2015-01-19 15:15:51 -0500201 QOSState *qs = ahci->parent;
John Snow278128a2015-05-22 14:13:43 -0400202
Eric Blakea189a932017-09-11 12:20:02 -0500203 assert(!global_qtest);
John Snow259342d2015-02-05 12:41:28 -0500204 ahci_clean_mem(ahci);
John Snowdd0029c2015-01-19 15:15:51 -0500205 free_ahci_device(ahci->dev);
206 g_free(ahci);
207 qtest_shutdown(qs);
John Snow1cd10312014-08-21 13:44:32 -0400208}
209
John Snowd63b4012015-02-25 18:06:36 -0500210/**
211 * Boot and fully enable the HBA device.
212 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
213 */
John Snowdebaaa12015-04-28 15:27:51 -0400214static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
John Snowd63b4012015-02-25 18:06:36 -0500215{
216 AHCIQState *ahci;
John Snowdebaaa12015-04-28 15:27:51 -0400217 va_list ap;
John Snow34475232015-07-04 02:06:03 -0400218 uint16_t buff[256];
219 uint8_t port;
John Snowd0b282a2016-01-11 14:10:42 -0500220 uint8_t hello;
John Snowdebaaa12015-04-28 15:27:51 -0400221
222 if (cli) {
223 va_start(ap, cli);
224 ahci = ahci_vboot(cli, ap);
225 va_end(ap);
226 } else {
227 ahci = ahci_boot(NULL);
228 }
John Snowd63b4012015-02-25 18:06:36 -0500229
230 ahci_pci_enable(ahci);
231 ahci_hba_enable(ahci);
John Snow34475232015-07-04 02:06:03 -0400232 /* Initialize test device */
233 port = ahci_port_select(ahci);
234 ahci_port_clear(ahci, port);
John Snowd0b282a2016-01-11 14:10:42 -0500235 if (is_atapi(ahci, port)) {
236 hello = CMD_PACKET_ID;
237 } else {
238 hello = CMD_IDENTIFY;
239 }
240 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
John Snowd63b4012015-02-25 18:06:36 -0500241
242 return ahci;
243}
244
John Snow8840a842014-08-21 13:44:34 -0400245/*** Specification Adherence Tests ***/
246
247/**
248 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
249 */
John Snow6100ddb2015-01-19 15:15:56 -0500250static void ahci_test_pci_spec(AHCIQState *ahci)
John Snow8840a842014-08-21 13:44:34 -0400251{
252 uint8_t datab;
253 uint16_t data;
254 uint32_t datal;
255
256 /* Most of these bits should start cleared until we turn them on. */
John Snow6100ddb2015-01-19 15:15:56 -0500257 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
John Snow8840a842014-08-21 13:44:34 -0400258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
265 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
266 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
267 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
268
John Snow6100ddb2015-01-19 15:15:56 -0500269 data = qpci_config_readw(ahci->dev, PCI_STATUS);
John Snow8840a842014-08-21 13:44:34 -0400270 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
272 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
278 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
279 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
280
281 /* RID occupies the low byte, CCs occupy the high three. */
John Snow6100ddb2015-01-19 15:15:56 -0500282 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
John Snow8840a842014-08-21 13:44:34 -0400283 if (ahci_pedantic) {
284 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
285 * Though in practice this is likely seldom true. */
286 ASSERT_BIT_CLEAR(datal, 0xFF);
287 }
288
289 /* BCC *must* equal 0x01. */
290 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
291 if (PCI_SCC(datal) == 0x01) {
292 /* IDE */
293 ASSERT_BIT_SET(0x80000000, datal);
294 ASSERT_BIT_CLEAR(0x60000000, datal);
295 } else if (PCI_SCC(datal) == 0x04) {
296 /* RAID */
297 g_assert_cmphex(PCI_PI(datal), ==, 0);
298 } else if (PCI_SCC(datal) == 0x06) {
299 /* AHCI */
300 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
301 } else {
302 g_assert_not_reached();
303 }
304
John Snow6100ddb2015-01-19 15:15:56 -0500305 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
John Snow8840a842014-08-21 13:44:34 -0400306 g_assert_cmphex(datab, ==, 0);
307
John Snow6100ddb2015-01-19 15:15:56 -0500308 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
John Snow8840a842014-08-21 13:44:34 -0400309 g_assert_cmphex(datab, ==, 0);
310
311 /* Only the bottom 7 bits must be off. */
John Snow6100ddb2015-01-19 15:15:56 -0500312 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
John Snow8840a842014-08-21 13:44:34 -0400313 ASSERT_BIT_CLEAR(datab, 0x7F);
314
315 /* BIST is optional, but the low 7 bits must always start off regardless. */
John Snow6100ddb2015-01-19 15:15:56 -0500316 datab = qpci_config_readb(ahci->dev, PCI_BIST);
John Snow8840a842014-08-21 13:44:34 -0400317 ASSERT_BIT_CLEAR(datab, 0x7F);
318
319 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
John Snow6100ddb2015-01-19 15:15:56 -0500320 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
John Snow8840a842014-08-21 13:44:34 -0400321 g_assert_cmphex(datal, ==, 0);
322
John Snow6100ddb2015-01-19 15:15:56 -0500323 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
324 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
John Snow8840a842014-08-21 13:44:34 -0400325 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
326 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
327 ASSERT_BIT_CLEAR(datal, 0xFF);
328
329 /* Capability list MUST be present, */
John Snow6100ddb2015-01-19 15:15:56 -0500330 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
John Snow8840a842014-08-21 13:44:34 -0400331 /* But these bits are reserved. */
332 ASSERT_BIT_CLEAR(datal, ~0xFF);
333 g_assert_cmphex(datal, !=, 0);
334
335 /* Check specification adherence for capability extenstions. */
John Snow6100ddb2015-01-19 15:15:56 -0500336 data = qpci_config_readw(ahci->dev, datal);
John Snow8840a842014-08-21 13:44:34 -0400337
John Snow8d5eece2015-01-19 15:15:57 -0500338 switch (ahci->fingerprint) {
John Snow8840a842014-08-21 13:44:34 -0400339 case AHCI_INTEL_ICH9:
340 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
341 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
342 break;
343 default:
344 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
345 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
346 }
347
348 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
349
350 /* Reserved. */
John Snow6100ddb2015-01-19 15:15:56 -0500351 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
John Snow8840a842014-08-21 13:44:34 -0400352 g_assert_cmphex(datal, ==, 0);
353
354 /* IPIN might vary, but ILINE must be off. */
John Snow6100ddb2015-01-19 15:15:56 -0500355 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
John Snow8840a842014-08-21 13:44:34 -0400356 g_assert_cmphex(datab, ==, 0);
357}
358
359/**
360 * Test PCI capabilities for AHCI specification adherence.
361 */
John Snow6100ddb2015-01-19 15:15:56 -0500362static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
John Snow8840a842014-08-21 13:44:34 -0400363 uint8_t offset)
364{
365 uint8_t cid = header & 0xFF;
366 uint8_t next = header >> 8;
367
368 g_test_message("CID: %02x; next: %02x", cid, next);
369
370 switch (cid) {
371 case PCI_CAP_ID_PM:
372 ahci_test_pmcap(ahci, offset);
373 break;
374 case PCI_CAP_ID_MSI:
375 ahci_test_msicap(ahci, offset);
376 break;
377 case PCI_CAP_ID_SATA:
378 ahci_test_satacap(ahci, offset);
379 break;
380
381 default:
382 g_test_message("Unknown CAP 0x%02x", cid);
383 }
384
385 if (next) {
John Snow6100ddb2015-01-19 15:15:56 -0500386 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
John Snow8840a842014-08-21 13:44:34 -0400387 }
388}
389
390/**
391 * Test SATA PCI capabilitity for AHCI specification adherence.
392 */
John Snow6100ddb2015-01-19 15:15:56 -0500393static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
John Snow8840a842014-08-21 13:44:34 -0400394{
395 uint16_t dataw;
396 uint32_t datal;
397
398 g_test_message("Verifying SATACAP");
399
400 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
John Snow6100ddb2015-01-19 15:15:56 -0500401 dataw = qpci_config_readw(ahci->dev, offset + 2);
John Snow8840a842014-08-21 13:44:34 -0400402 g_assert_cmphex(dataw, ==, 0x10);
403
404 /* Grab the SATACR1 register. */
John Snow6100ddb2015-01-19 15:15:56 -0500405 datal = qpci_config_readw(ahci->dev, offset + 4);
John Snow8840a842014-08-21 13:44:34 -0400406
407 switch (datal & 0x0F) {
408 case 0x04: /* BAR0 */
409 case 0x05: /* BAR1 */
410 case 0x06:
411 case 0x07:
412 case 0x08:
413 case 0x09: /* BAR5 */
414 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
415 break;
416 default:
417 /* Invalid BARLOC for the Index Data Pair. */
418 g_assert_not_reached();
419 }
420
421 /* Reserved. */
422 g_assert_cmphex((datal >> 24), ==, 0x00);
423}
424
425/**
426 * Test MSI PCI capability for AHCI specification adherence.
427 */
John Snow6100ddb2015-01-19 15:15:56 -0500428static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
John Snow8840a842014-08-21 13:44:34 -0400429{
430 uint16_t dataw;
431 uint32_t datal;
432
433 g_test_message("Verifying MSICAP");
434
John Snow6100ddb2015-01-19 15:15:56 -0500435 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
John Snow8840a842014-08-21 13:44:34 -0400436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
437 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
438 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
439
John Snow6100ddb2015-01-19 15:15:56 -0500440 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
John Snow8840a842014-08-21 13:44:34 -0400441 g_assert_cmphex(datal, ==, 0);
442
443 if (dataw & PCI_MSI_FLAGS_64BIT) {
444 g_test_message("MSICAP is 64bit");
John Snow6100ddb2015-01-19 15:15:56 -0500445 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
John Snow8840a842014-08-21 13:44:34 -0400446 g_assert_cmphex(datal, ==, 0);
John Snow6100ddb2015-01-19 15:15:56 -0500447 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
John Snow8840a842014-08-21 13:44:34 -0400448 g_assert_cmphex(dataw, ==, 0);
449 } else {
450 g_test_message("MSICAP is 32bit");
John Snow6100ddb2015-01-19 15:15:56 -0500451 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
John Snow8840a842014-08-21 13:44:34 -0400452 g_assert_cmphex(dataw, ==, 0);
453 }
454}
455
456/**
457 * Test Power Management PCI capability for AHCI specification adherence.
458 */
John Snow6100ddb2015-01-19 15:15:56 -0500459static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
John Snow8840a842014-08-21 13:44:34 -0400460{
461 uint16_t dataw;
462
463 g_test_message("Verifying PMCAP");
464
John Snow6100ddb2015-01-19 15:15:56 -0500465 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
John Snow8840a842014-08-21 13:44:34 -0400466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
468 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
469 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
470
John Snow6100ddb2015-01-19 15:15:56 -0500471 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
John Snow8840a842014-08-21 13:44:34 -0400472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
474 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
475 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
476}
477
John Snow6100ddb2015-01-19 15:15:56 -0500478static void ahci_test_hba_spec(AHCIQState *ahci)
John Snowc2f30292014-08-21 13:44:37 -0400479{
John Snowc2f30292014-08-21 13:44:37 -0400480 unsigned i;
John Snow8d5eece2015-01-19 15:15:57 -0500481 uint32_t reg;
John Snowc2f30292014-08-21 13:44:37 -0400482 uint32_t ports;
483 uint8_t nports_impl;
484 uint8_t maxports;
485
John Snow6100ddb2015-01-19 15:15:56 -0500486 g_assert(ahci != NULL);
John Snowc2f30292014-08-21 13:44:37 -0400487
488 /*
489 * Note that the AHCI spec does expect the BIOS to set up a few things:
490 * CAP.SSS - Support for staggered spin-up (t/f)
491 * CAP.SMPS - Support for mechanical presence switches (t/f)
492 * PI - Ports Implemented (1-32)
493 * PxCMD.HPCP - Hot Plug Capable Port
494 * PxCMD.MPSP - Mechanical Presence Switch Present
495 * PxCMD.CPD - Cold Presence Detection support
496 *
497 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
498 * Foreach Port Implemented:
499 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
500 * -PxCLB/U and PxFB/U are set to valid regions in memory
501 * -PxSUD is set to 1.
502 * -PxSSTS.DET is polled for presence; if detected, we continue:
503 * -PxSERR is cleared with 1's.
504 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
505 * the device is ready.
506 */
507
508 /* 1 CAP - Capabilities Register */
John Snow1a8bba42015-01-19 15:16:01 -0500509 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
John Snow8d5eece2015-01-19 15:15:57 -0500510 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
John Snowc2f30292014-08-21 13:44:37 -0400511
512 /* 2 GHC - Global Host Control */
John Snow1a8bba42015-01-19 15:16:01 -0500513 reg = ahci_rreg(ahci, AHCI_GHC);
John Snowc2f30292014-08-21 13:44:37 -0400514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
515 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
516 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
John Snow8d5eece2015-01-19 15:15:57 -0500517 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
John Snowc2f30292014-08-21 13:44:37 -0400518 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
519 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
520 } else {
521 g_test_message("Supports AHCI/Legacy mix.");
522 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
523 }
524
525 /* 3 IS - Interrupt Status */
John Snow1a8bba42015-01-19 15:16:01 -0500526 reg = ahci_rreg(ahci, AHCI_IS);
John Snowc2f30292014-08-21 13:44:37 -0400527 g_assert_cmphex(reg, ==, 0);
528
529 /* 4 PI - Ports Implemented */
John Snow1a8bba42015-01-19 15:16:01 -0500530 ports = ahci_rreg(ahci, AHCI_PI);
John Snowc2f30292014-08-21 13:44:37 -0400531 /* Ports Implemented must be non-zero. */
532 g_assert_cmphex(ports, !=, 0);
533 /* Ports Implemented must be <= Number of Ports. */
534 nports_impl = ctpopl(ports);
John Snow8d5eece2015-01-19 15:15:57 -0500535 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
John Snowc2f30292014-08-21 13:44:37 -0400536
John Snowc2f30292014-08-21 13:44:37 -0400537 /* Ports must be within the proper range. Given a mapping of SIZE,
538 * 256 bytes are used for global HBA control, and the rest is used
539 * for ports data, at 0x80 bytes each. */
John Snow8d5eece2015-01-19 15:15:57 -0500540 g_assert_cmphex(ahci->barsize, >, 0);
541 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
John Snowc2f30292014-08-21 13:44:37 -0400542 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
543 g_assert_cmphex((reg >> maxports), ==, 0);
544
545 /* 5 AHCI Version */
John Snow1a8bba42015-01-19 15:16:01 -0500546 reg = ahci_rreg(ahci, AHCI_VS);
John Snowc2f30292014-08-21 13:44:37 -0400547 switch (reg) {
548 case AHCI_VERSION_0_95:
549 case AHCI_VERSION_1_0:
550 case AHCI_VERSION_1_1:
551 case AHCI_VERSION_1_2:
552 case AHCI_VERSION_1_3:
553 break;
554 default:
555 g_assert_not_reached();
556 }
557
558 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
John Snow1a8bba42015-01-19 15:16:01 -0500559 reg = ahci_rreg(ahci, AHCI_CCCCTL);
John Snow8d5eece2015-01-19 15:15:57 -0500560 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
John Snowc2f30292014-08-21 13:44:37 -0400561 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
562 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
563 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
564 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
565 } else {
566 g_assert_cmphex(reg, ==, 0);
567 }
568
569 /* 7 CCC_PORTS */
John Snow1a8bba42015-01-19 15:16:01 -0500570 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
John Snowc2f30292014-08-21 13:44:37 -0400571 /* Must be zeroes initially regardless of CAP.CCCS */
572 g_assert_cmphex(reg, ==, 0);
573
574 /* 8 EM_LOC */
John Snow1a8bba42015-01-19 15:16:01 -0500575 reg = ahci_rreg(ahci, AHCI_EMLOC);
John Snow8d5eece2015-01-19 15:15:57 -0500576 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
John Snowc2f30292014-08-21 13:44:37 -0400577 g_assert_cmphex(reg, ==, 0);
578 }
579
580 /* 9 EM_CTL */
John Snow1a8bba42015-01-19 15:16:01 -0500581 reg = ahci_rreg(ahci, AHCI_EMCTL);
John Snow8d5eece2015-01-19 15:15:57 -0500582 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
John Snowc2f30292014-08-21 13:44:37 -0400583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
585 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
586 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
587 } else {
588 g_assert_cmphex(reg, ==, 0);
589 }
590
591 /* 10 CAP2 -- Capabilities Extended */
John Snow1a8bba42015-01-19 15:16:01 -0500592 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
John Snow8d5eece2015-01-19 15:15:57 -0500593 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
John Snowc2f30292014-08-21 13:44:37 -0400594
595 /* 11 BOHC -- Bios/OS Handoff Control */
John Snow1a8bba42015-01-19 15:16:01 -0500596 reg = ahci_rreg(ahci, AHCI_BOHC);
John Snowc2f30292014-08-21 13:44:37 -0400597 g_assert_cmphex(reg, ==, 0);
598
599 /* 12 -- 23: Reserved */
600 g_test_message("Verifying HBA reserved area is empty.");
601 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
John Snow1a8bba42015-01-19 15:16:01 -0500602 reg = ahci_rreg(ahci, i);
John Snowc2f30292014-08-21 13:44:37 -0400603 g_assert_cmphex(reg, ==, 0);
604 }
605
606 /* 24 -- 39: NVMHCI */
John Snow8d5eece2015-01-19 15:15:57 -0500607 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
John Snowc2f30292014-08-21 13:44:37 -0400608 g_test_message("Verifying HBA/NVMHCI area is empty.");
609 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
John Snow1a8bba42015-01-19 15:16:01 -0500610 reg = ahci_rreg(ahci, i);
John Snowc2f30292014-08-21 13:44:37 -0400611 g_assert_cmphex(reg, ==, 0);
612 }
613 }
614
615 /* 40 -- 63: Vendor */
616 g_test_message("Verifying HBA/Vendor area is empty.");
617 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
John Snow1a8bba42015-01-19 15:16:01 -0500618 reg = ahci_rreg(ahci, i);
John Snowc2f30292014-08-21 13:44:37 -0400619 g_assert_cmphex(reg, ==, 0);
620 }
621
622 /* 64 -- XX: Port Space */
John Snowc2f30292014-08-21 13:44:37 -0400623 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
624 if (BITSET(ports, 0x1)) {
625 g_test_message("Testing port %u for spec", i);
John Snow8d5eece2015-01-19 15:15:57 -0500626 ahci_test_port_spec(ahci, i);
John Snowc2f30292014-08-21 13:44:37 -0400627 } else {
628 uint16_t j;
629 uint16_t low = AHCI_PORTS + (32 * i);
630 uint16_t high = AHCI_PORTS + (32 * (i + 1));
631 g_test_message("Asserting unimplemented port %u "
632 "(reg [%u-%u]) is empty.",
633 i, low, high - 1);
634 for (j = low; j < high; ++j) {
John Snow1a8bba42015-01-19 15:16:01 -0500635 reg = ahci_rreg(ahci, j);
John Snowc2f30292014-08-21 13:44:37 -0400636 g_assert_cmphex(reg, ==, 0);
637 }
638 }
639 }
640}
641
642/**
643 * Test the memory space for one port for specification adherence.
644 */
John Snow8d5eece2015-01-19 15:15:57 -0500645static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
John Snowc2f30292014-08-21 13:44:37 -0400646{
647 uint32_t reg;
648 unsigned i;
649
650 /* (0) CLB */
John Snow1a8bba42015-01-19 15:16:01 -0500651 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
John Snowc2f30292014-08-21 13:44:37 -0400652 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
653
654 /* (1) CLBU */
John Snow8d5eece2015-01-19 15:15:57 -0500655 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
John Snow1a8bba42015-01-19 15:16:01 -0500656 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
John Snowc2f30292014-08-21 13:44:37 -0400657 g_assert_cmphex(reg, ==, 0);
658 }
659
660 /* (2) FB */
John Snow1a8bba42015-01-19 15:16:01 -0500661 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
John Snowc2f30292014-08-21 13:44:37 -0400662 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
663
664 /* (3) FBU */
John Snow8d5eece2015-01-19 15:15:57 -0500665 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
John Snow1a8bba42015-01-19 15:16:01 -0500666 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
John Snowc2f30292014-08-21 13:44:37 -0400667 g_assert_cmphex(reg, ==, 0);
668 }
669
670 /* (4) IS */
John Snow1a8bba42015-01-19 15:16:01 -0500671 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
John Snowc2f30292014-08-21 13:44:37 -0400672 g_assert_cmphex(reg, ==, 0);
673
674 /* (5) IE */
John Snow1a8bba42015-01-19 15:16:01 -0500675 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
John Snowc2f30292014-08-21 13:44:37 -0400676 g_assert_cmphex(reg, ==, 0);
677
678 /* (6) CMD */
John Snow1a8bba42015-01-19 15:16:01 -0500679 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
John Snowc2f30292014-08-21 13:44:37 -0400680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
690 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
691 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
692 /* If CPDetect support does not exist, CPState must be off. */
693 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
694 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
695 }
696 /* If MPSPresence is not set, MPSState must be off. */
697 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
698 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
699 }
700 /* If we do not support MPS, MPSS and MPSP must be off. */
John Snow8d5eece2015-01-19 15:15:57 -0500701 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
John Snowc2f30292014-08-21 13:44:37 -0400702 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
703 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
704 }
705 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
John Snow7e7d49d2015-03-17 16:58:19 -0400706 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
John Snowc2f30292014-08-21 13:44:37 -0400707 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
708 }
709 /* HPCP and ESP cannot both be active. */
710 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
711 /* If CAP.FBSS is not set, FBSCP must not be set. */
John Snow8d5eece2015-01-19 15:15:57 -0500712 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
John Snowc2f30292014-08-21 13:44:37 -0400713 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
714 }
715
716 /* (7) RESERVED */
John Snow1a8bba42015-01-19 15:16:01 -0500717 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
John Snowc2f30292014-08-21 13:44:37 -0400718 g_assert_cmphex(reg, ==, 0);
719
720 /* (8) TFD */
John Snow1a8bba42015-01-19 15:16:01 -0500721 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
John Snowc2f30292014-08-21 13:44:37 -0400722 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
723 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
726 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
727 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
729 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
730 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
731
732 /* (9) SIG */
733 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
734 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
735 * D2H register FIS and update the signature asynchronously,
736 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
737
738 /* (10) SSTS / SCR0: SStatus */
John Snow1a8bba42015-01-19 15:16:01 -0500739 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
John Snowc2f30292014-08-21 13:44:37 -0400740 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
741 /* Even though the register should be 0 at boot, it is asynchronous and
742 * prone to change, so we cannot test any well known value. */
743
744 /* (11) SCTL / SCR2: SControl */
John Snow1a8bba42015-01-19 15:16:01 -0500745 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
John Snowc2f30292014-08-21 13:44:37 -0400746 g_assert_cmphex(reg, ==, 0);
747
748 /* (12) SERR / SCR1: SError */
John Snow1a8bba42015-01-19 15:16:01 -0500749 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
John Snowc2f30292014-08-21 13:44:37 -0400750 g_assert_cmphex(reg, ==, 0);
751
752 /* (13) SACT / SCR3: SActive */
John Snow1a8bba42015-01-19 15:16:01 -0500753 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
John Snowc2f30292014-08-21 13:44:37 -0400754 g_assert_cmphex(reg, ==, 0);
755
756 /* (14) CI */
John Snow1a8bba42015-01-19 15:16:01 -0500757 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
John Snowc2f30292014-08-21 13:44:37 -0400758 g_assert_cmphex(reg, ==, 0);
759
760 /* (15) SNTF */
John Snow1a8bba42015-01-19 15:16:01 -0500761 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
John Snowc2f30292014-08-21 13:44:37 -0400762 g_assert_cmphex(reg, ==, 0);
763
764 /* (16) FBS */
John Snow1a8bba42015-01-19 15:16:01 -0500765 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
John Snowc2f30292014-08-21 13:44:37 -0400766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
770 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
771 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
John Snow8d5eece2015-01-19 15:15:57 -0500772 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
John Snowc2f30292014-08-21 13:44:37 -0400773 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
774 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
775 }
776
777 /* [17 -- 27] RESERVED */
778 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
John Snow1a8bba42015-01-19 15:16:01 -0500779 reg = ahci_px_rreg(ahci, port, i);
John Snowc2f30292014-08-21 13:44:37 -0400780 g_assert_cmphex(reg, ==, 0);
781 }
782
783 /* [28 -- 31] Vendor-Specific */
784 for (i = AHCI_PX_VS; i < 32; ++i) {
John Snow1a8bba42015-01-19 15:16:01 -0500785 reg = ahci_px_rreg(ahci, port, i);
John Snowc2f30292014-08-21 13:44:37 -0400786 if (reg) {
787 g_test_message("INFO: Vendor register %u non-empty", i);
788 }
789 }
790}
791
John Snow0fa781e2014-08-21 13:44:39 -0400792/**
793 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
794 * device we see, then read and check the response.
795 */
John Snow6100ddb2015-01-19 15:15:56 -0500796static void ahci_test_identify(AHCIQState *ahci)
John Snow0fa781e2014-08-21 13:44:39 -0400797{
John Snow0fa781e2014-08-21 13:44:39 -0400798 uint16_t buff[256];
John Snowae029622015-02-05 12:41:27 -0500799 unsigned px;
John Snow0fa781e2014-08-21 13:44:39 -0400800 int rc;
John Snow122482a2015-02-05 12:41:29 -0500801 uint16_t sect_size;
John Snowae029622015-02-05 12:41:27 -0500802 const size_t buffsize = 512;
John Snow0fa781e2014-08-21 13:44:39 -0400803
804 g_assert(ahci != NULL);
John Snow0fa781e2014-08-21 13:44:39 -0400805
John Snowae029622015-02-05 12:41:27 -0500806 /**
807 * This serves as a bit of a tutorial on AHCI device programming:
808 *
809 * (1) Create a data buffer for the IDENTIFY response to be sent to
810 * (2) Create a Command Table buffer, where we will store the
811 * command and PRDT (Physical Region Descriptor Table)
John Snow64a5a272015-02-05 12:41:23 -0500812 * (3) Construct an FIS host-to-device command structure, and write it to
John Snowae029622015-02-05 12:41:27 -0500813 * the top of the Command Table buffer.
814 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
815 * a location in memory where data may be stored/retrieved.
816 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
817 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
818 * header that points to a Command Table buffer. Pick an unused slot
819 * and update it to point to the Command Table we have built.
820 * (7) Now: Command #n points to our Command Table, and our Command Table
821 * contains the FIS (that describes our command) and the PRDTL, which
822 * describes our buffer.
823 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
824 * #n is ready for processing.
John Snow0fa781e2014-08-21 13:44:39 -0400825 */
826
827 /* Pick the first implemented and running port */
John Snowae029622015-02-05 12:41:27 -0500828 px = ahci_port_select(ahci);
829 g_test_message("Selected port %u for test", px);
John Snow0fa781e2014-08-21 13:44:39 -0400830
John Snowe83fd962015-02-05 12:41:13 -0500831 /* Clear out the FIS Receive area and any pending interrupts. */
John Snowae029622015-02-05 12:41:27 -0500832 ahci_port_clear(ahci, px);
John Snow0fa781e2014-08-21 13:44:39 -0400833
John Snowae029622015-02-05 12:41:27 -0500834 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
John Snow727be1a2015-04-28 15:27:51 -0400835 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
John Snow0fa781e2014-08-21 13:44:39 -0400836
837 /* Check serial number/version in the buffer */
838 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
839 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
840 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
841 * as a consequence, only needs to unchunk the data on LE machines. */
842 string_bswap16(&buff[10], 20);
843 rc = memcmp(&buff[10], "testdisk ", 20);
844 g_assert_cmphex(rc, ==, 0);
845
846 string_bswap16(&buff[23], 8);
847 rc = memcmp(&buff[23], "version ", 8);
848 g_assert_cmphex(rc, ==, 0);
John Snow122482a2015-02-05 12:41:29 -0500849
850 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
John Snow727be1a2015-04-28 15:27:51 -0400851 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
John Snow0fa781e2014-08-21 13:44:39 -0400852}
853
John Snowbda39dc2015-02-25 18:06:39 -0500854static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
John Snow727be1a2015-04-28 15:27:51 -0400855 uint64_t sector, uint8_t read_cmd,
856 uint8_t write_cmd)
John Snow81705ee2015-02-05 12:41:30 -0500857{
858 uint64_t ptr;
859 uint8_t port;
John Snow81705ee2015-02-05 12:41:30 -0500860 unsigned char *tx = g_malloc(bufsize);
861 unsigned char *rx = g_malloc0(bufsize);
862
863 g_assert(ahci != NULL);
864
865 /* Pick the first running port and clear it. */
866 port = ahci_port_select(ahci);
867 ahci_port_clear(ahci, port);
868
869 /*** Create pattern and transfer to guest ***/
870 /* Data buffer in the guest */
871 ptr = ahci_alloc(ahci, bufsize);
872 g_assert(ptr);
873
John Snowd6c403e2015-02-25 18:06:38 -0500874 /* Write some indicative pattern to our buffer. */
John Snow54fced02015-03-19 20:24:16 -0400875 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
Eric Blakea189a932017-09-11 12:20:02 -0500876 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
John Snow81705ee2015-02-05 12:41:30 -0500877
878 /* Write this buffer to disk, then read it back to the DMA buffer. */
John Snow727be1a2015-04-28 15:27:51 -0400879 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
Eric Blakea189a932017-09-11 12:20:02 -0500880 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
John Snow727be1a2015-04-28 15:27:51 -0400881 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
John Snow81705ee2015-02-05 12:41:30 -0500882
883 /*** Read back the Data ***/
Eric Blakea189a932017-09-11 12:20:02 -0500884 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
John Snow81705ee2015-02-05 12:41:30 -0500885 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
886
887 ahci_free(ahci, ptr);
888 g_free(tx);
889 g_free(rx);
890}
891
John Snow0d3e9d12015-07-04 02:06:02 -0400892static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
John Snow4e217072015-04-28 15:27:51 -0400893{
John Snow0d3e9d12015-07-04 02:06:02 -0400894 uint8_t port;
John Snow4e217072015-04-28 15:27:51 -0400895
896 /* Sanitize */
John Snow0d3e9d12015-07-04 02:06:02 -0400897 port = ahci_port_select(ahci);
898 ahci_port_clear(ahci, port);
John Snow4e217072015-04-28 15:27:51 -0400899
John Snowb1b66c32016-01-11 14:10:43 -0500900 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
John Snow0d3e9d12015-07-04 02:06:02 -0400901
902 return port;
John Snow4e217072015-04-28 15:27:51 -0400903}
904
905static void ahci_test_flush(AHCIQState *ahci)
906{
907 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
908}
909
John Snow0d3e9d12015-07-04 02:06:02 -0400910static void ahci_test_max(AHCIQState *ahci)
911{
912 RegD2HFIS *d2h = g_malloc0(0x20);
913 uint64_t nsect;
914 uint8_t port;
915 uint8_t cmd;
John Snow917158d2015-11-13 14:31:43 -0500916 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
John Snow0d3e9d12015-07-04 02:06:02 -0400917
918 if (config_sect > 0xFFFFFF) {
919 cmd = CMD_READ_MAX_EXT;
920 } else {
921 cmd = CMD_READ_MAX;
922 }
923
924 port = ahci_test_nondata(ahci, cmd);
Eric Blakea189a932017-09-11 12:20:02 -0500925 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
John Snow0d3e9d12015-07-04 02:06:02 -0400926 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
927 (uint64_t)d2h->lba_hi[1] << 32 |
928 (uint64_t)d2h->lba_hi[0] << 24 |
929 (uint64_t)d2h->lba_lo[2] << 16 |
930 (uint64_t)d2h->lba_lo[1] << 8 |
931 (uint64_t)d2h->lba_lo[0];
932
933 g_assert_cmphex(nsect, ==, config_sect);
934 g_free(d2h);
935}
936
John Snow4e217072015-04-28 15:27:51 -0400937
John Snow1cd10312014-08-21 13:44:32 -0400938/******************************************************************************/
939/* Test Interfaces */
940/******************************************************************************/
941
942/**
943 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
944 */
945static void test_sanity(void)
946{
John Snowdd0029c2015-01-19 15:15:51 -0500947 AHCIQState *ahci;
John Snowdebaaa12015-04-28 15:27:51 -0400948 ahci = ahci_boot(NULL);
John Snow1cd10312014-08-21 13:44:32 -0400949 ahci_shutdown(ahci);
950}
951
John Snow8840a842014-08-21 13:44:34 -0400952/**
953 * Ensure that the PCI configuration space for the AHCI device is in-line with
954 * the AHCI 1.3 specification for initial values.
955 */
956static void test_pci_spec(void)
957{
John Snowdd0029c2015-01-19 15:15:51 -0500958 AHCIQState *ahci;
John Snowdebaaa12015-04-28 15:27:51 -0400959 ahci = ahci_boot(NULL);
John Snow6100ddb2015-01-19 15:15:56 -0500960 ahci_test_pci_spec(ahci);
John Snow8840a842014-08-21 13:44:34 -0400961 ahci_shutdown(ahci);
962}
963
John Snow96d6d3b2014-08-21 13:44:35 -0400964/**
965 * Engage the PCI AHCI device and sanity check the response.
966 * Perform additional PCI config space bringup for the HBA.
967 */
968static void test_pci_enable(void)
969{
John Snowdd0029c2015-01-19 15:15:51 -0500970 AHCIQState *ahci;
John Snowdebaaa12015-04-28 15:27:51 -0400971 ahci = ahci_boot(NULL);
John Snow6100ddb2015-01-19 15:15:56 -0500972 ahci_pci_enable(ahci);
John Snow96d6d3b2014-08-21 13:44:35 -0400973 ahci_shutdown(ahci);
974}
975
John Snowc2f30292014-08-21 13:44:37 -0400976/**
977 * Investigate the memory mapped regions of the HBA,
978 * and test them for AHCI specification adherence.
979 */
980static void test_hba_spec(void)
981{
John Snowdd0029c2015-01-19 15:15:51 -0500982 AHCIQState *ahci;
John Snowc2f30292014-08-21 13:44:37 -0400983
John Snowdebaaa12015-04-28 15:27:51 -0400984 ahci = ahci_boot(NULL);
John Snow6100ddb2015-01-19 15:15:56 -0500985 ahci_pci_enable(ahci);
986 ahci_test_hba_spec(ahci);
John Snowc2f30292014-08-21 13:44:37 -0400987 ahci_shutdown(ahci);
988}
989
John Snowdbc180e2014-08-21 13:44:38 -0400990/**
991 * Engage the HBA functionality of the AHCI PCI device,
992 * and bring it into a functional idle state.
993 */
994static void test_hba_enable(void)
995{
John Snowdd0029c2015-01-19 15:15:51 -0500996 AHCIQState *ahci;
John Snowdbc180e2014-08-21 13:44:38 -0400997
John Snowdebaaa12015-04-28 15:27:51 -0400998 ahci = ahci_boot(NULL);
John Snow6100ddb2015-01-19 15:15:56 -0500999 ahci_pci_enable(ahci);
1000 ahci_hba_enable(ahci);
John Snowdbc180e2014-08-21 13:44:38 -04001001 ahci_shutdown(ahci);
1002}
1003
John Snow0fa781e2014-08-21 13:44:39 -04001004/**
1005 * Bring up the device and issue an IDENTIFY command.
1006 * Inspect the state of the HBA device and the data returned.
1007 */
1008static void test_identify(void)
1009{
John Snowdd0029c2015-01-19 15:15:51 -05001010 AHCIQState *ahci;
John Snow0fa781e2014-08-21 13:44:39 -04001011
John Snowdebaaa12015-04-28 15:27:51 -04001012 ahci = ahci_boot_and_enable(NULL);
John Snow6100ddb2015-01-19 15:15:56 -05001013 ahci_test_identify(ahci);
John Snow0fa781e2014-08-21 13:44:39 -04001014 ahci_shutdown(ahci);
1015}
1016
John Snowe0c59cc2015-02-25 18:06:40 -05001017/**
1018 * Fragmented DMA test: Perform a standard 4K DMA read/write
1019 * test, but make sure the physical regions are fragmented to
1020 * be very small, each just 32 bytes, to see how AHCI performs
1021 * with chunks defined to be much less than a sector.
1022 */
1023static void test_dma_fragmented(void)
1024{
1025 AHCIQState *ahci;
1026 AHCICommand *cmd;
1027 uint8_t px;
1028 size_t bufsize = 4096;
1029 unsigned char *tx = g_malloc(bufsize);
1030 unsigned char *rx = g_malloc0(bufsize);
John Snowe0c59cc2015-02-25 18:06:40 -05001031 uint64_t ptr;
1032
John Snowdebaaa12015-04-28 15:27:51 -04001033 ahci = ahci_boot_and_enable(NULL);
John Snowe0c59cc2015-02-25 18:06:40 -05001034 px = ahci_port_select(ahci);
1035 ahci_port_clear(ahci, px);
1036
1037 /* create pattern */
John Snow54fced02015-03-19 20:24:16 -04001038 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
John Snowe0c59cc2015-02-25 18:06:40 -05001039
1040 /* Create a DMA buffer in guest memory, and write our pattern to it. */
Paolo Bonzinieb5937b2018-11-29 12:37:04 +01001041 ptr = guest_alloc(&ahci->parent->alloc, bufsize);
John Snowe0c59cc2015-02-25 18:06:40 -05001042 g_assert(ptr);
Eric Blakea189a932017-09-11 12:20:02 -05001043 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
John Snowe0c59cc2015-02-25 18:06:40 -05001044
1045 cmd = ahci_command_create(CMD_WRITE_DMA);
1046 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1047 ahci_command_commit(ahci, cmd, px);
1048 ahci_command_issue(ahci, cmd);
1049 ahci_command_verify(ahci, cmd);
John Snow248de4a2016-01-11 14:10:42 -05001050 ahci_command_free(cmd);
John Snowe0c59cc2015-02-25 18:06:40 -05001051
1052 cmd = ahci_command_create(CMD_READ_DMA);
1053 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1054 ahci_command_commit(ahci, cmd, px);
1055 ahci_command_issue(ahci, cmd);
1056 ahci_command_verify(ahci, cmd);
John Snow248de4a2016-01-11 14:10:42 -05001057 ahci_command_free(cmd);
John Snowe0c59cc2015-02-25 18:06:40 -05001058
1059 /* Read back the guest's receive buffer into local memory */
Eric Blakea189a932017-09-11 12:20:02 -05001060 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
Paolo Bonzinieb5937b2018-11-29 12:37:04 +01001061 guest_free(&ahci->parent->alloc, ptr);
John Snowe0c59cc2015-02-25 18:06:40 -05001062
1063 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1064
1065 ahci_shutdown(ahci);
1066
1067 g_free(rx);
1068 g_free(tx);
1069}
1070
Evgeny Yakovlev2dd7e102016-07-18 22:39:51 +03001071/*
1072 * Write sector 1 with random data to make AHCI storage dirty
1073 * Needed for flush tests so that flushes actually go though the block layer
1074 */
1075static void make_dirty(AHCIQState* ahci, uint8_t port)
1076{
1077 uint64_t ptr;
1078 unsigned bufsize = 512;
1079
1080 ptr = ahci_alloc(ahci, bufsize);
1081 g_assert(ptr);
1082
1083 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1084 ahci_free(ahci, ptr);
1085}
1086
John Snow4e217072015-04-28 15:27:51 -04001087static void test_flush(void)
1088{
1089 AHCIQState *ahci;
Evgeny Yakovlev2dd7e102016-07-18 22:39:51 +03001090 uint8_t port;
John Snow4e217072015-04-28 15:27:51 -04001091
John Snowdebaaa12015-04-28 15:27:51 -04001092 ahci = ahci_boot_and_enable(NULL);
Evgeny Yakovlev2dd7e102016-07-18 22:39:51 +03001093
1094 port = ahci_port_select(ahci);
1095 ahci_port_clear(ahci, port);
1096
1097 make_dirty(ahci, port);
1098
John Snow4e217072015-04-28 15:27:51 -04001099 ahci_test_flush(ahci);
1100 ahci_shutdown(ahci);
1101}
1102
John Snowcf5aa892015-04-28 15:27:51 -04001103static void test_flush_retry(void)
1104{
1105 AHCIQState *ahci;
1106 AHCICommand *cmd;
1107 uint8_t port;
John Snowcf5aa892015-04-28 15:27:51 -04001108
1109 prepare_blkdebug_script(debug_path, "flush_to_disk");
1110 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001111 "format=%s,cache=writeback,"
John Snowcf5aa892015-04-28 15:27:51 -04001112 "rerror=stop,werror=stop "
1113 "-M q35 "
1114 "-device ide-hd,drive=drive0 ",
1115 debug_path,
John Snowb236b612015-11-13 14:31:42 -05001116 tmp_path, imgfmt);
John Snowcf5aa892015-04-28 15:27:51 -04001117
John Snowcf5aa892015-04-28 15:27:51 -04001118 port = ahci_port_select(ahci);
1119 ahci_port_clear(ahci, port);
John Snowcf5aa892015-04-28 15:27:51 -04001120
Evgeny Yakovlev2dd7e102016-07-18 22:39:51 +03001121 /* Issue write so that flush actually goes to disk */
1122 make_dirty(ahci, port);
1123
1124 /* Issue Flush Command and wait for error */
John Snowb682d3a2016-01-11 14:10:43 -05001125 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1126 ahci_guest_io_resume(ahci, cmd);
John Snowcf5aa892015-04-28 15:27:51 -04001127
John Snowcf5aa892015-04-28 15:27:51 -04001128 ahci_shutdown(ahci);
1129}
1130
John Snow278128a2015-05-22 14:13:43 -04001131/**
1132 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1133 */
1134static void test_migrate_sanity(void)
1135{
1136 AHCIQState *src, *dst;
John Snow6d9e7292015-11-13 14:31:42 -05001137 char *uri = g_strdup_printf("unix:%s", mig_socket);
John Snow278128a2015-05-22 14:13:43 -04001138
Dr. David Alan Gilbertff0ca962017-07-18 11:47:57 -04001139 src = ahci_boot("-m 384 -M q35 "
John Snowb236b612015-11-13 14:31:42 -05001140 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
Dr. David Alan Gilbertff0ca962017-07-18 11:47:57 -04001141 dst = ahci_boot("-m 384 -M q35 "
John Snowb236b612015-11-13 14:31:42 -05001142 "-drive if=ide,file=%s,format=%s "
1143 "-incoming %s", tmp_path, imgfmt, uri);
John Snow278128a2015-05-22 14:13:43 -04001144
1145 ahci_migrate(src, dst, uri);
1146
1147 ahci_shutdown(src);
1148 ahci_shutdown(dst);
John Snow6d9e7292015-11-13 14:31:42 -05001149 g_free(uri);
John Snow278128a2015-05-22 14:13:43 -04001150}
1151
John Snow88e21f92015-05-22 14:13:43 -04001152/**
John Snow07a1ee72015-07-04 02:06:04 -04001153 * Simple migration test: Write a pattern, migrate, then read.
John Snow88e21f92015-05-22 14:13:43 -04001154 */
John Snow07a1ee72015-07-04 02:06:04 -04001155static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
John Snow88e21f92015-05-22 14:13:43 -04001156{
1157 AHCIQState *src, *dst;
1158 uint8_t px;
1159 size_t bufsize = 4096;
1160 unsigned char *tx = g_malloc(bufsize);
1161 unsigned char *rx = g_malloc0(bufsize);
John Snow6d9e7292015-11-13 14:31:42 -05001162 char *uri = g_strdup_printf("unix:%s", mig_socket);
John Snow88e21f92015-05-22 14:13:43 -04001163
Dr. David Alan Gilbertff0ca962017-07-18 11:47:57 -04001164 src = ahci_boot_and_enable("-m 384 -M q35 "
John Snowb236b612015-11-13 14:31:42 -05001165 "-drive if=ide,format=%s,file=%s ",
1166 imgfmt, tmp_path);
Dr. David Alan Gilbertff0ca962017-07-18 11:47:57 -04001167 dst = ahci_boot("-m 384 -M q35 "
John Snowb236b612015-11-13 14:31:42 -05001168 "-drive if=ide,format=%s,file=%s "
1169 "-incoming %s", imgfmt, tmp_path, uri);
John Snow88e21f92015-05-22 14:13:43 -04001170
John Snow88e21f92015-05-22 14:13:43 -04001171 /* initialize */
1172 px = ahci_port_select(src);
1173 ahci_port_clear(src, px);
1174
1175 /* create pattern */
John Snowd7531632015-09-17 14:17:04 -04001176 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
John Snow88e21f92015-05-22 14:13:43 -04001177
1178 /* Write, migrate, then read. */
John Snow07a1ee72015-07-04 02:06:04 -04001179 ahci_io(src, px, cmd_write, tx, bufsize, 0);
John Snow88e21f92015-05-22 14:13:43 -04001180 ahci_migrate(src, dst, uri);
John Snow07a1ee72015-07-04 02:06:04 -04001181 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
John Snow88e21f92015-05-22 14:13:43 -04001182
1183 /* Verify pattern */
1184 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1185
1186 ahci_shutdown(src);
1187 ahci_shutdown(dst);
1188 g_free(rx);
1189 g_free(tx);
John Snow6d9e7292015-11-13 14:31:42 -05001190 g_free(uri);
John Snow88e21f92015-05-22 14:13:43 -04001191}
1192
John Snow07a1ee72015-07-04 02:06:04 -04001193static void test_migrate_dma(void)
1194{
1195 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1196}
1197
1198static void test_migrate_ncq(void)
1199{
1200 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1201}
1202
John Snowa606ce52015-05-22 14:13:43 -04001203/**
John Snow7f6cf5e2015-07-04 02:06:05 -04001204 * Halted IO Error Test
John Snow189d1b62015-05-22 14:13:43 -04001205 *
1206 * Simulate an error on first write, Try to write a pattern,
1207 * Confirm the VM has stopped, resume the VM, verify command
1208 * has completed, then read back the data and verify.
1209 */
John Snow7f6cf5e2015-07-04 02:06:05 -04001210static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
John Snow189d1b62015-05-22 14:13:43 -04001211{
1212 AHCIQState *ahci;
1213 uint8_t port;
1214 size_t bufsize = 4096;
1215 unsigned char *tx = g_malloc(bufsize);
1216 unsigned char *rx = g_malloc0(bufsize);
John Snow189d1b62015-05-22 14:13:43 -04001217 uint64_t ptr;
1218 AHCICommand *cmd;
1219
1220 prepare_blkdebug_script(debug_path, "write_aio");
1221
1222 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001223 "format=%s,cache=writeback,"
John Snow189d1b62015-05-22 14:13:43 -04001224 "rerror=stop,werror=stop "
1225 "-M q35 "
1226 "-device ide-hd,drive=drive0 ",
1227 debug_path,
John Snowb236b612015-11-13 14:31:42 -05001228 tmp_path, imgfmt);
John Snow189d1b62015-05-22 14:13:43 -04001229
1230 /* Initialize and prepare */
1231 port = ahci_port_select(ahci);
1232 ahci_port_clear(ahci, port);
1233
John Snow189d1b62015-05-22 14:13:43 -04001234 /* create DMA source buffer and write pattern */
John Snowd7531632015-09-17 14:17:04 -04001235 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
John Snow189d1b62015-05-22 14:13:43 -04001236 ptr = ahci_alloc(ahci, bufsize);
1237 g_assert(ptr);
Eric Blakea189a932017-09-11 12:20:02 -05001238 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize);
John Snow189d1b62015-05-22 14:13:43 -04001239
1240 /* Attempt to write (and fail) */
John Snow7f6cf5e2015-07-04 02:06:05 -04001241 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
John Snow189d1b62015-05-22 14:13:43 -04001242 ptr, bufsize, 0);
1243
1244 /* Attempt to resume the command */
1245 ahci_guest_io_resume(ahci, cmd);
1246 ahci_free(ahci, ptr);
1247
1248 /* Read back and verify */
John Snow7f6cf5e2015-07-04 02:06:05 -04001249 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
John Snow189d1b62015-05-22 14:13:43 -04001250 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1251
1252 /* Cleanup and go home */
1253 ahci_shutdown(ahci);
1254 g_free(rx);
1255 g_free(tx);
1256}
1257
John Snow7f6cf5e2015-07-04 02:06:05 -04001258static void test_halted_dma(void)
1259{
1260 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1261}
1262
1263static void test_halted_ncq(void)
1264{
1265 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1266}
1267
John Snow189d1b62015-05-22 14:13:43 -04001268/**
John Snow8146d7d2015-07-04 02:06:05 -04001269 * IO Error Migration Test
John Snow5d1cf092015-05-22 14:13:43 -04001270 *
1271 * Simulate an error on first write, Try to write a pattern,
1272 * Confirm the VM has stopped, migrate, resume the VM,
1273 * verify command has completed, then read back the data and verify.
1274 */
John Snow8146d7d2015-07-04 02:06:05 -04001275static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
John Snow5d1cf092015-05-22 14:13:43 -04001276{
1277 AHCIQState *src, *dst;
1278 uint8_t port;
1279 size_t bufsize = 4096;
1280 unsigned char *tx = g_malloc(bufsize);
1281 unsigned char *rx = g_malloc0(bufsize);
John Snow5d1cf092015-05-22 14:13:43 -04001282 uint64_t ptr;
1283 AHCICommand *cmd;
John Snow6d9e7292015-11-13 14:31:42 -05001284 char *uri = g_strdup_printf("unix:%s", mig_socket);
John Snow5d1cf092015-05-22 14:13:43 -04001285
1286 prepare_blkdebug_script(debug_path, "write_aio");
1287
1288 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001289 "format=%s,cache=writeback,"
John Snow5d1cf092015-05-22 14:13:43 -04001290 "rerror=stop,werror=stop "
1291 "-M q35 "
1292 "-device ide-hd,drive=drive0 ",
1293 debug_path,
John Snowb236b612015-11-13 14:31:42 -05001294 tmp_path, imgfmt);
John Snow5d1cf092015-05-22 14:13:43 -04001295
1296 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001297 "format=%s,cache=writeback,"
John Snow5d1cf092015-05-22 14:13:43 -04001298 "rerror=stop,werror=stop "
1299 "-M q35 "
1300 "-device ide-hd,drive=drive0 "
1301 "-incoming %s",
John Snowb236b612015-11-13 14:31:42 -05001302 tmp_path, imgfmt, uri);
John Snow5d1cf092015-05-22 14:13:43 -04001303
John Snow5d1cf092015-05-22 14:13:43 -04001304 /* Initialize and prepare */
1305 port = ahci_port_select(src);
1306 ahci_port_clear(src, port);
John Snowd7531632015-09-17 14:17:04 -04001307 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
John Snow5d1cf092015-05-22 14:13:43 -04001308
1309 /* create DMA source buffer and write pattern */
1310 ptr = ahci_alloc(src, bufsize);
1311 g_assert(ptr);
Eric Blakea189a932017-09-11 12:20:02 -05001312 qtest_memwrite(src->parent->qts, ptr, tx, bufsize);
John Snow5d1cf092015-05-22 14:13:43 -04001313
1314 /* Write, trigger the VM to stop, migrate, then resume. */
John Snow8146d7d2015-07-04 02:06:05 -04001315 cmd = ahci_guest_io_halt(src, port, cmd_write,
John Snow5d1cf092015-05-22 14:13:43 -04001316 ptr, bufsize, 0);
1317 ahci_migrate(src, dst, uri);
1318 ahci_guest_io_resume(dst, cmd);
1319 ahci_free(dst, ptr);
1320
1321 /* Read back */
John Snow8146d7d2015-07-04 02:06:05 -04001322 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
John Snow5d1cf092015-05-22 14:13:43 -04001323
1324 /* Verify TX and RX are identical */
1325 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1326
1327 /* Cleanup and go home. */
1328 ahci_shutdown(src);
1329 ahci_shutdown(dst);
1330 g_free(rx);
1331 g_free(tx);
John Snow6d9e7292015-11-13 14:31:42 -05001332 g_free(uri);
John Snow5d1cf092015-05-22 14:13:43 -04001333}
1334
John Snow8146d7d2015-07-04 02:06:05 -04001335static void test_migrate_halted_dma(void)
1336{
1337 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1338}
1339
1340static void test_migrate_halted_ncq(void)
1341{
1342 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1343}
1344
John Snow5d1cf092015-05-22 14:13:43 -04001345/**
John Snowa606ce52015-05-22 14:13:43 -04001346 * Migration test: Try to flush, migrate, then resume.
1347 */
1348static void test_flush_migrate(void)
1349{
1350 AHCIQState *src, *dst;
1351 AHCICommand *cmd;
1352 uint8_t px;
John Snow6d9e7292015-11-13 14:31:42 -05001353 char *uri = g_strdup_printf("unix:%s", mig_socket);
John Snowa606ce52015-05-22 14:13:43 -04001354
1355 prepare_blkdebug_script(debug_path, "flush_to_disk");
1356
1357 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001358 "cache=writeback,rerror=stop,werror=stop,"
1359 "format=%s "
John Snowa606ce52015-05-22 14:13:43 -04001360 "-M q35 "
1361 "-device ide-hd,drive=drive0 ",
John Snowb236b612015-11-13 14:31:42 -05001362 debug_path, tmp_path, imgfmt);
John Snowa606ce52015-05-22 14:13:43 -04001363 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
John Snowb236b612015-11-13 14:31:42 -05001364 "cache=writeback,rerror=stop,werror=stop,"
1365 "format=%s "
John Snowa606ce52015-05-22 14:13:43 -04001366 "-M q35 "
1367 "-device ide-hd,drive=drive0 "
John Snowb236b612015-11-13 14:31:42 -05001368 "-incoming %s", tmp_path, imgfmt, uri);
John Snowa606ce52015-05-22 14:13:43 -04001369
John Snowa606ce52015-05-22 14:13:43 -04001370 px = ahci_port_select(src);
1371 ahci_port_clear(src, px);
Evgeny Yakovlev2dd7e102016-07-18 22:39:51 +03001372
1373 /* Dirty device so that flush reaches disk */
1374 make_dirty(src, px);
1375
1376 /* Issue Flush Command */
John Snowa606ce52015-05-22 14:13:43 -04001377 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1378 ahci_command_commit(src, cmd, px);
1379 ahci_command_issue_async(src, cmd);
Eric Blakea189a932017-09-11 12:20:02 -05001380 qtest_qmp_eventwait(src->parent->qts, "STOP");
John Snowa606ce52015-05-22 14:13:43 -04001381
1382 /* Migrate over */
1383 ahci_migrate(src, dst, uri);
1384
1385 /* Complete the command */
Eric Blakea189a932017-09-11 12:20:02 -05001386 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }");
1387 qtest_qmp_eventwait(dst->parent->qts, "RESUME");
John Snowa606ce52015-05-22 14:13:43 -04001388 ahci_command_wait(dst, cmd);
1389 ahci_command_verify(dst, cmd);
1390
1391 ahci_command_free(cmd);
1392 ahci_shutdown(src);
1393 ahci_shutdown(dst);
John Snow6d9e7292015-11-13 14:31:42 -05001394 g_free(uri);
John Snowa606ce52015-05-22 14:13:43 -04001395}
1396
John Snow0d3e9d12015-07-04 02:06:02 -04001397static void test_max(void)
1398{
1399 AHCIQState *ahci;
1400
1401 ahci = ahci_boot_and_enable(NULL);
1402 ahci_test_max(ahci);
1403 ahci_shutdown(ahci);
1404}
1405
John Snowd31a3eb2015-07-04 02:06:02 -04001406static void test_reset(void)
1407{
1408 AHCIQState *ahci;
1409 int i;
1410
1411 ahci = ahci_boot(NULL);
1412 ahci_test_pci_spec(ahci);
1413 ahci_pci_enable(ahci);
1414
1415 for (i = 0; i < 2; i++) {
1416 ahci_test_hba_spec(ahci);
1417 ahci_hba_enable(ahci);
1418 ahci_test_identify(ahci);
1419 ahci_test_io_rw_simple(ahci, 4096, 0,
1420 CMD_READ_DMA_EXT,
1421 CMD_WRITE_DMA_EXT);
1422 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1423 ahci_clean_mem(ahci);
1424 }
1425
1426 ahci_shutdown(ahci);
1427}
1428
John Snow26ad0042015-07-04 02:06:04 -04001429static void test_ncq_simple(void)
1430{
1431 AHCIQState *ahci;
1432
1433 ahci = ahci_boot_and_enable(NULL);
1434 ahci_test_io_rw_simple(ahci, 4096, 0,
1435 READ_FPDMA_QUEUED,
1436 WRITE_FPDMA_QUEUED);
1437 ahci_shutdown(ahci);
1438}
1439
John Snowe8109692016-01-11 14:10:43 -05001440static int prepare_iso(size_t size, unsigned char **buf, char **name)
1441{
1442 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1443 unsigned char *patt;
1444 ssize_t ret;
1445 int fd = mkstemp(cdrom_path);
1446
1447 g_assert(buf);
1448 g_assert(name);
1449 patt = g_malloc(size);
1450
1451 /* Generate a pattern and build a CDROM image to read from */
1452 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1453 ret = write(fd, patt, size);
1454 g_assert(ret == size);
1455
1456 *name = g_strdup(cdrom_path);
1457 *buf = patt;
1458 return fd;
1459}
1460
1461static void remove_iso(int fd, char *name)
1462{
1463 unlink(name);
1464 g_free(name);
1465 close(fd);
1466}
1467
1468static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1469 const AHCIOpts *opts)
1470{
1471 unsigned char *tx = opts->opaque;
John Snowebde93b2016-11-14 11:15:54 -05001472 unsigned char *rx;
John Snowe8109692016-01-11 14:10:43 -05001473
John Snowebde93b2016-11-14 11:15:54 -05001474 if (!opts->size) {
1475 return 0;
1476 }
1477
1478 rx = g_malloc0(opts->size);
Eric Blakea189a932017-09-11 12:20:02 -05001479 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
John Snowe8109692016-01-11 14:10:43 -05001480 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1481 g_free(rx);
1482
1483 return 0;
1484}
1485
John Snowebde93b2016-11-14 11:15:54 -05001486static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1487 bool override_bcl, uint16_t bcl)
John Snowe8109692016-01-11 14:10:43 -05001488{
1489 AHCIQState *ahci;
1490 unsigned char *tx;
1491 char *iso;
1492 int fd;
1493 AHCIOpts opts = {
1494 .size = (ATAPI_SECTOR_SIZE * nsectors),
1495 .atapi = true,
1496 .atapi_dma = dma,
1497 .post_cb = ahci_cb_cmp_buff,
John Snowebde93b2016-11-14 11:15:54 -05001498 .set_bcl = override_bcl,
1499 .bcl = bcl,
John Snowe8109692016-01-11 14:10:43 -05001500 };
John Snow53c05e62016-11-14 11:15:54 -05001501 uint64_t iso_size = ATAPI_SECTOR_SIZE * (nsectors + 1);
John Snowe8109692016-01-11 14:10:43 -05001502
1503 /* Prepare ISO and fill 'tx' buffer */
John Snow53c05e62016-11-14 11:15:54 -05001504 fd = prepare_iso(iso_size, &tx, &iso);
John Snowe8109692016-01-11 14:10:43 -05001505 opts.opaque = tx;
1506
1507 /* Standard startup wonkery, but use ide-cd and our special iso file */
1508 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1509 "-M q35 "
1510 "-device ide-cd,drive=drive0 ", iso);
1511
1512 /* Build & Send AHCI command */
John Snowebde93b2016-11-14 11:15:54 -05001513 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
John Snowe8109692016-01-11 14:10:43 -05001514
1515 /* Cleanup */
1516 g_free(tx);
1517 ahci_shutdown(ahci);
1518 remove_iso(fd, iso);
1519}
1520
John Snowebde93b2016-11-14 11:15:54 -05001521static void ahci_test_cdrom_read10(int nsectors, bool dma)
1522{
1523 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1524}
1525
John Snowe8109692016-01-11 14:10:43 -05001526static void test_cdrom_dma(void)
1527{
John Snowebde93b2016-11-14 11:15:54 -05001528 ahci_test_cdrom_read10(1, true);
John Snowe8109692016-01-11 14:10:43 -05001529}
1530
1531static void test_cdrom_dma_multi(void)
1532{
John Snowebde93b2016-11-14 11:15:54 -05001533 ahci_test_cdrom_read10(3, true);
John Snowe8109692016-01-11 14:10:43 -05001534}
1535
1536static void test_cdrom_pio(void)
1537{
John Snowebde93b2016-11-14 11:15:54 -05001538 ahci_test_cdrom_read10(1, false);
John Snowe8109692016-01-11 14:10:43 -05001539}
1540
1541static void test_cdrom_pio_multi(void)
1542{
John Snowebde93b2016-11-14 11:15:54 -05001543 ahci_test_cdrom_read10(3, false);
1544}
1545
1546/* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
1547 * completes as a NOP instead of erroring out. */
1548static void test_atapi_bcl(void)
1549{
1550 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
John Snowe8109692016-01-11 14:10:43 -05001551}
1552
John Snow22381d42016-11-14 11:15:55 -05001553
Eric Blakea189a932017-09-11 12:20:02 -05001554static void atapi_wait_tray(AHCIQState *ahci, bool open)
John Snow22381d42016-11-14 11:15:55 -05001555{
Eric Blakea189a932017-09-11 12:20:02 -05001556 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts,
1557 "DEVICE_TRAY_MOVED");
John Snow22381d42016-11-14 11:15:55 -05001558 QDict *data = qdict_get_qdict(rsp, "data");
1559 if (open) {
1560 g_assert(qdict_get_bool(data, "tray-open"));
1561 } else {
1562 g_assert(!qdict_get_bool(data, "tray-open"));
1563 }
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +02001564 qobject_unref(rsp);
John Snow22381d42016-11-14 11:15:55 -05001565}
1566
1567static void test_atapi_tray(void)
1568{
1569 AHCIQState *ahci;
1570 unsigned char *tx;
1571 char *iso;
1572 int fd;
1573 uint8_t port, sense, asc;
1574 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1575 QDict *rsp;
1576
1577 fd = prepare_iso(iso_size, &tx, &iso);
Max Reitzf6c3dc12017-11-10 23:43:00 +01001578 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
John Snow22381d42016-11-14 11:15:55 -05001579 "-M q35 "
Max Reitzf6c3dc12017-11-10 23:43:00 +01001580 "-device ide-cd,id=cd0,drive=drive0 ", iso);
John Snow22381d42016-11-14 11:15:55 -05001581 port = ahci_port_select(ahci);
1582
1583 ahci_atapi_eject(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001584 atapi_wait_tray(ahci, true);
John Snow22381d42016-11-14 11:15:55 -05001585
1586 ahci_atapi_load(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001587 atapi_wait_tray(ahci, false);
John Snow22381d42016-11-14 11:15:55 -05001588
1589 /* Remove media */
Eric Blakea189a932017-09-11 12:20:02 -05001590 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', "
1591 "'arguments': {'id': 'cd0'}}");
1592 atapi_wait_tray(ahci, true);
1593 rsp = qtest_qmp_receive(ahci->parent->qts);
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +02001594 qobject_unref(rsp);
John Snow22381d42016-11-14 11:15:55 -05001595
Eric Blakea189a932017-09-11 12:20:02 -05001596 qmp_discard_response(ahci->parent->qts,
1597 "{'execute': 'blockdev-remove-medium', "
Max Reitzf6c3dc12017-11-10 23:43:00 +01001598 "'arguments': {'id': 'cd0'}}");
John Snow22381d42016-11-14 11:15:55 -05001599
1600 /* Test the tray without a medium */
1601 ahci_atapi_load(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001602 atapi_wait_tray(ahci, false);
John Snow22381d42016-11-14 11:15:55 -05001603
1604 ahci_atapi_eject(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001605 atapi_wait_tray(ahci, true);
John Snow22381d42016-11-14 11:15:55 -05001606
1607 /* Re-insert media */
Eric Blakea189a932017-09-11 12:20:02 -05001608 qmp_discard_response(ahci->parent->qts,
1609 "{'execute': 'blockdev-add', "
1610 "'arguments': {'node-name': 'node0', "
John Snow22381d42016-11-14 11:15:55 -05001611 "'driver': 'raw', "
1612 "'file': { 'driver': 'file', "
1613 "'filename': %s }}}", iso);
Eric Blakea189a932017-09-11 12:20:02 -05001614 qmp_discard_response(ahci->parent->qts,
1615 "{'execute': 'blockdev-insert-medium',"
1616 "'arguments': { 'id': 'cd0', "
John Snow22381d42016-11-14 11:15:55 -05001617 "'node-name': 'node0' }}");
1618
1619 /* Again, the event shows up first */
Eric Blakea189a932017-09-11 12:20:02 -05001620 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', "
1621 "'arguments': {'id': 'cd0'}}");
1622 atapi_wait_tray(ahci, false);
1623 rsp = qtest_qmp_receive(ahci->parent->qts);
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +02001624 qobject_unref(rsp);
John Snow22381d42016-11-14 11:15:55 -05001625
1626 /* Now, to convince ATAPI we understand the media has changed... */
1627 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1628 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1629 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1630 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1631
1632 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1633 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1634 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1635 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1636
1637 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1638 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1639 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1640
1641 /* Final tray test. */
1642 ahci_atapi_eject(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001643 atapi_wait_tray(ahci, true);
John Snow22381d42016-11-14 11:15:55 -05001644
1645 ahci_atapi_load(ahci, port);
Eric Blakea189a932017-09-11 12:20:02 -05001646 atapi_wait_tray(ahci, false);
John Snow22381d42016-11-14 11:15:55 -05001647
1648 /* Cleanup */
1649 g_free(tx);
1650 ahci_shutdown(ahci);
1651 remove_iso(fd, iso);
1652}
1653
John Snowbda39dc2015-02-25 18:06:39 -05001654/******************************************************************************/
1655/* AHCI I/O Test Matrix Definitions */
1656
1657enum BuffLen {
1658 LEN_BEGIN = 0,
1659 LEN_SIMPLE = LEN_BEGIN,
1660 LEN_DOUBLE,
1661 LEN_LONG,
1662 LEN_SHORT,
1663 NUM_LENGTHS
1664};
1665
1666static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1667 "long", "short" };
1668
1669enum AddrMode {
1670 ADDR_MODE_BEGIN = 0,
1671 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1672 ADDR_MODE_LBA48,
1673 NUM_ADDR_MODES
1674};
1675
1676static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1677
1678enum IOMode {
1679 MODE_BEGIN = 0,
1680 MODE_PIO = MODE_BEGIN,
1681 MODE_DMA,
1682 NUM_MODES
1683};
1684
1685static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1686
1687enum IOOps {
1688 IO_BEGIN = 0,
1689 IO_READ = IO_BEGIN,
1690 IO_WRITE,
1691 NUM_IO_OPS
1692};
1693
John Snow727be1a2015-04-28 15:27:51 -04001694enum OffsetType {
1695 OFFSET_BEGIN = 0,
1696 OFFSET_ZERO = OFFSET_BEGIN,
1697 OFFSET_LOW,
1698 OFFSET_HIGH,
1699 NUM_OFFSETS
1700};
1701
1702static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1703
John Snowbda39dc2015-02-25 18:06:39 -05001704typedef struct AHCIIOTestOptions {
1705 enum BuffLen length;
1706 enum AddrMode address_type;
1707 enum IOMode io_type;
John Snow727be1a2015-04-28 15:27:51 -04001708 enum OffsetType offset;
John Snowbda39dc2015-02-25 18:06:39 -05001709} AHCIIOTestOptions;
1710
John Snow727be1a2015-04-28 15:27:51 -04001711static uint64_t offset_sector(enum OffsetType ofst,
1712 enum AddrMode addr_type,
1713 uint64_t buffsize)
1714{
1715 uint64_t ceil;
1716 uint64_t nsectors;
1717
1718 switch (ofst) {
1719 case OFFSET_ZERO:
1720 return 0;
1721 case OFFSET_LOW:
1722 return 1;
1723 case OFFSET_HIGH:
1724 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
John Snow917158d2015-11-13 14:31:43 -05001725 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
John Snow727be1a2015-04-28 15:27:51 -04001726 nsectors = buffsize / AHCI_SECTOR_SIZE;
1727 return ceil - nsectors + 1;
1728 default:
1729 g_assert_not_reached();
1730 }
1731}
1732
John Snow81705ee2015-02-05 12:41:30 -05001733/**
John Snowbda39dc2015-02-25 18:06:39 -05001734 * Table of possible I/O ATA commands given a set of enumerations.
John Snow81705ee2015-02-05 12:41:30 -05001735 */
John Snowbda39dc2015-02-25 18:06:39 -05001736static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1737 [MODE_PIO] = {
1738 [ADDR_MODE_LBA28] = {
1739 [IO_READ] = CMD_READ_PIO,
1740 [IO_WRITE] = CMD_WRITE_PIO },
1741 [ADDR_MODE_LBA48] = {
1742 [IO_READ] = CMD_READ_PIO_EXT,
1743 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1744 },
1745 [MODE_DMA] = {
1746 [ADDR_MODE_LBA28] = {
1747 [IO_READ] = CMD_READ_DMA,
1748 [IO_WRITE] = CMD_WRITE_DMA },
1749 [ADDR_MODE_LBA48] = {
1750 [IO_READ] = CMD_READ_DMA_EXT,
1751 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1752 }
1753};
1754
1755/**
1756 * Test a Read/Write pattern using various commands, addressing modes,
1757 * transfer modes, and buffer sizes.
1758 */
1759static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
John Snow727be1a2015-04-28 15:27:51 -04001760 unsigned bufsize, uint64_t sector)
John Snow81705ee2015-02-05 12:41:30 -05001761{
1762 AHCIQState *ahci;
1763
John Snowdebaaa12015-04-28 15:27:51 -04001764 ahci = ahci_boot_and_enable(NULL);
John Snow727be1a2015-04-28 15:27:51 -04001765 ahci_test_io_rw_simple(ahci, bufsize, sector,
John Snowbda39dc2015-02-25 18:06:39 -05001766 io_cmds[dma][lba48][IO_READ],
1767 io_cmds[dma][lba48][IO_WRITE]);
John Snow81705ee2015-02-05 12:41:30 -05001768 ahci_shutdown(ahci);
1769}
1770
John Snowbda39dc2015-02-25 18:06:39 -05001771/**
1772 * Demultiplex the test data and invoke the actual test routine.
1773 */
1774static void test_io_interface(gconstpointer opaque)
John Snowd6c403e2015-02-25 18:06:38 -05001775{
John Snowbda39dc2015-02-25 18:06:39 -05001776 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1777 unsigned bufsize;
John Snow727be1a2015-04-28 15:27:51 -04001778 uint64_t sector;
John Snowbda39dc2015-02-25 18:06:39 -05001779
1780 switch (opts->length) {
1781 case LEN_SIMPLE:
1782 bufsize = 4096;
1783 break;
1784 case LEN_DOUBLE:
1785 bufsize = 8192;
1786 break;
1787 case LEN_LONG:
1788 bufsize = 4096 * 64;
1789 break;
1790 case LEN_SHORT:
1791 bufsize = 512;
1792 break;
1793 default:
1794 g_assert_not_reached();
1795 }
1796
John Snow727be1a2015-04-28 15:27:51 -04001797 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1798 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
John Snowbda39dc2015-02-25 18:06:39 -05001799 g_free(opts);
1800 return;
John Snowd6c403e2015-02-25 18:06:38 -05001801}
1802
John Snowbda39dc2015-02-25 18:06:39 -05001803static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
John Snow727be1a2015-04-28 15:27:51 -04001804 enum BuffLen len, enum OffsetType offset)
John Snowd6c403e2015-02-25 18:06:38 -05001805{
John Snowbda39dc2015-02-25 18:06:39 -05001806 char *name;
John Snow917158d2015-11-13 14:31:43 -05001807 AHCIIOTestOptions *opts;
John Snowd6c403e2015-02-25 18:06:38 -05001808
Marc-André Lureau790bbb92017-10-06 20:49:56 -03001809 opts = g_new(AHCIIOTestOptions, 1);
John Snowbda39dc2015-02-25 18:06:39 -05001810 opts->length = len;
1811 opts->address_type = addr;
1812 opts->io_type = type;
John Snow727be1a2015-04-28 15:27:51 -04001813 opts->offset = offset;
John Snowd6c403e2015-02-25 18:06:38 -05001814
Andreas Färber53f77e42015-03-25 18:40:15 +01001815 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
John Snowbda39dc2015-02-25 18:06:39 -05001816 io_mode_str[type],
1817 addr_mode_str[addr],
John Snow727be1a2015-04-28 15:27:51 -04001818 buff_len_str[len],
1819 offset_str[offset]);
John Snowbda39dc2015-02-25 18:06:39 -05001820
John Snow917158d2015-11-13 14:31:43 -05001821 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1822 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1823 g_test_message("%s: skipped; test image too small", name);
Marc-André Lureau0fd76bc2018-02-15 22:25:51 +01001824 g_free(opts);
John Snow917158d2015-11-13 14:31:43 -05001825 g_free(name);
1826 return;
1827 }
1828
Andreas Färber53f77e42015-03-25 18:40:15 +01001829 qtest_add_data_func(name, opts, test_io_interface);
John Snowbda39dc2015-02-25 18:06:39 -05001830 g_free(name);
John Snowd6c403e2015-02-25 18:06:38 -05001831}
1832
John Snow1cd10312014-08-21 13:44:32 -04001833/******************************************************************************/
1834
1835int main(int argc, char **argv)
1836{
1837 const char *arch;
John Snow1cd10312014-08-21 13:44:32 -04001838 int ret;
John Snowcf5aa892015-04-28 15:27:51 -04001839 int fd;
John Snow8840a842014-08-21 13:44:34 -04001840 int c;
John Snow727be1a2015-04-28 15:27:51 -04001841 int i, j, k, m;
John Snow8840a842014-08-21 13:44:34 -04001842
1843 static struct option long_options[] = {
1844 {"pedantic", no_argument, 0, 'p' },
1845 {0, 0, 0, 0},
1846 };
John Snow1cd10312014-08-21 13:44:32 -04001847
1848 /* Should be first to utilize g_test functionality, So we can see errors. */
1849 g_test_init(&argc, &argv, NULL);
1850
John Snow8840a842014-08-21 13:44:34 -04001851 while (1) {
1852 c = getopt_long(argc, argv, "", long_options, NULL);
1853 if (c == -1) {
1854 break;
1855 }
1856 switch (c) {
1857 case -1:
1858 break;
1859 case 'p':
1860 ahci_pedantic = 1;
1861 break;
1862 default:
1863 fprintf(stderr, "Unrecognized ahci_test option.\n");
1864 g_assert_not_reached();
1865 }
1866 }
1867
John Snow1cd10312014-08-21 13:44:32 -04001868 /* Check architecture */
1869 arch = qtest_get_arch();
1870 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1871 g_test_message("Skipping test for non-x86");
1872 return 0;
1873 }
1874
John Snowb236b612015-11-13 14:31:42 -05001875 /* Create a temporary image */
1876 fd = mkstemp(tmp_path);
1877 g_assert(fd >= 0);
John Snow917158d2015-11-13 14:31:43 -05001878 if (have_qemu_img()) {
1879 imgfmt = "qcow2";
1880 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1881 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1882 } else {
1883 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1884 "skipping LBA48 high-sector tests");
1885 imgfmt = "raw";
1886 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1887 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1888 g_assert(ret == 0);
1889 }
John Snowb236b612015-11-13 14:31:42 -05001890 close(fd);
John Snow1cd10312014-08-21 13:44:32 -04001891
John Snowcf5aa892015-04-28 15:27:51 -04001892 /* Create temporary blkdebug instructions */
1893 fd = mkstemp(debug_path);
1894 g_assert(fd >= 0);
1895 close(fd);
1896
John Snow6d9e7292015-11-13 14:31:42 -05001897 /* Reserve a hollow file to use as a socket for migration tests */
1898 fd = mkstemp(mig_socket);
1899 g_assert(fd >= 0);
1900 close(fd);
1901
John Snow1cd10312014-08-21 13:44:32 -04001902 /* Run the tests */
1903 qtest_add_func("/ahci/sanity", test_sanity);
John Snow8840a842014-08-21 13:44:34 -04001904 qtest_add_func("/ahci/pci_spec", test_pci_spec);
John Snow96d6d3b2014-08-21 13:44:35 -04001905 qtest_add_func("/ahci/pci_enable", test_pci_enable);
John Snowc2f30292014-08-21 13:44:37 -04001906 qtest_add_func("/ahci/hba_spec", test_hba_spec);
John Snowdbc180e2014-08-21 13:44:38 -04001907 qtest_add_func("/ahci/hba_enable", test_hba_enable);
John Snow0fa781e2014-08-21 13:44:39 -04001908 qtest_add_func("/ahci/identify", test_identify);
John Snowbda39dc2015-02-25 18:06:39 -05001909
1910 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1911 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1912 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
John Snow727be1a2015-04-28 15:27:51 -04001913 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1914 create_ahci_io_test(i, j, k, m);
1915 }
John Snowbda39dc2015-02-25 18:06:39 -05001916 }
1917 }
1918 }
John Snow1cd10312014-08-21 13:44:32 -04001919
John Snowe0c59cc2015-02-25 18:06:40 -05001920 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1921
John Snow4e217072015-04-28 15:27:51 -04001922 qtest_add_func("/ahci/flush/simple", test_flush);
John Snowcf5aa892015-04-28 15:27:51 -04001923 qtest_add_func("/ahci/flush/retry", test_flush_retry);
John Snowa606ce52015-05-22 14:13:43 -04001924 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
John Snow4e217072015-04-28 15:27:51 -04001925
John Snow278128a2015-05-22 14:13:43 -04001926 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
John Snow5d1cf092015-05-22 14:13:43 -04001927 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
John Snow189d1b62015-05-22 14:13:43 -04001928 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
John Snow5d1cf092015-05-22 14:13:43 -04001929 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
John Snow278128a2015-05-22 14:13:43 -04001930
John Snow0d3e9d12015-07-04 02:06:02 -04001931 qtest_add_func("/ahci/max", test_max);
John Snowd31a3eb2015-07-04 02:06:02 -04001932 qtest_add_func("/ahci/reset", test_reset);
John Snow0d3e9d12015-07-04 02:06:02 -04001933
John Snow26ad0042015-07-04 02:06:04 -04001934 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
John Snow07a1ee72015-07-04 02:06:04 -04001935 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
John Snow7f6cf5e2015-07-04 02:06:05 -04001936 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
John Snow8146d7d2015-07-04 02:06:05 -04001937 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
John Snow26ad0042015-07-04 02:06:04 -04001938
John Snowe8109692016-01-11 14:10:43 -05001939 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1940 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1941 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1942 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1943
John Snowebde93b2016-11-14 11:15:54 -05001944 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
John Snow22381d42016-11-14 11:15:55 -05001945 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
John Snowebde93b2016-11-14 11:15:54 -05001946
John Snow1cd10312014-08-21 13:44:32 -04001947 ret = g_test_run();
1948
1949 /* Cleanup */
1950 unlink(tmp_path);
John Snowcf5aa892015-04-28 15:27:51 -04001951 unlink(debug_path);
John Snow6d9e7292015-11-13 14:31:42 -05001952 unlink(mig_socket);
John Snow1cd10312014-08-21 13:44:32 -04001953
1954 return ret;
1955}