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Juan Quintela79b97bf2009-08-31 16:07:18 +02001/*
Philippe Mathieu-Daudé3ac25232021-12-06 23:45:25 +01002 * QEMU MMIO VGA Emulator.
Juan Quintela79b97bf2009-08-31 16:07:18 +02003 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbrusterd6454272019-08-12 07:23:45 +020024
Peter Maydell47df5152016-01-26 18:17:13 +000025#include "qemu/osdep.h"
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010026#include "qapi/error.h"
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010027#include "hw/sysbus.h"
28#include "hw/display/vga.h"
29#include "hw/qdev-properties.h"
Michael S. Tsirkin28cf3962022-11-09 17:21:23 -050030#include "ui/console.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010031#include "vga_int.h"
Juan Quintela79b97bf2009-08-31 16:07:18 +020032
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010033/*
34 * QEMU interface:
35 * + sysbus MMIO region 0: VGA I/O registers
36 * + sysbus MMIO region 1: VGA MMIO registers
37 * + sysbus MMIO region 2: VGA memory
38 */
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +020039
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010040OBJECT_DECLARE_SIMPLE_TYPE(VGAMmioState, VGA_MMIO)
41
42struct VGAMmioState {
43 /*< private >*/
44 SysBusDevice parent_obj;
45
46 /*< public >*/
Juan Quintela79b97bf2009-08-31 16:07:18 +020047 VGACommonState vga;
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010048 MemoryRegion iomem;
49 MemoryRegion lowmem;
Juan Quintela79b97bf2009-08-31 16:07:18 +020050
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010051 uint8_t it_shift;
52};
53
Peter Maydell5f927992018-08-02 16:51:46 +010054static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size)
Juan Quintela79b97bf2009-08-31 16:07:18 +020055{
Philippe Mathieu-Daudé3ac25232021-12-06 23:45:25 +010056 VGAMmioState *s = opaque;
Juan Quintela79b97bf2009-08-31 16:07:18 +020057
Peter Maydell5f927992018-08-02 16:51:46 +010058 return vga_ioport_read(&s->vga, addr >> s->it_shift) &
59 MAKE_64BIT_MASK(0, size * 8);
Juan Quintela79b97bf2009-08-31 16:07:18 +020060}
61
Peter Maydell5f927992018-08-02 16:51:46 +010062static void vga_mm_write(void *opaque, hwaddr addr, uint64_t value,
63 unsigned size)
Juan Quintela79b97bf2009-08-31 16:07:18 +020064{
Philippe Mathieu-Daudé3ac25232021-12-06 23:45:25 +010065 VGAMmioState *s = opaque;
Juan Quintela79b97bf2009-08-31 16:07:18 +020066
Peter Maydell5f927992018-08-02 16:51:46 +010067 vga_ioport_write(&s->vga, addr >> s->it_shift,
68 value & MAKE_64BIT_MASK(0, size * 8));
Juan Quintela79b97bf2009-08-31 16:07:18 +020069}
70
Avi Kivityb1950432011-08-08 16:08:57 +030071static const MemoryRegionOps vga_mm_ctrl_ops = {
Peter Maydell5f927992018-08-02 16:51:46 +010072 .read = vga_mm_read,
73 .write = vga_mm_write,
74 .valid.min_access_size = 1,
75 .valid.max_access_size = 4,
76 .impl.min_access_size = 1,
77 .impl.max_access_size = 4,
Avi Kivityb1950432011-08-08 16:08:57 +030078 .endianness = DEVICE_NATIVE_ENDIAN,
Juan Quintela79b97bf2009-08-31 16:07:18 +020079};
80
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010081static void vga_mmio_reset(DeviceState *dev)
82{
83 VGAMmioState *s = VGA_MMIO(dev);
84
85 vga_common_reset(&s->vga);
86}
87
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +010088static void vga_mmio_realizefn(DeviceState *dev, Error **errp)
89{
90 VGAMmioState *s = VGA_MMIO(dev);
91 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
92
93 memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s,
94 "vga-mmio", 0x100000);
95 memory_region_set_flush_coalesced(&s->iomem);
96 sysbus_init_mmio(sbd, &s->iomem);
97
98 /* XXX: endianness? */
99 memory_region_init_io(&s->lowmem, OBJECT(dev), &vga_mem_ops, &s->vga,
100 "vga-lowmem", 0x20000);
101 memory_region_set_coalescing(&s->lowmem);
102 sysbus_init_mmio(sbd, &s->lowmem);
103
104 s->vga.bank_offset = 0;
105 s->vga.global_vmstate = true;
Thomas Huth6832deb2022-03-17 09:30:25 +0100106 if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
107 return;
108 }
109
Philippe Mathieu-Daudé23f6e3b2021-12-06 23:45:27 +0100110 sysbus_init_mmio(sbd, &s->vga.vram);
111 s->vga.con = graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga);
112}
113
114static Property vga_mmio_properties[] = {
115 DEFINE_PROP_UINT8("it_shift", VGAMmioState, it_shift, 0),
116 DEFINE_PROP_UINT32("vgamem_mb", VGAMmioState, vga.vram_size_mb, 8),
117 DEFINE_PROP_END_OF_LIST(),
118};
119
120static void vga_mmio_class_initfn(ObjectClass *klass, void *data)
121{
122 DeviceClass *dc = DEVICE_CLASS(klass);
123
124 dc->realize = vga_mmio_realizefn;
125 dc->reset = vga_mmio_reset;
126 dc->vmsd = &vmstate_vga_common;
127 device_class_set_props(dc, vga_mmio_properties);
128 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
129}
130
131static const TypeInfo vga_mmio_info = {
132 .name = TYPE_VGA_MMIO,
133 .parent = TYPE_SYS_BUS_DEVICE,
134 .instance_size = sizeof(VGAMmioState),
135 .class_init = vga_mmio_class_initfn,
136};
137
138static void vga_mmio_register_types(void)
139{
140 type_register_static(&vga_mmio_info);
141}
142
143type_init(vga_mmio_register_types)