blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Sparc Sun4c interrupt controller emulation |
| 3 | * |
| 4 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 24 | |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 25 | #include "hw.h" |
| 26 | #include "sun4m.h" |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 27 | #include "monitor.h" |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 28 | #include "sysbus.h" |
| 29 | |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 30 | //#define DEBUG_IRQ_COUNT |
| 31 | //#define DEBUG_IRQ |
| 32 | |
| 33 | #ifdef DEBUG_IRQ |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 34 | #define DPRINTF(fmt, ...) \ |
| 35 | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 36 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 37 | #define DPRINTF(fmt, ...) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 38 | #endif |
| 39 | |
| 40 | /* |
| 41 | * Registers of interrupt controller in sun4c. |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | #define MAX_PILS 16 |
| 46 | |
| 47 | typedef struct Sun4c_INTCTLState { |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 48 | SysBusDevice busdev; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 49 | #ifdef DEBUG_IRQ_COUNT |
| 50 | uint64_t irq_count; |
| 51 | #endif |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 52 | qemu_irq cpu_irqs[MAX_PILS]; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 53 | const uint32_t *intbit_to_level; |
| 54 | uint32_t pil_out; |
| 55 | uint8_t reg; |
| 56 | uint8_t pending; |
| 57 | } Sun4c_INTCTLState; |
| 58 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 59 | #define INTCTL_SIZE 1 |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 60 | |
| 61 | static void sun4c_check_interrupts(void *opaque); |
| 62 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 63 | static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 64 | { |
| 65 | Sun4c_INTCTLState *s = opaque; |
| 66 | uint32_t ret; |
| 67 | |
| 68 | ret = s->reg; |
| 69 | DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
| 70 | |
| 71 | return ret; |
| 72 | } |
| 73 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 74 | static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 75 | uint32_t val) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 76 | { |
| 77 | Sun4c_INTCTLState *s = opaque; |
| 78 | |
| 79 | DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
| 80 | val &= 0xbf; |
| 81 | s->reg = val; |
| 82 | sun4c_check_interrupts(s); |
| 83 | } |
| 84 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 85 | static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = { |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 86 | sun4c_intctl_mem_readb, |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 87 | NULL, |
| 88 | NULL, |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 89 | }; |
| 90 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 91 | static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = { |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 92 | sun4c_intctl_mem_writeb, |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 93 | NULL, |
| 94 | NULL, |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 95 | }; |
| 96 | |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 97 | void sun4c_pic_info(Monitor *mon, void *opaque) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 98 | { |
| 99 | Sun4c_INTCTLState *s = opaque; |
| 100 | |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 101 | monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n", |
| 102 | s->pending, s->reg); |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 103 | } |
| 104 | |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 105 | void sun4c_irq_info(Monitor *mon, void *opaque) |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 106 | { |
| 107 | #ifndef DEBUG_IRQ_COUNT |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 108 | monitor_printf(mon, "irq statistic code not compiled.\n"); |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 109 | #else |
| 110 | Sun4c_INTCTLState *s = opaque; |
| 111 | int64_t count; |
| 112 | |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 113 | monitor_printf(mon, "IRQ statistics:\n"); |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 114 | count = s->irq_count; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 115 | if (count > 0) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 116 | monitor_printf(mon, " %" PRId64 "\n", count); |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 117 | #endif |
| 118 | } |
| 119 | |
| 120 | static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, }; |
| 121 | |
| 122 | static void sun4c_check_interrupts(void *opaque) |
| 123 | { |
| 124 | Sun4c_INTCTLState *s = opaque; |
| 125 | uint32_t pil_pending; |
| 126 | unsigned int i; |
| 127 | |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 128 | pil_pending = 0; |
| 129 | if (s->pending && !(s->reg & 0x80000000)) { |
| 130 | for (i = 0; i < 8; i++) { |
| 131 | if (s->pending & (1 << i)) |
| 132 | pil_pending |= 1 << intbit_to_level[i]; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | for (i = 0; i < MAX_PILS; i++) { |
| 137 | if (pil_pending & (1 << i)) { |
| 138 | if (!(s->pil_out & (1 << i))) |
| 139 | qemu_irq_raise(s->cpu_irqs[i]); |
| 140 | } else { |
| 141 | if (s->pil_out & (1 << i)) |
| 142 | qemu_irq_lower(s->cpu_irqs[i]); |
| 143 | } |
| 144 | } |
| 145 | s->pil_out = pil_pending; |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * "irq" here is the bit number in the system interrupt register |
| 150 | */ |
| 151 | static void sun4c_set_irq(void *opaque, int irq, int level) |
| 152 | { |
| 153 | Sun4c_INTCTLState *s = opaque; |
| 154 | uint32_t mask = 1 << irq; |
| 155 | uint32_t pil = intbit_to_level[irq]; |
| 156 | |
| 157 | DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil, |
| 158 | level); |
| 159 | if (pil > 0) { |
| 160 | if (level) { |
| 161 | #ifdef DEBUG_IRQ_COUNT |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 162 | s->irq_count++; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 163 | #endif |
| 164 | s->pending |= mask; |
| 165 | } else { |
| 166 | s->pending &= ~mask; |
| 167 | } |
| 168 | sun4c_check_interrupts(s); |
| 169 | } |
| 170 | } |
| 171 | |
Blue Swirl | 9902571 | 2009-08-31 19:30:21 +0000 | [diff] [blame] | 172 | static const VMStateDescription vmstate_sun4c_intctl = { |
| 173 | .name ="sun4c_intctl", |
| 174 | .version_id = 1, |
| 175 | .minimum_version_id = 1, |
| 176 | .minimum_version_id_old = 1, |
| 177 | .fields = (VMStateField []) { |
| 178 | VMSTATE_UINT8(reg, Sun4c_INTCTLState), |
| 179 | VMSTATE_UINT8(pending, Sun4c_INTCTLState), |
| 180 | VMSTATE_END_OF_LIST() |
| 181 | } |
| 182 | }; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 183 | |
| 184 | static void sun4c_intctl_reset(void *opaque) |
| 185 | { |
| 186 | Sun4c_INTCTLState *s = opaque; |
| 187 | |
| 188 | s->reg = 1; |
| 189 | s->pending = 0; |
blueswir1 | ee76f82 | 2007-12-28 20:59:23 +0000 | [diff] [blame] | 190 | } |
| 191 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 192 | static int sun4c_intctl_init1(SysBusDevice *dev) |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 193 | { |
| 194 | Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev); |
| 195 | int io_memory; |
| 196 | unsigned int i; |
| 197 | |
| 198 | io_memory = cpu_register_io_memory(sun4c_intctl_mem_read, |
| 199 | sun4c_intctl_mem_write, s); |
| 200 | sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); |
| 201 | qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8); |
| 202 | |
| 203 | for (i = 0; i < MAX_PILS; i++) { |
| 204 | sysbus_init_irq(dev, &s->cpu_irqs[i]); |
| 205 | } |
Blue Swirl | 9902571 | 2009-08-31 19:30:21 +0000 | [diff] [blame] | 206 | vmstate_register(-1, &vmstate_sun4c_intctl, s); |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 207 | qemu_register_reset(sun4c_intctl_reset, s); |
| 208 | sun4c_intctl_reset(s); |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 209 | return 0; |
Blue Swirl | e32cba2 | 2009-07-21 19:57:32 +0000 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | static SysBusDeviceInfo sun4c_intctl_info = { |
| 213 | .init = sun4c_intctl_init1, |
| 214 | .qdev.name = "sun4c_intctl", |
| 215 | .qdev.size = sizeof(Sun4c_INTCTLState), |
| 216 | }; |
| 217 | |
| 218 | static void sun4c_intctl_register_devices(void) |
| 219 | { |
| 220 | sysbus_register_withprop(&sun4c_intctl_info); |
| 221 | } |
| 222 | |
| 223 | device_init(sun4c_intctl_register_devices) |