aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #define TCG_TARGET_HPPA 1 |
| 26 | |
Stefan Weil | 840f586 | 2011-09-17 22:00:28 +0200 | [diff] [blame] | 27 | #if TCG_TARGET_REG_BITS != 32 |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 28 | #error unsupported |
| 29 | #endif |
| 30 | |
| 31 | #define TCG_TARGET_WORDS_BIGENDIAN |
| 32 | |
| 33 | #define TCG_TARGET_NB_REGS 32 |
| 34 | |
Richard Henderson | 771142c | 2011-11-09 08:03:33 +0000 | [diff] [blame] | 35 | typedef enum { |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 36 | TCG_REG_R0 = 0, |
| 37 | TCG_REG_R1, |
| 38 | TCG_REG_RP, |
| 39 | TCG_REG_R3, |
| 40 | TCG_REG_R4, |
| 41 | TCG_REG_R5, |
| 42 | TCG_REG_R6, |
| 43 | TCG_REG_R7, |
| 44 | TCG_REG_R8, |
| 45 | TCG_REG_R9, |
| 46 | TCG_REG_R10, |
| 47 | TCG_REG_R11, |
| 48 | TCG_REG_R12, |
| 49 | TCG_REG_R13, |
| 50 | TCG_REG_R14, |
| 51 | TCG_REG_R15, |
| 52 | TCG_REG_R16, |
| 53 | TCG_REG_R17, |
| 54 | TCG_REG_R18, |
| 55 | TCG_REG_R19, |
| 56 | TCG_REG_R20, |
| 57 | TCG_REG_R21, |
| 58 | TCG_REG_R22, |
| 59 | TCG_REG_R23, |
| 60 | TCG_REG_R24, |
| 61 | TCG_REG_R25, |
| 62 | TCG_REG_R26, |
| 63 | TCG_REG_DP, |
| 64 | TCG_REG_RET0, |
| 65 | TCG_REG_RET1, |
| 66 | TCG_REG_SP, |
| 67 | TCG_REG_R31, |
Richard Henderson | 771142c | 2011-11-09 08:03:33 +0000 | [diff] [blame] | 68 | } TCGReg; |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 69 | |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 70 | #define TCG_CT_CONST_0 0x0100 |
| 71 | #define TCG_CT_CONST_S5 0x0200 |
| 72 | #define TCG_CT_CONST_S11 0x0400 |
Richard Henderson | 9149363 | 2010-04-07 16:46:33 +0200 | [diff] [blame] | 73 | #define TCG_CT_CONST_MS11 0x0800 |
Richard Henderson | 0085bd5 | 2010-04-09 10:45:49 -0700 | [diff] [blame] | 74 | #define TCG_CT_CONST_AND 0x1000 |
| 75 | #define TCG_CT_CONST_OR 0x2000 |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 76 | |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 77 | /* used for function call generation */ |
| 78 | #define TCG_REG_CALL_STACK TCG_REG_SP |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 79 | #define TCG_TARGET_STACK_ALIGN 64 |
| 80 | #define TCG_TARGET_CALL_STACK_OFFSET -48 |
| 81 | #define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4 |
| 82 | #define TCG_TARGET_CALL_ALIGN_ARGS 1 |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 83 | #define TCG_TARGET_STACK_GROWSUP |
| 84 | |
| 85 | /* optional instructions */ |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 86 | #define TCG_TARGET_HAS_div_i32 0 |
| 87 | #define TCG_TARGET_HAS_rot_i32 1 |
| 88 | #define TCG_TARGET_HAS_ext8s_i32 1 |
| 89 | #define TCG_TARGET_HAS_ext16s_i32 1 |
| 90 | #define TCG_TARGET_HAS_bswap16_i32 1 |
| 91 | #define TCG_TARGET_HAS_bswap32_i32 1 |
| 92 | #define TCG_TARGET_HAS_not_i32 1 |
| 93 | #define TCG_TARGET_HAS_andc_i32 1 |
| 94 | #define TCG_TARGET_HAS_orc_i32 0 |
| 95 | #define TCG_TARGET_HAS_eqv_i32 0 |
| 96 | #define TCG_TARGET_HAS_nand_i32 0 |
| 97 | #define TCG_TARGET_HAS_nor_i32 0 |
| 98 | #define TCG_TARGET_HAS_deposit_i32 1 |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 99 | |
Richard Henderson | 70ec48e | 2010-04-10 22:22:28 +0200 | [diff] [blame] | 100 | /* optional instructions automatically implemented */ |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 101 | #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, 0, rs */ |
| 102 | #define TCG_TARGET_HAS_ext8u_i32 0 /* and rd, rs, 0xff */ |
| 103 | #define TCG_TARGET_HAS_ext16u_i32 0 /* and rd, rs, 0xffff */ |
Richard Henderson | 70ec48e | 2010-04-10 22:22:28 +0200 | [diff] [blame] | 104 | |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 105 | #define TCG_TARGET_HAS_GUEST_BASE |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 106 | |
| 107 | /* Note: must be synced with dyngen-exec.h */ |
| 108 | #define TCG_AREG0 TCG_REG_R17 |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 109 | |
Stefan Weil | dba4f1b | 2012-03-02 23:30:05 +0100 | [diff] [blame] | 110 | |
| 111 | static inline void flush_icache_range(tcg_target_ulong start, |
| 112 | tcg_target_ulong stop) |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 113 | { |
| 114 | start &= ~31; |
Richard Henderson | fd76e73 | 2010-04-07 04:56:43 -0700 | [diff] [blame] | 115 | while (start <= stop) { |
| 116 | asm volatile ("fdc 0(%0)\n\t" |
| 117 | "sync\n\t" |
| 118 | "fic 0(%%sr4, %0)\n\t" |
| 119 | "sync" |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 120 | : : "r"(start) : "memory"); |
| 121 | start += 32; |
| 122 | } |
| 123 | } |