bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1 | /* |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 2 | * QEMU generic PowerPC hardware System Emulator |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 24 | #include "hw.h" |
| 25 | #include "ppc.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 26 | #include "qemu/timer.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 27 | #include "sysemu/sysemu.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 28 | #include "nvram.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 29 | #include "qemu/log.h" |
Blue Swirl | ca20cf3 | 2009-09-20 14:58:02 +0000 | [diff] [blame] | 30 | #include "loader.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 31 | #include "sysemu/kvm.h" |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 32 | #include "kvm_ppc.h" |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 33 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 34 | //#define PPC_DEBUG_IRQ |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 35 | //#define PPC_DEBUG_TB |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 36 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 37 | #ifdef PPC_DEBUG_IRQ |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 38 | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 39 | #else |
| 40 | # define LOG_IRQ(...) do { } while (0) |
| 41 | #endif |
| 42 | |
| 43 | |
| 44 | #ifdef PPC_DEBUG_TB |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 45 | # define LOG_TB(...) qemu_log(__VA_ARGS__) |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 46 | #else |
| 47 | # define LOG_TB(...) do { } while (0) |
| 48 | #endif |
| 49 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 50 | static void cpu_ppc_tb_stop (CPUPPCState *env); |
| 51 | static void cpu_ppc_tb_start (CPUPPCState *env); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 52 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 53 | void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 54 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 55 | CPUPPCState *env = &cpu->env; |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 56 | unsigned int old_pending = env->pending_interrupts; |
| 57 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 58 | if (level) { |
| 59 | env->pending_interrupts |= 1 << n_IRQ; |
| 60 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 61 | } else { |
| 62 | env->pending_interrupts &= ~(1 << n_IRQ); |
| 63 | if (env->pending_interrupts == 0) |
| 64 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 65 | } |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 66 | |
| 67 | if (old_pending != env->pending_interrupts) { |
| 68 | #ifdef CONFIG_KVM |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 69 | kvmppc_set_interrupt(cpu, n_IRQ, level); |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 70 | #endif |
| 71 | } |
| 72 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 73 | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 74 | "req %08x\n", __func__, env, n_IRQ, level, |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 75 | env->pending_interrupts, env->interrupt_request); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 76 | } |
| 77 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 78 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 79 | static void ppc6xx_set_irq(void *opaque, int pin, int level) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 80 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 81 | PowerPCCPU *cpu = opaque; |
| 82 | CPUPPCState *env = &cpu->env; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 83 | int cur_level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 84 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 85 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 86 | env, pin, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 87 | cur_level = (env->irq_input_state >> pin) & 1; |
| 88 | /* Don't generate spurious events */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 89 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 90 | switch (pin) { |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 91 | case PPC6xx_INPUT_TBEN: |
| 92 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 93 | LOG_IRQ("%s: %s the time base\n", |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 94 | __func__, level ? "start" : "stop"); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 95 | if (level) { |
| 96 | cpu_ppc_tb_start(env); |
| 97 | } else { |
| 98 | cpu_ppc_tb_stop(env); |
| 99 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 100 | case PPC6xx_INPUT_INT: |
| 101 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 102 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 103 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 104 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 105 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 106 | case PPC6xx_INPUT_SMI: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 107 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 108 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 109 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 110 | ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 111 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 112 | case PPC6xx_INPUT_MCP: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 113 | /* Negative edge sensitive */ |
| 114 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 115 | * 603/604/740/750: check HID0[EMCP] |
| 116 | */ |
| 117 | if (cur_level == 1 && level == 0) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 118 | LOG_IRQ("%s: raise machine check state\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 119 | __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 120 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 121 | } |
| 122 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 123 | case PPC6xx_INPUT_CKSTP_IN: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 124 | /* Level sensitive - active low */ |
| 125 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
j_mayer | e63ecc6 | 2007-10-14 08:48:23 +0000 | [diff] [blame] | 126 | /* XXX: Note that the only way to restart the CPU is to reset it */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 127 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 128 | LOG_IRQ("%s: stop the CPU\n", __func__); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 129 | env->halted = 1; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 130 | } |
| 131 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 132 | case PPC6xx_INPUT_HRESET: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 133 | /* Level sensitive - active low */ |
| 134 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 135 | LOG_IRQ("%s: reset the CPU\n", __func__); |
Alexander Graf | fc0b2c0 | 2012-02-21 19:41:59 +0100 | [diff] [blame] | 136 | cpu_interrupt(env, CPU_INTERRUPT_RESET); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 137 | } |
| 138 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 139 | case PPC6xx_INPUT_SRESET: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 140 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 141 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 142 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 143 | break; |
| 144 | default: |
| 145 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 146 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 147 | return; |
| 148 | } |
| 149 | if (level) |
| 150 | env->irq_input_state |= 1 << pin; |
| 151 | else |
| 152 | env->irq_input_state &= ~(1 << pin); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 156 | void ppc6xx_irq_init(CPUPPCState *env) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 157 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 158 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 159 | |
| 160 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 161 | PPC6xx_INPUT_NB); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 162 | } |
| 163 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 164 | #if defined(TARGET_PPC64) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 165 | /* PowerPC 970 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 166 | static void ppc970_set_irq(void *opaque, int pin, int level) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 167 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 168 | PowerPCCPU *cpu = opaque; |
| 169 | CPUPPCState *env = &cpu->env; |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 170 | int cur_level; |
| 171 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 172 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 173 | env, pin, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 174 | cur_level = (env->irq_input_state >> pin) & 1; |
| 175 | /* Don't generate spurious events */ |
| 176 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 177 | switch (pin) { |
| 178 | case PPC970_INPUT_INT: |
| 179 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 180 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 181 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 182 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 183 | break; |
| 184 | case PPC970_INPUT_THINT: |
| 185 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 186 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 187 | level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 188 | ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 189 | break; |
| 190 | case PPC970_INPUT_MCP: |
| 191 | /* Negative edge sensitive */ |
| 192 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 193 | * 603/604/740/750: check HID0[EMCP] |
| 194 | */ |
| 195 | if (cur_level == 1 && level == 0) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 196 | LOG_IRQ("%s: raise machine check state\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 197 | __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 198 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 199 | } |
| 200 | break; |
| 201 | case PPC970_INPUT_CKSTP: |
| 202 | /* Level sensitive - active low */ |
| 203 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
| 204 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 205 | LOG_IRQ("%s: stop the CPU\n", __func__); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 206 | env->halted = 1; |
| 207 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 208 | LOG_IRQ("%s: restart the CPU\n", __func__); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 209 | env->halted = 0; |
Andreas Färber | c08d742 | 2012-05-03 04:34:15 +0200 | [diff] [blame] | 210 | qemu_cpu_kick(CPU(cpu)); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 211 | } |
| 212 | break; |
| 213 | case PPC970_INPUT_HRESET: |
| 214 | /* Level sensitive - active low */ |
| 215 | if (level) { |
Alexander Graf | fc0b2c0 | 2012-02-21 19:41:59 +0100 | [diff] [blame] | 216 | cpu_interrupt(env, CPU_INTERRUPT_RESET); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 217 | } |
| 218 | break; |
| 219 | case PPC970_INPUT_SRESET: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 220 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 221 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 222 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 223 | break; |
| 224 | case PPC970_INPUT_TBEN: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 225 | LOG_IRQ("%s: set the TBEN state to %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 226 | level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 227 | /* XXX: TODO */ |
| 228 | break; |
| 229 | default: |
| 230 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 231 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 232 | return; |
| 233 | } |
| 234 | if (level) |
| 235 | env->irq_input_state |= 1 << pin; |
| 236 | else |
| 237 | env->irq_input_state &= ~(1 << pin); |
| 238 | } |
| 239 | } |
| 240 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 241 | void ppc970_irq_init(CPUPPCState *env) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 242 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 243 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 244 | |
| 245 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 246 | PPC970_INPUT_NB); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 247 | } |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 248 | |
| 249 | /* POWER7 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 250 | static void power7_set_irq(void *opaque, int pin, int level) |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 251 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 252 | PowerPCCPU *cpu = opaque; |
| 253 | CPUPPCState *env = &cpu->env; |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 254 | |
| 255 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
| 256 | env, pin, level); |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 257 | |
| 258 | switch (pin) { |
| 259 | case POWER7_INPUT_INT: |
| 260 | /* Level sensitive - active high */ |
| 261 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
| 262 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 263 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 264 | break; |
| 265 | default: |
| 266 | /* Unknown pin - do nothing */ |
| 267 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
| 268 | return; |
| 269 | } |
| 270 | if (level) { |
| 271 | env->irq_input_state |= 1 << pin; |
| 272 | } else { |
| 273 | env->irq_input_state &= ~(1 << pin); |
| 274 | } |
| 275 | } |
| 276 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 277 | void ppcPOWER7_irq_init(CPUPPCState *env) |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 278 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 279 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 280 | |
| 281 | env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 282 | POWER7_INPUT_NB); |
| 283 | } |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 284 | #endif /* defined(TARGET_PPC64) */ |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 285 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 286 | /* PowerPC 40x internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 287 | static void ppc40x_set_irq(void *opaque, int pin, int level) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 288 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 289 | PowerPCCPU *cpu = opaque; |
| 290 | CPUPPCState *env = &cpu->env; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 291 | int cur_level; |
| 292 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 293 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 294 | env, pin, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 295 | cur_level = (env->irq_input_state >> pin) & 1; |
| 296 | /* Don't generate spurious events */ |
| 297 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 298 | switch (pin) { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 299 | case PPC40x_INPUT_RESET_SYS: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 300 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 301 | LOG_IRQ("%s: reset the PowerPC system\n", |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 302 | __func__); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 303 | ppc40x_system_reset(env); |
| 304 | } |
| 305 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 306 | case PPC40x_INPUT_RESET_CHIP: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 307 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 308 | LOG_IRQ("%s: reset the PowerPC chip\n", __func__); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 309 | ppc40x_chip_reset(env); |
| 310 | } |
| 311 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 312 | case PPC40x_INPUT_RESET_CORE: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 313 | /* XXX: TODO: update DBSR[MRR] */ |
| 314 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 315 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 316 | ppc40x_core_reset(env); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 317 | } |
| 318 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 319 | case PPC40x_INPUT_CINT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 320 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 321 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 322 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 323 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 324 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 325 | case PPC40x_INPUT_INT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 326 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 327 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 328 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 329 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 330 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 331 | case PPC40x_INPUT_HALT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 332 | /* Level sensitive - active low */ |
| 333 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 334 | LOG_IRQ("%s: stop the CPU\n", __func__); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 335 | env->halted = 1; |
| 336 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 337 | LOG_IRQ("%s: restart the CPU\n", __func__); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 338 | env->halted = 0; |
Andreas Färber | c08d742 | 2012-05-03 04:34:15 +0200 | [diff] [blame] | 339 | qemu_cpu_kick(CPU(cpu)); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 340 | } |
| 341 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 342 | case PPC40x_INPUT_DEBUG: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 343 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 344 | LOG_IRQ("%s: set the debug pin state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 345 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 346 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 347 | break; |
| 348 | default: |
| 349 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 350 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 351 | return; |
| 352 | } |
| 353 | if (level) |
| 354 | env->irq_input_state |= 1 << pin; |
| 355 | else |
| 356 | env->irq_input_state &= ~(1 << pin); |
| 357 | } |
| 358 | } |
| 359 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 360 | void ppc40x_irq_init(CPUPPCState *env) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 361 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 362 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 363 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 364 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 365 | cpu, PPC40x_INPUT_NB); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 366 | } |
| 367 | |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 368 | /* PowerPC E500 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 369 | static void ppce500_set_irq(void *opaque, int pin, int level) |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 370 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 371 | PowerPCCPU *cpu = opaque; |
| 372 | CPUPPCState *env = &cpu->env; |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 373 | int cur_level; |
| 374 | |
| 375 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
| 376 | env, pin, level); |
| 377 | cur_level = (env->irq_input_state >> pin) & 1; |
| 378 | /* Don't generate spurious events */ |
| 379 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 380 | switch (pin) { |
| 381 | case PPCE500_INPUT_MCK: |
| 382 | if (level) { |
| 383 | LOG_IRQ("%s: reset the PowerPC system\n", |
| 384 | __func__); |
| 385 | qemu_system_reset_request(); |
| 386 | } |
| 387 | break; |
| 388 | case PPCE500_INPUT_RESET_CORE: |
| 389 | if (level) { |
| 390 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 391 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 392 | } |
| 393 | break; |
| 394 | case PPCE500_INPUT_CINT: |
| 395 | /* Level sensitive - active high */ |
| 396 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
| 397 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 398 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 399 | break; |
| 400 | case PPCE500_INPUT_INT: |
| 401 | /* Level sensitive - active high */ |
| 402 | LOG_IRQ("%s: set the core IRQ state to %d\n", |
| 403 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 404 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 405 | break; |
| 406 | case PPCE500_INPUT_DEBUG: |
| 407 | /* Level sensitive - active high */ |
| 408 | LOG_IRQ("%s: set the debug pin state to %d\n", |
| 409 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 410 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 411 | break; |
| 412 | default: |
| 413 | /* Unknown pin - do nothing */ |
| 414 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
| 415 | return; |
| 416 | } |
| 417 | if (level) |
| 418 | env->irq_input_state |= 1 << pin; |
| 419 | else |
| 420 | env->irq_input_state &= ~(1 << pin); |
| 421 | } |
| 422 | } |
| 423 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 424 | void ppce500_irq_init(CPUPPCState *env) |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 425 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 426 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 427 | |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 428 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 429 | cpu, PPCE500_INPUT_NB); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 430 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 431 | /*****************************************************************************/ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 432 | /* PowerPC time base and decrementer emulation */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 433 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 434 | uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 435 | { |
| 436 | /* TB time in tb periods */ |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 437 | return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 438 | } |
| 439 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 440 | uint64_t cpu_ppc_load_tbl (CPUPPCState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 441 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 442 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 443 | uint64_t tb; |
| 444 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 445 | if (kvm_enabled()) { |
| 446 | return env->spr[SPR_TBL]; |
| 447 | } |
| 448 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 449 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 450 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 451 | |
Alexander Graf | e3ea652 | 2009-12-21 12:24:17 +0100 | [diff] [blame] | 452 | return tb; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 453 | } |
| 454 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 455 | static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 456 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 457 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 458 | uint64_t tb; |
| 459 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 460 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 461 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 462 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 463 | return tb >> 32; |
| 464 | } |
| 465 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 466 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 467 | { |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 468 | if (kvm_enabled()) { |
| 469 | return env->spr[SPR_TBU]; |
| 470 | } |
| 471 | |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 472 | return _cpu_ppc_load_tbu(env); |
| 473 | } |
| 474 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 475 | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 476 | int64_t *tb_offsetp, uint64_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 477 | { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 478 | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 479 | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 480 | __func__, value, *tb_offsetp); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 481 | } |
| 482 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 483 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 484 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 485 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 486 | uint64_t tb; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 487 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 488 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 489 | tb &= 0xFFFFFFFF00000000ULL; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 490 | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 491 | &tb_env->tb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 492 | } |
| 493 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 494 | static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 495 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 496 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 497 | uint64_t tb; |
| 498 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 499 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 500 | tb &= 0x00000000FFFFFFFFULL; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 501 | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 502 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 503 | } |
| 504 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 505 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 506 | { |
| 507 | _cpu_ppc_store_tbu(env, value); |
| 508 | } |
| 509 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 510 | uint64_t cpu_ppc_load_atbl (CPUPPCState *env) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 511 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 512 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 513 | uint64_t tb; |
| 514 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 515 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 516 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 517 | |
Aurelien Jarno | b711de9 | 2009-12-21 13:52:08 +0100 | [diff] [blame] | 518 | return tb; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 519 | } |
| 520 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 521 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 522 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 523 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 524 | uint64_t tb; |
| 525 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 526 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 527 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 528 | |
| 529 | return tb >> 32; |
| 530 | } |
| 531 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 532 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 533 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 534 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 535 | uint64_t tb; |
| 536 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 537 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 538 | tb &= 0xFFFFFFFF00000000ULL; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 539 | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 540 | &tb_env->atb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 541 | } |
| 542 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 543 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 544 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 545 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 546 | uint64_t tb; |
| 547 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 548 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 549 | tb &= 0x00000000FFFFFFFFULL; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 550 | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 551 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); |
| 552 | } |
| 553 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 554 | static void cpu_ppc_tb_stop (CPUPPCState *env) |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 555 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 556 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 557 | uint64_t tb, atb, vmclk; |
| 558 | |
| 559 | /* If the time base is already frozen, do nothing */ |
| 560 | if (tb_env->tb_freq != 0) { |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 561 | vmclk = qemu_get_clock_ns(vm_clock); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 562 | /* Get the time base */ |
| 563 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
| 564 | /* Get the alternate time base */ |
| 565 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
| 566 | /* Store the time base value (ie compute the current offset) */ |
| 567 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 568 | /* Store the alternate time base value (compute the current offset) */ |
| 569 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 570 | /* Set the time base frequency to zero */ |
| 571 | tb_env->tb_freq = 0; |
| 572 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ |
| 573 | } |
| 574 | } |
| 575 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 576 | static void cpu_ppc_tb_start (CPUPPCState *env) |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 577 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 578 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 579 | uint64_t tb, atb, vmclk; |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 580 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 581 | /* If the time base is not frozen, do nothing */ |
| 582 | if (tb_env->tb_freq == 0) { |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 583 | vmclk = qemu_get_clock_ns(vm_clock); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 584 | /* Get the time base from tb_offset */ |
| 585 | tb = tb_env->tb_offset; |
| 586 | /* Get the alternate time base from atb_offset */ |
| 587 | atb = tb_env->atb_offset; |
| 588 | /* Restore the tb frequency from the decrementer frequency */ |
| 589 | tb_env->tb_freq = tb_env->decr_freq; |
| 590 | /* Store the time base value */ |
| 591 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 592 | /* Store the alternate time base value */ |
| 593 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 594 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 595 | } |
| 596 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 597 | static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 598 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 599 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 600 | uint32_t decr; |
bellard | 4e588a4 | 2005-07-07 21:46:29 +0000 | [diff] [blame] | 601 | int64_t diff; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 602 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 603 | diff = next - qemu_get_clock_ns(vm_clock); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 604 | if (diff >= 0) { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 605 | decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 606 | } else if (tb_env->flags & PPC_TIMER_BOOKE) { |
| 607 | decr = 0; |
| 608 | } else { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 609 | decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 610 | } |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 611 | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 612 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 613 | return decr; |
| 614 | } |
| 615 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 616 | uint32_t cpu_ppc_load_decr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 617 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 618 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 619 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 620 | if (kvm_enabled()) { |
| 621 | return env->spr[SPR_DECR]; |
| 622 | } |
| 623 | |
Tristan Gingold | f55e9d9 | 2009-04-27 10:55:47 +0200 | [diff] [blame] | 624 | return _cpu_ppc_load_decr(env, tb_env->decr_next); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 625 | } |
| 626 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 627 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 628 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 629 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 630 | |
Tristan Gingold | f55e9d9 | 2009-04-27 10:55:47 +0200 | [diff] [blame] | 631 | return _cpu_ppc_load_decr(env, tb_env->hdecr_next); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 632 | } |
| 633 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 634 | uint64_t cpu_ppc_load_purr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 635 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 636 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 637 | uint64_t diff; |
| 638 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 639 | diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start; |
j_mayer | b33c17e | 2007-10-07 17:30:34 +0000 | [diff] [blame] | 640 | |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 641 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec()); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 642 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 643 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 644 | /* When decrementer expires, |
| 645 | * all we need to do is generate or queue a CPU exception |
| 646 | */ |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 647 | static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 648 | { |
| 649 | /* Raise it */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 650 | LOG_TB("raise decrementer exception\n"); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 651 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 652 | } |
| 653 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 654 | static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 655 | { |
| 656 | /* Raise it */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 657 | LOG_TB("raise decrementer exception\n"); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 658 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 659 | } |
| 660 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 661 | static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, |
| 662 | struct QEMUTimer *timer, |
| 663 | void (*raise_excp)(PowerPCCPU *), |
| 664 | uint32_t decr, uint32_t value, |
| 665 | int is_excp) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 666 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 667 | CPUPPCState *env = &cpu->env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 668 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 669 | uint64_t now, next; |
| 670 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 671 | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 672 | decr, value); |
David Gibson | 55f7d4b | 2011-10-16 19:26:17 +0000 | [diff] [blame] | 673 | |
| 674 | if (kvm_enabled()) { |
| 675 | /* KVM handles decrementer exceptions, we don't need our own timer */ |
| 676 | return; |
| 677 | } |
| 678 | |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 679 | now = qemu_get_clock_ns(vm_clock); |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 680 | next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 681 | if (is_excp) { |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 682 | next += *nextp - now; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 683 | } |
| 684 | if (next == now) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 685 | next++; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 686 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 687 | *nextp = next; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 688 | /* Adjust timer */ |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 689 | qemu_mod_timer(timer, next); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 690 | |
| 691 | /* If we set a negative value and the decrementer was positive, raise an |
| 692 | * exception. |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 693 | */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 694 | if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) |
| 695 | && (value & 0x80000000) |
| 696 | && !(decr & 0x80000000)) { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 697 | (*raise_excp)(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 698 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 699 | } |
| 700 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 701 | static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr, |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 702 | uint32_t value, int is_excp) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 703 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 704 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 705 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 706 | __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 707 | &cpu_ppc_decr_excp, decr, value, is_excp); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 708 | } |
| 709 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 710 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 711 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 712 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 713 | |
| 714 | _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 715 | } |
| 716 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 717 | static void cpu_ppc_decr_cb(void *opaque) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 718 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 719 | PowerPCCPU *cpu = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 720 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 721 | _cpu_ppc_store_decr(cpu, 0x00000000, 0xFFFFFFFF, 1); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 722 | } |
| 723 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 724 | static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr, |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 725 | uint32_t value, int is_excp) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 726 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 727 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 728 | |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 729 | if (tb_env->hdecr_timer != NULL) { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 730 | __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 731 | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
| 732 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 733 | } |
| 734 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 735 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 736 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 737 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 738 | |
| 739 | _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 0); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 740 | } |
| 741 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 742 | static void cpu_ppc_hdecr_cb(void *opaque) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 743 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 744 | PowerPCCPU *cpu = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 745 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 746 | _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 747 | } |
| 748 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 749 | static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 750 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 751 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 752 | |
| 753 | tb_env->purr_load = value; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 754 | tb_env->purr_start = qemu_get_clock_ns(vm_clock); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 755 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 756 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 757 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
| 758 | { |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 759 | CPUPPCState *env = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 760 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 761 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 762 | |
| 763 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 764 | tb_env->decr_freq = freq; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 765 | /* There is a bug in Linux 2.4 kernels: |
| 766 | * if a decrementer exception is pending when it enables msr_ee at startup, |
| 767 | * it's not ready to handle it... |
| 768 | */ |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 769 | _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
| 770 | _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
| 771 | cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 772 | } |
| 773 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 774 | /* Set up (once) timebase frequency (in Hz) */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 775 | clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 776 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 777 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 778 | ppc_tb_t *tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 779 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 780 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 781 | env->tb_env = tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 782 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 783 | /* Create new timer */ |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 784 | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 785 | if (0) { |
| 786 | /* XXX: find a suitable condition to enable the hypervisor decrementer |
| 787 | */ |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 788 | tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb, |
| 789 | cpu); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 790 | } else { |
| 791 | tb_env->hdecr_timer = NULL; |
| 792 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 793 | cpu_ppc_set_tb_clk(env, freq); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 794 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 795 | return &cpu_ppc_set_tb_clk; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 796 | } |
| 797 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 798 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 799 | #if 0 |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 800 | static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 801 | { |
| 802 | return cpu_ppc_tb_init(env, 7812500); |
| 803 | } |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 804 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 805 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 806 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 807 | { |
| 808 | _cpu_ppc_store_tbu(env, value); |
| 809 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 810 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 811 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 812 | { |
| 813 | return _cpu_ppc_load_tbu(env); |
| 814 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 815 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 816 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 817 | { |
| 818 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); |
| 819 | } |
| 820 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 821 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 822 | { |
| 823 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
| 824 | } |
| 825 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 826 | /*****************************************************************************/ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 827 | /* PowerPC 40x timers */ |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 828 | |
| 829 | /* PIT, FIT & WDT */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 830 | typedef struct ppc40x_timer_t ppc40x_timer_t; |
| 831 | struct ppc40x_timer_t { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 832 | uint64_t pit_reload; /* PIT auto-reload value */ |
| 833 | uint64_t fit_next; /* Tick for next FIT interrupt */ |
| 834 | struct QEMUTimer *fit_timer; |
| 835 | uint64_t wdt_next; /* Tick for next WDT interrupt */ |
| 836 | struct QEMUTimer *wdt_timer; |
Edgar E. Iglesias | d63cb48 | 2010-09-20 19:08:42 +0200 | [diff] [blame] | 837 | |
| 838 | /* 405 have the PIT, 440 have a DECR. */ |
| 839 | unsigned int decr_excp; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 840 | }; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 841 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 842 | /* Fixed interval timer */ |
| 843 | static void cpu_4xx_fit_cb (void *opaque) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 844 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 845 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 846 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 847 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 848 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 849 | uint64_t now, next; |
| 850 | |
| 851 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 852 | cpu = ppc_env_get_cpu(env); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 853 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 854 | ppc40x_timer = tb_env->opaque; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 855 | now = qemu_get_clock_ns(vm_clock); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 856 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
| 857 | case 0: |
| 858 | next = 1 << 9; |
| 859 | break; |
| 860 | case 1: |
| 861 | next = 1 << 13; |
| 862 | break; |
| 863 | case 2: |
| 864 | next = 1 << 17; |
| 865 | break; |
| 866 | case 3: |
| 867 | next = 1 << 21; |
| 868 | break; |
| 869 | default: |
| 870 | /* Cannot occur, but makes gcc happy */ |
| 871 | return; |
| 872 | } |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 873 | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 874 | if (next == now) |
| 875 | next++; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 876 | qemu_mod_timer(ppc40x_timer->fit_timer, next); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 877 | env->spr[SPR_40x_TSR] |= 1 << 26; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 878 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { |
| 879 | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); |
| 880 | } |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 881 | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
| 882 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
| 883 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | /* Programmable interval timer */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 887 | static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 888 | { |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 889 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 890 | uint64_t now, next; |
| 891 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 892 | ppc40x_timer = tb_env->opaque; |
| 893 | if (ppc40x_timer->pit_reload <= 1 || |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 894 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
| 895 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
| 896 | /* Stop PIT */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 897 | LOG_TB("%s: stop PIT\n", __func__); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 898 | qemu_del_timer(tb_env->decr_timer); |
| 899 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 900 | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 901 | __func__, ppc40x_timer->pit_reload); |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 902 | now = qemu_get_clock_ns(vm_clock); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 903 | next = now + muldiv64(ppc40x_timer->pit_reload, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 904 | get_ticks_per_sec(), tb_env->decr_freq); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 905 | if (is_excp) |
| 906 | next += tb_env->decr_next - now; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 907 | if (next == now) |
| 908 | next++; |
| 909 | qemu_mod_timer(tb_env->decr_timer, next); |
| 910 | tb_env->decr_next = next; |
| 911 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | static void cpu_4xx_pit_cb (void *opaque) |
| 915 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 916 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 917 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 918 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 919 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 920 | |
| 921 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 922 | cpu = ppc_env_get_cpu(env); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 923 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 924 | ppc40x_timer = tb_env->opaque; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 925 | env->spr[SPR_40x_TSR] |= 1 << 27; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 926 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { |
| 927 | ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); |
| 928 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 929 | start_stop_pit(env, tb_env, 1); |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 930 | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
| 931 | "%016" PRIx64 "\n", __func__, |
| 932 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
| 933 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
| 934 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 935 | ppc40x_timer->pit_reload); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 936 | } |
| 937 | |
| 938 | /* Watchdog timer */ |
| 939 | static void cpu_4xx_wdt_cb (void *opaque) |
| 940 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 941 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 942 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 943 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 944 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 945 | uint64_t now, next; |
| 946 | |
| 947 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 948 | cpu = ppc_env_get_cpu(env); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 949 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 950 | ppc40x_timer = tb_env->opaque; |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 951 | now = qemu_get_clock_ns(vm_clock); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 952 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
| 953 | case 0: |
| 954 | next = 1 << 17; |
| 955 | break; |
| 956 | case 1: |
| 957 | next = 1 << 21; |
| 958 | break; |
| 959 | case 2: |
| 960 | next = 1 << 25; |
| 961 | break; |
| 962 | case 3: |
| 963 | next = 1 << 29; |
| 964 | break; |
| 965 | default: |
| 966 | /* Cannot occur, but makes gcc happy */ |
| 967 | return; |
| 968 | } |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 969 | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 970 | if (next == now) |
| 971 | next++; |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 972 | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
| 973 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 974 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
| 975 | case 0x0: |
| 976 | case 0x1: |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 977 | qemu_mod_timer(ppc40x_timer->wdt_timer, next); |
| 978 | ppc40x_timer->wdt_next = next; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 979 | env->spr[SPR_40x_TSR] |= 1 << 31; |
| 980 | break; |
| 981 | case 0x2: |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 982 | qemu_mod_timer(ppc40x_timer->wdt_timer, next); |
| 983 | ppc40x_timer->wdt_next = next; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 984 | env->spr[SPR_40x_TSR] |= 1 << 30; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 985 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { |
| 986 | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); |
| 987 | } |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 988 | break; |
| 989 | case 0x3: |
| 990 | env->spr[SPR_40x_TSR] &= ~0x30000000; |
| 991 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; |
| 992 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
| 993 | case 0x0: |
| 994 | /* No reset */ |
| 995 | break; |
| 996 | case 0x1: /* Core reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 997 | ppc40x_core_reset(env); |
| 998 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 999 | case 0x2: /* Chip reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1000 | ppc40x_chip_reset(env); |
| 1001 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1002 | case 0x3: /* System reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1003 | ppc40x_system_reset(env); |
| 1004 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1005 | } |
| 1006 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1007 | } |
| 1008 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1009 | void store_40x_pit (CPUPPCState *env, target_ulong val) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1010 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1011 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1012 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1013 | |
| 1014 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1015 | ppc40x_timer = tb_env->opaque; |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 1016 | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1017 | ppc40x_timer->pit_reload = val; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1018 | start_stop_pit(env, tb_env, 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1019 | } |
| 1020 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1021 | target_ulong load_40x_pit (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1022 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1023 | return cpu_ppc_load_decr(env); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1024 | } |
| 1025 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1026 | static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1027 | { |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1028 | CPUPPCState *env = opaque; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1029 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1030 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1031 | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 1032 | freq); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1033 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1034 | tb_env->decr_freq = freq; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1035 | /* XXX: we should also update all timers */ |
| 1036 | } |
| 1037 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1038 | clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, |
Edgar E. Iglesias | d63cb48 | 2010-09-20 19:08:42 +0200 | [diff] [blame] | 1039 | unsigned int decr_excp) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1040 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1041 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1042 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1043 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1044 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1045 | env->tb_env = tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1046 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
| 1047 | ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1048 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1049 | tb_env->decr_freq = freq; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1050 | tb_env->opaque = ppc40x_timer; |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1051 | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1052 | if (ppc40x_timer != NULL) { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1053 | /* We use decr timer for PIT */ |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 1054 | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1055 | ppc40x_timer->fit_timer = |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 1056 | qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1057 | ppc40x_timer->wdt_timer = |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 1058 | qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1059 | ppc40x_timer->decr_excp = decr_excp; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1060 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1061 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1062 | return &ppc_40x_set_tb_clk; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1063 | } |
| 1064 | |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1065 | /*****************************************************************************/ |
| 1066 | /* Embedded PowerPC Device Control Registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1067 | typedef struct ppc_dcrn_t ppc_dcrn_t; |
| 1068 | struct ppc_dcrn_t { |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1069 | dcr_read_cb dcr_read; |
| 1070 | dcr_write_cb dcr_write; |
| 1071 | void *opaque; |
| 1072 | }; |
| 1073 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1074 | /* XXX: on 460, DCR addresses are 32 bits wide, |
| 1075 | * using DCRIPR to get the 22 upper bits of the DCR address |
| 1076 | */ |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1077 | #define DCRN_NB 1024 |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1078 | struct ppc_dcr_t { |
| 1079 | ppc_dcrn_t dcrn[DCRN_NB]; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1080 | int (*read_error)(int dcrn); |
| 1081 | int (*write_error)(int dcrn); |
| 1082 | }; |
| 1083 | |
Alexander Graf | 73b0196 | 2009-12-21 14:02:39 +0100 | [diff] [blame] | 1084 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1085 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1086 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1087 | |
| 1088 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1089 | goto error; |
| 1090 | dcr = &dcr_env->dcrn[dcrn]; |
| 1091 | if (dcr->dcr_read == NULL) |
| 1092 | goto error; |
| 1093 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
| 1094 | |
| 1095 | return 0; |
| 1096 | |
| 1097 | error: |
| 1098 | if (dcr_env->read_error != NULL) |
| 1099 | return (*dcr_env->read_error)(dcrn); |
| 1100 | |
| 1101 | return -1; |
| 1102 | } |
| 1103 | |
Alexander Graf | 73b0196 | 2009-12-21 14:02:39 +0100 | [diff] [blame] | 1104 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1105 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1106 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1107 | |
| 1108 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1109 | goto error; |
| 1110 | dcr = &dcr_env->dcrn[dcrn]; |
| 1111 | if (dcr->dcr_write == NULL) |
| 1112 | goto error; |
| 1113 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
| 1114 | |
| 1115 | return 0; |
| 1116 | |
| 1117 | error: |
| 1118 | if (dcr_env->write_error != NULL) |
| 1119 | return (*dcr_env->write_error)(dcrn); |
| 1120 | |
| 1121 | return -1; |
| 1122 | } |
| 1123 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1124 | int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1125 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
| 1126 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1127 | ppc_dcr_t *dcr_env; |
| 1128 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1129 | |
| 1130 | dcr_env = env->dcr_env; |
| 1131 | if (dcr_env == NULL) |
| 1132 | return -1; |
| 1133 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1134 | return -1; |
| 1135 | dcr = &dcr_env->dcrn[dcrn]; |
| 1136 | if (dcr->opaque != NULL || |
| 1137 | dcr->dcr_read != NULL || |
| 1138 | dcr->dcr_write != NULL) |
| 1139 | return -1; |
| 1140 | dcr->opaque = opaque; |
| 1141 | dcr->dcr_read = dcr_read; |
| 1142 | dcr->dcr_write = dcr_write; |
| 1143 | |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1147 | int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1148 | int (*write_error)(int dcrn)) |
| 1149 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1150 | ppc_dcr_t *dcr_env; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1151 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1152 | dcr_env = g_malloc0(sizeof(ppc_dcr_t)); |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1153 | dcr_env->read_error = read_error; |
| 1154 | dcr_env->write_error = write_error; |
| 1155 | env->dcr_env = dcr_env; |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1160 | /*****************************************************************************/ |
| 1161 | /* Debug port */ |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1162 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1163 | { |
| 1164 | addr &= 0xF; |
| 1165 | switch (addr) { |
| 1166 | case 0: |
| 1167 | printf("%c", val); |
| 1168 | break; |
| 1169 | case 1: |
| 1170 | printf("\n"); |
| 1171 | fflush(stdout); |
| 1172 | break; |
| 1173 | case 2: |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 1174 | printf("Set loglevel to %04" PRIx32 "\n", val); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1175 | cpu_set_log(val | 0x100); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1176 | break; |
| 1177 | } |
| 1178 | } |
| 1179 | |
| 1180 | /*****************************************************************************/ |
| 1181 | /* NVRAM helpers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1182 | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1183 | { |
Dong Xu Wang | 3a93113 | 2011-11-29 16:52:38 +0800 | [diff] [blame] | 1184 | return (*nvram->read_fn)(nvram->opaque, addr); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1185 | } |
| 1186 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1187 | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1188 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1189 | (*nvram->write_fn)(nvram->opaque, addr, val); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1190 | } |
| 1191 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1192 | static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1193 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1194 | nvram_write(nvram, addr, value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1195 | } |
| 1196 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1197 | static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr) |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1198 | { |
| 1199 | return nvram_read(nvram, addr); |
| 1200 | } |
| 1201 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1202 | static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value) |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1203 | { |
| 1204 | nvram_write(nvram, addr, value >> 8); |
| 1205 | nvram_write(nvram, addr + 1, value & 0xFF); |
| 1206 | } |
| 1207 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1208 | static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1209 | { |
| 1210 | uint16_t tmp; |
| 1211 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1212 | tmp = nvram_read(nvram, addr) << 8; |
| 1213 | tmp |= nvram_read(nvram, addr + 1); |
| 1214 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1215 | return tmp; |
| 1216 | } |
| 1217 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1218 | static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1219 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1220 | nvram_write(nvram, addr, value >> 24); |
| 1221 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| 1222 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
| 1223 | nvram_write(nvram, addr + 3, value & 0xFF); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1224 | } |
| 1225 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1226 | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1227 | { |
| 1228 | uint32_t tmp; |
| 1229 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1230 | tmp = nvram_read(nvram, addr) << 24; |
| 1231 | tmp |= nvram_read(nvram, addr + 1) << 16; |
| 1232 | tmp |= nvram_read(nvram, addr + 2) << 8; |
| 1233 | tmp |= nvram_read(nvram, addr + 3); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1234 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1235 | return tmp; |
| 1236 | } |
| 1237 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1238 | static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str, |
| 1239 | uint32_t max) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1240 | { |
| 1241 | int i; |
| 1242 | |
| 1243 | for (i = 0; i < max && str[i] != '\0'; i++) { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1244 | nvram_write(nvram, addr + i, str[i]); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1245 | } |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1246 | nvram_write(nvram, addr + i, str[i]); |
| 1247 | nvram_write(nvram, addr + max - 1, '\0'); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1248 | } |
| 1249 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1250 | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1251 | { |
| 1252 | int i; |
| 1253 | |
| 1254 | memset(dst, 0, max); |
| 1255 | for (i = 0; i < max; i++) { |
| 1256 | dst[i] = NVRAM_get_byte(nvram, addr + i); |
| 1257 | if (dst[i] == '\0') |
| 1258 | break; |
| 1259 | } |
| 1260 | |
| 1261 | return i; |
| 1262 | } |
| 1263 | |
| 1264 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) |
| 1265 | { |
| 1266 | uint16_t tmp; |
| 1267 | uint16_t pd, pd1, pd2; |
| 1268 | |
| 1269 | tmp = prev >> 8; |
| 1270 | pd = prev ^ value; |
| 1271 | pd1 = pd & 0x000F; |
| 1272 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
| 1273 | tmp ^= (pd1 << 3) | (pd1 << 8); |
| 1274 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
| 1275 | |
| 1276 | return tmp; |
| 1277 | } |
| 1278 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1279 | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1280 | { |
| 1281 | uint32_t i; |
| 1282 | uint16_t crc = 0xFFFF; |
| 1283 | int odd; |
| 1284 | |
| 1285 | odd = count & 1; |
| 1286 | count &= ~1; |
| 1287 | for (i = 0; i != count; i++) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1288 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1289 | } |
| 1290 | if (odd) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1291 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
| 1294 | return crc; |
| 1295 | } |
| 1296 | |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1297 | #define CMDLINE_ADDR 0x017ff000 |
| 1298 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1299 | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1300 | const char *arch, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1301 | uint32_t RAM_size, int boot_device, |
| 1302 | uint32_t kernel_image, uint32_t kernel_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1303 | const char *cmdline, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1304 | uint32_t initrd_image, uint32_t initrd_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1305 | uint32_t NVRAM_image, |
| 1306 | int width, int height, int depth) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1307 | { |
| 1308 | uint16_t crc; |
| 1309 | |
| 1310 | /* Set parameters for Open Hack'Ware BIOS */ |
| 1311 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 1312 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
| 1313 | NVRAM_set_word(nvram, 0x14, NVRAM_size); |
| 1314 | NVRAM_set_string(nvram, 0x20, arch, 16); |
| 1315 | NVRAM_set_lword(nvram, 0x30, RAM_size); |
| 1316 | NVRAM_set_byte(nvram, 0x34, boot_device); |
| 1317 | NVRAM_set_lword(nvram, 0x38, kernel_image); |
| 1318 | NVRAM_set_lword(nvram, 0x3C, kernel_size); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1319 | if (cmdline) { |
| 1320 | /* XXX: put the cmdline in NVRAM too ? */ |
Gerd Hoffmann | 3c178e7 | 2009-10-07 13:37:06 +0200 | [diff] [blame] | 1321 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1322 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
| 1323 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); |
| 1324 | } else { |
| 1325 | NVRAM_set_lword(nvram, 0x40, 0); |
| 1326 | NVRAM_set_lword(nvram, 0x44, 0); |
| 1327 | } |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1328 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
| 1329 | NVRAM_set_lword(nvram, 0x4C, initrd_size); |
| 1330 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1331 | |
| 1332 | NVRAM_set_word(nvram, 0x54, width); |
| 1333 | NVRAM_set_word(nvram, 0x56, height); |
| 1334 | NVRAM_set_word(nvram, 0x58, depth); |
| 1335 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1336 | NVRAM_set_word(nvram, 0xFC, crc); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1337 | |
| 1338 | return 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1339 | } |