Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM GIC support - internal interfaces |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation, either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef QEMU_ARM_GIC_INTERNAL_H |
| 22 | #define QEMU_ARM_GIC_INTERNAL_H |
| 23 | |
| 24 | #include "sysbus.h" |
| 25 | |
| 26 | /* Maximum number of possible interrupts, determined by the GIC architecture */ |
| 27 | #define GIC_MAXIRQ 1020 |
| 28 | /* First 32 are private to each CPU (SGIs and PPIs). */ |
| 29 | #define GIC_INTERNAL 32 |
| 30 | /* Maximum number of possible CPU interfaces, determined by GIC architecture */ |
| 31 | #define NCPU 8 |
| 32 | |
| 33 | #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) |
| 34 | |
| 35 | /* The NVIC has 16 internal vectors. However these are not exposed |
| 36 | through the normal GIC interface. */ |
| 37 | #define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) |
| 38 | |
| 39 | #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm) |
| 40 | #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm) |
| 41 | #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) |
| 42 | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm) |
| 43 | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm) |
| 44 | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
| 45 | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) |
| 46 | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) |
| 47 | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
| 48 | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
| 49 | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
| 50 | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model |
| 51 | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) |
| 52 | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) |
| 53 | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
| 54 | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
| 55 | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
| 56 | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger |
| 57 | #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ |
| 58 | s->priority1[irq][cpu] : \ |
| 59 | s->priority2[(irq) - GIC_INTERNAL]) |
| 60 | #define GIC_TARGET(irq) s->irq_target[irq] |
| 61 | |
| 62 | typedef struct gic_irq_state { |
| 63 | /* The enable bits are only banked for per-cpu interrupts. */ |
| 64 | unsigned enabled:NCPU; |
| 65 | unsigned pending:NCPU; |
| 66 | unsigned active:NCPU; |
| 67 | unsigned level:NCPU; |
| 68 | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
| 69 | unsigned trigger:1; /* nonzero = edge triggered. */ |
| 70 | } gic_irq_state; |
| 71 | |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 72 | typedef struct GICState { |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 73 | SysBusDevice busdev; |
| 74 | qemu_irq parent_irq[NCPU]; |
| 75 | int enabled; |
| 76 | int cpu_enabled[NCPU]; |
| 77 | |
| 78 | gic_irq_state irq_state[GIC_MAXIRQ]; |
| 79 | int irq_target[GIC_MAXIRQ]; |
| 80 | int priority1[GIC_INTERNAL][NCPU]; |
| 81 | int priority2[GIC_MAXIRQ - GIC_INTERNAL]; |
| 82 | int last_active[GIC_MAXIRQ][NCPU]; |
| 83 | |
| 84 | int priority_mask[NCPU]; |
| 85 | int running_irq[NCPU]; |
| 86 | int running_priority[NCPU]; |
| 87 | int current_pending[NCPU]; |
| 88 | |
| 89 | uint32_t num_cpu; |
| 90 | |
| 91 | MemoryRegion iomem; /* Distributor */ |
| 92 | /* This is just so we can have an opaque pointer which identifies |
| 93 | * both this GIC and which CPU interface we should be accessing. |
| 94 | */ |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 95 | struct GICState *backref[NCPU]; |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 96 | MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ |
| 97 | uint32_t num_irq; |
| 98 | uint32_t revision; |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 99 | } GICState; |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 100 | |
| 101 | /* The special cases for the revision property: */ |
| 102 | #define REV_11MPCORE 0 |
| 103 | #define REV_NVIC 0xffffffff |
| 104 | |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 105 | void gic_set_pending_private(GICState *s, int cpu, int irq); |
| 106 | uint32_t gic_acknowledge_irq(GICState *s, int cpu); |
| 107 | void gic_complete_irq(GICState *s, int cpu, int irq); |
| 108 | void gic_update(GICState *s); |
| 109 | void gic_init_irqs_and_distributor(GICState *s, int num_irq); |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 110 | |
| 111 | #define TYPE_ARM_GIC_COMMON "arm_gic_common" |
| 112 | #define ARM_GIC_COMMON(obj) \ |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 113 | OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 114 | #define ARM_GIC_COMMON_CLASS(klass) \ |
| 115 | OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) |
| 116 | #define ARM_GIC_COMMON_GET_CLASS(obj) \ |
| 117 | OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) |
| 118 | |
| 119 | typedef struct ARMGICCommonClass { |
| 120 | SysBusDeviceClass parent_class; |
| 121 | } ARMGICCommonClass; |
| 122 | |
| 123 | #define TYPE_ARM_GIC "arm_gic" |
| 124 | #define ARM_GIC(obj) \ |
Peter Maydell | fae1528 | 2012-10-12 11:54:39 +0100 | [diff] [blame] | 125 | OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 126 | #define ARM_GIC_CLASS(klass) \ |
| 127 | OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC) |
| 128 | #define ARM_GIC_GET_CLASS(obj) \ |
| 129 | OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC) |
| 130 | |
| 131 | typedef struct ARMGICClass { |
| 132 | ARMGICCommonClass parent_class; |
| 133 | int (*parent_init)(SysBusDevice *dev); |
| 134 | } ARMGICClass; |
| 135 | |
| 136 | #endif /* !QEMU_ARM_GIC_INTERNAL_H */ |