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bellardb92e5a22003-08-08 23:58:05 +00001/*
2 * Software MMU support
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardb92e5a22003-08-08 23:58:05 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardb92e5a22003-08-08 23:58:05 +000018 */
Blue Swirl29e922b2010-03-29 19:24:00 +000019#include "qemu-timer.h"
20
bellardb92e5a22003-08-08 23:58:05 +000021#define DATA_SIZE (1 << SHIFT)
22
23#if DATA_SIZE == 8
24#define SUFFIX q
bellard61382a52003-10-27 21:22:23 +000025#define USUFFIX q
bellardb92e5a22003-08-08 23:58:05 +000026#define DATA_TYPE uint64_t
27#elif DATA_SIZE == 4
28#define SUFFIX l
bellard61382a52003-10-27 21:22:23 +000029#define USUFFIX l
bellardb92e5a22003-08-08 23:58:05 +000030#define DATA_TYPE uint32_t
31#elif DATA_SIZE == 2
32#define SUFFIX w
bellard61382a52003-10-27 21:22:23 +000033#define USUFFIX uw
bellardb92e5a22003-08-08 23:58:05 +000034#define DATA_TYPE uint16_t
35#elif DATA_SIZE == 1
36#define SUFFIX b
bellard61382a52003-10-27 21:22:23 +000037#define USUFFIX ub
bellardb92e5a22003-08-08 23:58:05 +000038#define DATA_TYPE uint8_t
39#else
40#error unsupported data size
41#endif
42
bellardb769d8f2004-10-03 15:07:13 +000043#ifdef SOFTMMU_CODE_ACCESS
44#define READ_ACCESS_TYPE 2
bellard84b7b8e2005-11-28 21:19:04 +000045#define ADDR_READ addr_code
bellardb769d8f2004-10-03 15:07:13 +000046#else
47#define READ_ACCESS_TYPE 0
bellard84b7b8e2005-11-28 21:19:04 +000048#define ADDR_READ addr_read
bellardb769d8f2004-10-03 15:07:13 +000049#endif
50
ths5fafdf22007-09-16 21:08:06 +000051static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
j_mayer6ebbf392007-10-14 07:07:08 +000052 int mmu_idx,
bellard61382a52003-10-27 21:22:23 +000053 void *retaddr);
Anthony Liguoric227f092009-10-01 16:12:16 -050054static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
pbrook2e70f6e2008-06-29 01:03:05 +000055 target_ulong addr,
56 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +000057{
58 DATA_TYPE res;
59 int index;
pbrook0f459d12008-06-09 00:20:13 +000060 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
61 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
pbrook2e70f6e2008-06-29 01:03:05 +000062 env->mem_io_pc = (unsigned long)retaddr;
63 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
64 && !can_do_io(env)) {
65 cpu_io_recompile(env, retaddr);
66 }
bellardb92e5a22003-08-08 23:58:05 +000067
aliguoridb8886d2008-11-18 20:09:43 +000068 env->mem_io_vaddr = addr;
bellardb92e5a22003-08-08 23:58:05 +000069#if SHIFT <= 2
bellarda4193c82004-06-03 14:01:43 +000070 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
bellardb92e5a22003-08-08 23:58:05 +000071#else
72#ifdef TARGET_WORDS_BIGENDIAN
bellarda4193c82004-06-03 14:01:43 +000073 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
74 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
bellardb92e5a22003-08-08 23:58:05 +000075#else
bellarda4193c82004-06-03 14:01:43 +000076 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
77 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
bellardb92e5a22003-08-08 23:58:05 +000078#endif
79#endif /* SHIFT > 2 */
80 return res;
81}
82
bellardb92e5a22003-08-08 23:58:05 +000083/* handle all cases except unaligned access which span two pages */
bellardd6564692008-01-31 09:22:27 +000084DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
85 int mmu_idx)
bellardb92e5a22003-08-08 23:58:05 +000086{
87 DATA_TYPE res;
bellard61382a52003-10-27 21:22:23 +000088 int index;
bellardc27004e2005-01-03 23:35:10 +000089 target_ulong tlb_addr;
Paul Brook355b1942010-04-05 00:28:53 +010090 target_phys_addr_t ioaddr;
91 unsigned long addend;
bellardb92e5a22003-08-08 23:58:05 +000092 void *retaddr;
ths3b46e622007-09-17 08:09:54 +000093
bellardb92e5a22003-08-08 23:58:05 +000094 /* test if there is match for unaligned or IO access */
95 /* XXX: could done more in memory macro in a non portable way */
bellardb92e5a22003-08-08 23:58:05 +000096 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
97 redo:
j_mayer6ebbf392007-10-14 07:07:08 +000098 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
bellardb92e5a22003-08-08 23:58:05 +000099 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellardb92e5a22003-08-08 23:58:05 +0000100 if (tlb_addr & ~TARGET_PAGE_MASK) {
101 /* IO access */
102 if ((addr & (DATA_SIZE - 1)) != 0)
103 goto do_unaligned_access;
pbrook2e70f6e2008-06-29 01:03:05 +0000104 retaddr = GETPC();
Paul Brook355b1942010-04-05 00:28:53 +0100105 ioaddr = env->iotlb[mmu_idx][index];
106 res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000107 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000108 /* slow unaligned access (it spans two pages or IO) */
109 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +0000110 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000111#ifdef ALIGNED_ONLY
j_mayer6ebbf392007-10-14 07:07:08 +0000112 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000113#endif
ths5fafdf22007-09-16 21:08:06 +0000114 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
j_mayer6ebbf392007-10-14 07:07:08 +0000115 mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000116 } else {
bellarda64d4712005-12-05 19:57:57 +0000117 /* unaligned/aligned access in the same page */
118#ifdef ALIGNED_ONLY
119 if ((addr & (DATA_SIZE - 1)) != 0) {
120 retaddr = GETPC();
j_mayer6ebbf392007-10-14 07:07:08 +0000121 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000122 }
123#endif
pbrook0f459d12008-06-09 00:20:13 +0000124 addend = env->tlb_table[mmu_idx][index].addend;
125 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
bellardb92e5a22003-08-08 23:58:05 +0000126 }
127 } else {
128 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000129 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000130#ifdef ALIGNED_ONLY
131 if ((addr & (DATA_SIZE - 1)) != 0)
j_mayer6ebbf392007-10-14 07:07:08 +0000132 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000133#endif
j_mayer6ebbf392007-10-14 07:07:08 +0000134 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000135 goto redo;
136 }
137 return res;
138}
139
140/* handle all unaligned cases */
ths5fafdf22007-09-16 21:08:06 +0000141static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
j_mayer6ebbf392007-10-14 07:07:08 +0000142 int mmu_idx,
bellard61382a52003-10-27 21:22:23 +0000143 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000144{
145 DATA_TYPE res, res1, res2;
bellard61382a52003-10-27 21:22:23 +0000146 int index, shift;
Paul Brook355b1942010-04-05 00:28:53 +0100147 target_phys_addr_t ioaddr;
148 unsigned long addend;
bellardc27004e2005-01-03 23:35:10 +0000149 target_ulong tlb_addr, addr1, addr2;
bellardb92e5a22003-08-08 23:58:05 +0000150
bellardb92e5a22003-08-08 23:58:05 +0000151 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
152 redo:
j_mayer6ebbf392007-10-14 07:07:08 +0000153 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
bellardb92e5a22003-08-08 23:58:05 +0000154 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellardb92e5a22003-08-08 23:58:05 +0000155 if (tlb_addr & ~TARGET_PAGE_MASK) {
156 /* IO access */
157 if ((addr & (DATA_SIZE - 1)) != 0)
158 goto do_unaligned_access;
Paul Brook355b1942010-04-05 00:28:53 +0100159 ioaddr = env->iotlb[mmu_idx][index];
160 res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000161 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000162 do_unaligned_access:
163 /* slow unaligned access (it spans two pages) */
164 addr1 = addr & ~(DATA_SIZE - 1);
165 addr2 = addr1 + DATA_SIZE;
ths5fafdf22007-09-16 21:08:06 +0000166 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
j_mayer6ebbf392007-10-14 07:07:08 +0000167 mmu_idx, retaddr);
ths5fafdf22007-09-16 21:08:06 +0000168 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
j_mayer6ebbf392007-10-14 07:07:08 +0000169 mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000170 shift = (addr & (DATA_SIZE - 1)) * 8;
171#ifdef TARGET_WORDS_BIGENDIAN
172 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
173#else
174 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
175#endif
bellard6986f882004-01-18 21:53:18 +0000176 res = (DATA_TYPE)res;
bellardb92e5a22003-08-08 23:58:05 +0000177 } else {
178 /* unaligned/aligned access in the same page */
pbrook0f459d12008-06-09 00:20:13 +0000179 addend = env->tlb_table[mmu_idx][index].addend;
180 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
bellardb92e5a22003-08-08 23:58:05 +0000181 }
182 } else {
183 /* the page is not in the TLB : fill it */
j_mayer6ebbf392007-10-14 07:07:08 +0000184 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000185 goto redo;
186 }
187 return res;
188}
189
bellardb769d8f2004-10-03 15:07:13 +0000190#ifndef SOFTMMU_CODE_ACCESS
191
ths5fafdf22007-09-16 21:08:06 +0000192static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
193 DATA_TYPE val,
j_mayer6ebbf392007-10-14 07:07:08 +0000194 int mmu_idx,
bellardb769d8f2004-10-03 15:07:13 +0000195 void *retaddr);
196
Anthony Liguoric227f092009-10-01 16:12:16 -0500197static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
bellardb769d8f2004-10-03 15:07:13 +0000198 DATA_TYPE val,
pbrook0f459d12008-06-09 00:20:13 +0000199 target_ulong addr,
bellardb769d8f2004-10-03 15:07:13 +0000200 void *retaddr)
201{
202 int index;
pbrook0f459d12008-06-09 00:20:13 +0000203 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
204 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
pbrook2e70f6e2008-06-29 01:03:05 +0000205 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
206 && !can_do_io(env)) {
207 cpu_io_recompile(env, retaddr);
208 }
bellardb769d8f2004-10-03 15:07:13 +0000209
pbrook2e70f6e2008-06-29 01:03:05 +0000210 env->mem_io_vaddr = addr;
211 env->mem_io_pc = (unsigned long)retaddr;
bellardb769d8f2004-10-03 15:07:13 +0000212#if SHIFT <= 2
213 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
214#else
215#ifdef TARGET_WORDS_BIGENDIAN
216 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
217 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
218#else
219 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
220 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
221#endif
222#endif /* SHIFT > 2 */
223}
bellardb92e5a22003-08-08 23:58:05 +0000224
bellardd6564692008-01-31 09:22:27 +0000225void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
226 DATA_TYPE val,
227 int mmu_idx)
bellardb92e5a22003-08-08 23:58:05 +0000228{
Paul Brook355b1942010-04-05 00:28:53 +0100229 target_phys_addr_t ioaddr;
230 unsigned long addend;
bellardc27004e2005-01-03 23:35:10 +0000231 target_ulong tlb_addr;
bellardb92e5a22003-08-08 23:58:05 +0000232 void *retaddr;
bellard61382a52003-10-27 21:22:23 +0000233 int index;
ths3b46e622007-09-17 08:09:54 +0000234
bellardb92e5a22003-08-08 23:58:05 +0000235 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
236 redo:
j_mayer6ebbf392007-10-14 07:07:08 +0000237 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
bellardb92e5a22003-08-08 23:58:05 +0000238 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellardb92e5a22003-08-08 23:58:05 +0000239 if (tlb_addr & ~TARGET_PAGE_MASK) {
240 /* IO access */
241 if ((addr & (DATA_SIZE - 1)) != 0)
242 goto do_unaligned_access;
bellardd720b932004-04-25 17:57:43 +0000243 retaddr = GETPC();
Paul Brook355b1942010-04-05 00:28:53 +0100244 ioaddr = env->iotlb[mmu_idx][index];
245 glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000246 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000247 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +0000248 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000249#ifdef ALIGNED_ONLY
j_mayer6ebbf392007-10-14 07:07:08 +0000250 do_unaligned_access(addr, 1, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000251#endif
ths5fafdf22007-09-16 21:08:06 +0000252 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
j_mayer6ebbf392007-10-14 07:07:08 +0000253 mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000254 } else {
255 /* aligned/unaligned access in the same page */
bellarda64d4712005-12-05 19:57:57 +0000256#ifdef ALIGNED_ONLY
257 if ((addr & (DATA_SIZE - 1)) != 0) {
258 retaddr = GETPC();
j_mayer6ebbf392007-10-14 07:07:08 +0000259 do_unaligned_access(addr, 1, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000260 }
261#endif
pbrook0f459d12008-06-09 00:20:13 +0000262 addend = env->tlb_table[mmu_idx][index].addend;
263 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
bellardb92e5a22003-08-08 23:58:05 +0000264 }
265 } else {
266 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000267 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000268#ifdef ALIGNED_ONLY
269 if ((addr & (DATA_SIZE - 1)) != 0)
j_mayer6ebbf392007-10-14 07:07:08 +0000270 do_unaligned_access(addr, 1, mmu_idx, retaddr);
bellarda64d4712005-12-05 19:57:57 +0000271#endif
j_mayer6ebbf392007-10-14 07:07:08 +0000272 tlb_fill(addr, 1, mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000273 goto redo;
274 }
275}
276
277/* handles all unaligned cases */
ths5fafdf22007-09-16 21:08:06 +0000278static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000279 DATA_TYPE val,
j_mayer6ebbf392007-10-14 07:07:08 +0000280 int mmu_idx,
bellard61382a52003-10-27 21:22:23 +0000281 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000282{
Paul Brook355b1942010-04-05 00:28:53 +0100283 target_phys_addr_t ioaddr;
284 unsigned long addend;
bellardc27004e2005-01-03 23:35:10 +0000285 target_ulong tlb_addr;
bellard61382a52003-10-27 21:22:23 +0000286 int index, i;
bellardb92e5a22003-08-08 23:58:05 +0000287
bellardb92e5a22003-08-08 23:58:05 +0000288 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
289 redo:
j_mayer6ebbf392007-10-14 07:07:08 +0000290 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
bellardb92e5a22003-08-08 23:58:05 +0000291 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellardb92e5a22003-08-08 23:58:05 +0000292 if (tlb_addr & ~TARGET_PAGE_MASK) {
293 /* IO access */
294 if ((addr & (DATA_SIZE - 1)) != 0)
295 goto do_unaligned_access;
Paul Brook355b1942010-04-05 00:28:53 +0100296 ioaddr = env->iotlb[mmu_idx][index];
297 glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000298 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000299 do_unaligned_access:
300 /* XXX: not efficient, but simple */
balrog6c41b272007-11-17 12:12:29 +0000301 /* Note: relies on the fact that tlb_fill() does not remove the
302 * previous page from the TLB cache. */
balrog7221fa92007-11-17 09:53:42 +0000303 for(i = DATA_SIZE - 1; i >= 0; i--) {
bellardb92e5a22003-08-08 23:58:05 +0000304#ifdef TARGET_WORDS_BIGENDIAN
ths5fafdf22007-09-16 21:08:06 +0000305 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
j_mayer6ebbf392007-10-14 07:07:08 +0000306 mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000307#else
ths5fafdf22007-09-16 21:08:06 +0000308 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
j_mayer6ebbf392007-10-14 07:07:08 +0000309 mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000310#endif
311 }
312 } else {
313 /* aligned/unaligned access in the same page */
pbrook0f459d12008-06-09 00:20:13 +0000314 addend = env->tlb_table[mmu_idx][index].addend;
315 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
bellardb92e5a22003-08-08 23:58:05 +0000316 }
317 } else {
318 /* the page is not in the TLB : fill it */
j_mayer6ebbf392007-10-14 07:07:08 +0000319 tlb_fill(addr, 1, mmu_idx, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000320 goto redo;
321 }
322}
323
bellardb769d8f2004-10-03 15:07:13 +0000324#endif /* !defined(SOFTMMU_CODE_ACCESS) */
325
326#undef READ_ACCESS_TYPE
bellardb92e5a22003-08-08 23:58:05 +0000327#undef SHIFT
328#undef DATA_TYPE
329#undef SUFFIX
bellard61382a52003-10-27 21:22:23 +0000330#undef USUFFIX
bellardb92e5a22003-08-08 23:58:05 +0000331#undef DATA_SIZE
bellard84b7b8e2005-11-28 21:19:04 +0000332#undef ADDR_READ