blob: 3d79c73fdaadb39e15bf6c47a88e90ebb6e2e212 [file] [log] [blame]
pbrook502a5392006-05-13 16:11:23 +00001/*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
pbrook502a5392006-05-13 16:11:23 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
26#include "pc.h"
Michael S. Tsirkina2cb15b2012-12-12 14:24:50 +020027#include "pci/pci.h"
28#include "pci/pci_host.h"
Gerd Hoffmannf75247f2009-07-31 12:30:16 +020029#include "isa.h"
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +020030#include "sysbus.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010031#include "qemu/range.h"
Anthony PERARD41445302010-07-16 14:55:39 +010032#include "xen.h"
Isaku Yamahata410edd92012-11-14 15:54:02 -050033#include "pam.h"
pbrook87ecb682007-11-17 17:14:51 +000034
Isaku Yamahata56594fe2009-12-15 20:26:07 +090035/*
36 * I440FX chipset data sheet.
37 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
38 */
39
Andreas Färber67c332f2012-08-20 19:08:09 +020040typedef struct I440FXState {
41 PCIHostState parent_obj;
42} I440FXState;
pbrook502a5392006-05-13 16:11:23 +000043
Isaku Yamahataab431c22011-04-01 20:43:23 +090044#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
Isaku Yamahatae735b552011-04-01 20:43:22 +090045#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
Stefano Stabellinibf095512011-06-15 17:36:56 +010046#define XEN_PIIX_NUM_PIRQS 128ULL
Isaku Yamahataab431c22011-04-01 20:43:23 +090047#define PIIX_PIRQC 0x60
Isaku Yamahatae735b552011-04-01 20:43:22 +090048
Juan Quintelafd37d882009-08-28 15:28:18 +020049typedef struct PIIX3State {
50 PCIDevice dev;
Isaku Yamahataab431c22011-04-01 20:43:23 +090051
52 /*
53 * bitmap to track pic levels.
54 * The pic level is the logical OR of all the PCI irqs mapped to it
55 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
56 *
57 * PIRQ is mapped to PIC pins, we track it by
58 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
59 * pic_irq * PIIX_NUM_PIRQS + pirq
60 */
61#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
62#error "unable to encode pic state in 64bit in pic_levels."
63#endif
64 uint64_t pic_levels;
65
Juan Quintelabd7dce82009-08-28 15:28:19 +020066 qemu_irq *pic;
Isaku Yamahatae735b552011-04-01 20:43:22 +090067
68 /* This member isn't used. Just for save/load compatibility */
69 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
Gerd Hoffmann7cd9eee2009-09-16 22:25:33 +020070} PIIX3State;
Juan Quintelabd7dce82009-08-28 15:28:19 +020071
Juan Quintela0a3bacf2009-08-28 15:28:15 +020072struct PCII440FXState {
73 PCIDevice dev;
Avi Kivityae0a5462011-08-15 17:17:38 +030074 MemoryRegion *system_memory;
75 MemoryRegion *pci_address_space;
76 MemoryRegion *ram_memory;
77 MemoryRegion pci_hole;
78 MemoryRegion pci_hole_64bit;
79 PAMMemoryRegion pam_regions[13];
80 MemoryRegion smram_region;
Juan Quintela6c009fa2009-08-28 15:28:16 +020081 uint8_t smm_enabled;
Juan Quintela0a3bacf2009-08-28 15:28:15 +020082};
83
Isaku Yamahataf2c688b2009-12-15 20:26:05 +090084
85#define I440FX_PAM 0x59
86#define I440FX_PAM_SIZE 7
87#define I440FX_SMRAM 0x72
88
Isaku Yamahataab431c22011-04-01 20:43:23 +090089static void piix3_set_irq(void *opaque, int pirq, int level);
Michael S. Tsirkin3afa9bb2012-07-19 17:11:47 +030090static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
Stefano Stabellinibf095512011-06-15 17:36:56 +010091static void piix3_write_config_xen(PCIDevice *dev,
92 uint32_t address, uint32_t val, int len);
pbrookd2b59312006-09-24 00:16:34 +000093
94/* return the global irq number corresponding to a given device irq
95 pin. We could also use the bus number to have a more precise
96 mapping. */
Isaku Yamahataab431c22011-04-01 20:43:23 +090097static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
pbrookd2b59312006-09-24 00:16:34 +000098{
99 int slot_addend;
100 slot_addend = (pci_dev->devfn >> 3) - 1;
Isaku Yamahataab431c22011-04-01 20:43:23 +0900101 return (pci_intx + slot_addend) & 3;
pbrookd2b59312006-09-24 00:16:34 +0000102}
pbrook502a5392006-05-13 16:11:23 +0000103
Isaku Yamahata410edd92012-11-14 15:54:02 -0500104static void i440fx_update_memory_mappings(PCII440FXState *d)
bellard84631fd2006-09-24 19:31:43 +0000105{
Avi Kivity2725aec2012-10-17 17:10:04 +0200106 int i;
bellard84631fd2006-09-24 19:31:43 +0000107
Avi Kivity72124c02011-08-01 11:04:39 +0300108 memory_region_transaction_begin();
Isaku Yamahata410edd92012-11-14 15:54:02 -0500109 for (i = 0; i < 13; i++) {
110 pam_update(&d->pam_regions[i], i,
111 d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
bellardee0ea1d2006-09-24 18:49:13 +0000112 }
Isaku Yamahata410edd92012-11-14 15:54:02 -0500113 smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
Avi Kivity72124c02011-08-01 11:04:39 +0300114 memory_region_transaction_commit();
bellardee0ea1d2006-09-24 18:49:13 +0000115}
116
Isaku Yamahataf885f1e2010-05-14 16:29:04 +0900117static void i440fx_set_smm(int val, void *arg)
bellardee0ea1d2006-09-24 18:49:13 +0000118{
Isaku Yamahataf885f1e2010-05-14 16:29:04 +0900119 PCII440FXState *d = arg;
120
Isaku Yamahata410edd92012-11-14 15:54:02 -0500121 memory_region_transaction_begin();
122 smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
123 &d->smram_region);
124 memory_region_transaction_commit();
bellardee0ea1d2006-09-24 18:49:13 +0000125}
126
127
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200128static void i440fx_write_config(PCIDevice *dev,
bellardee0ea1d2006-09-24 18:49:13 +0000129 uint32_t address, uint32_t val, int len)
130{
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200131 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
132
bellardee0ea1d2006-09-24 18:49:13 +0000133 /* XXX: implement SMRAM.D_LOCK */
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200134 pci_default_write_config(dev, address, val, len);
Isaku Yamahata4da5fcd2009-12-15 20:26:06 +0900135 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
136 range_covers_byte(address, len, I440FX_SMRAM)) {
bellardee0ea1d2006-09-24 18:49:13 +0000137 i440fx_update_memory_mappings(d);
Isaku Yamahata4da5fcd2009-12-15 20:26:06 +0900138 }
bellardee0ea1d2006-09-24 18:49:13 +0000139}
140
Juan Quintela0c7d19e2009-08-28 15:28:26 +0200141static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
bellardee0ea1d2006-09-24 18:49:13 +0000142{
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200143 PCII440FXState *d = opaque;
balrog52fc1d82007-12-09 23:56:13 +0000144 int ret, i;
bellardee0ea1d2006-09-24 18:49:13 +0000145
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200146 ret = pci_device_load(&d->dev, f);
bellardee0ea1d2006-09-24 18:49:13 +0000147 if (ret < 0)
148 return ret;
149 i440fx_update_memory_mappings(d);
Juan Quintela6c009fa2009-08-28 15:28:16 +0200150 qemu_get_8s(f, &d->smm_enabled);
balrog52fc1d82007-12-09 23:56:13 +0000151
Isaku Yamahatae735b552011-04-01 20:43:22 +0900152 if (version_id == 2) {
153 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
154 qemu_get_be32(f); /* dummy load for compatibility */
155 }
156 }
balrog52fc1d82007-12-09 23:56:13 +0000157
bellardee0ea1d2006-09-24 18:49:13 +0000158 return 0;
159}
160
Juan Quintelae59fb372009-09-29 22:48:21 +0200161static int i440fx_post_load(void *opaque, int version_id)
Juan Quintela0c7d19e2009-08-28 15:28:26 +0200162{
163 PCII440FXState *d = opaque;
164
165 i440fx_update_memory_mappings(d);
166 return 0;
167}
168
169static const VMStateDescription vmstate_i440fx = {
170 .name = "I440FX",
171 .version_id = 3,
172 .minimum_version_id = 3,
173 .minimum_version_id_old = 1,
174 .load_state_old = i440fx_load_old,
Juan Quintela752ff2f2009-09-10 03:04:30 +0200175 .post_load = i440fx_post_load,
Juan Quintela0c7d19e2009-08-28 15:28:26 +0200176 .fields = (VMStateField []) {
177 VMSTATE_PCI_DEVICE(dev, PCII440FXState),
178 VMSTATE_UINT8(smm_enabled, PCII440FXState),
179 VMSTATE_END_OF_LIST()
180 }
181};
182
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200183static int i440fx_pcihost_initfn(SysBusDevice *dev)
pbrook502a5392006-05-13 16:11:23 +0000184{
Andreas Färber8558d942012-08-20 19:08:08 +0200185 PCIHostState *s = PCI_HOST_BRIDGE(dev);
pbrook502a5392006-05-13 16:11:23 +0000186
Avi Kivityd0ed8072011-07-24 17:47:18 +0300187 memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
188 "pci-conf-idx", 4);
189 sysbus_add_io(dev, 0xcf8, &s->conf_mem);
190 sysbus_init_ioports(&s->busdev, 0xcf8, 4);
pbrook502a5392006-05-13 16:11:23 +0000191
Avi Kivityd0ed8072011-07-24 17:47:18 +0300192 memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
193 "pci-conf-data", 4);
194 sysbus_add_io(dev, 0xcfc, &s->data_mem);
195 sysbus_init_ioports(&s->busdev, 0xcfc, 4);
196
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200197 return 0;
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200198}
pbrook502a5392006-05-13 16:11:23 +0000199
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200200static int i440fx_initfn(PCIDevice *dev)
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200201{
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200202 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
bellardee0ea1d2006-09-24 18:49:13 +0000203
Isaku Yamahataf2c688b2009-12-15 20:26:05 +0900204 d->dev.config[I440FX_SMRAM] = 0x02;
bellardee0ea1d2006-09-24 18:49:13 +0000205
Isaku Yamahataf885f1e2010-05-14 16:29:04 +0900206 cpu_smm_register(&i440fx_set_smm, d);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200207 return 0;
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200208}
209
Anthony PERARD41445302010-07-16 14:55:39 +0100210static PCIBus *i440fx_common_init(const char *device_name,
211 PCII440FXState **pi440fx_state,
212 int *piix3_devfn,
Hervé Poussineau60573072011-12-15 22:09:54 +0100213 ISABus **isa_bus, qemu_irq *pic,
Avi Kivityaee97b82011-08-08 16:09:04 +0300214 MemoryRegion *address_space_mem,
215 MemoryRegion *address_space_io,
Avi Kivityae0a5462011-08-15 17:17:38 +0300216 ram_addr_t ram_size,
Avi Kivitya8170e52012-10-23 12:30:10 +0200217 hwaddr pci_hole_start,
218 hwaddr pci_hole_size,
219 hwaddr pci_hole64_start,
220 hwaddr pci_hole64_size,
Avi Kivityae0a5462011-08-15 17:17:38 +0300221 MemoryRegion *pci_address_space,
222 MemoryRegion *ram_memory)
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200223{
224 DeviceState *dev;
225 PCIBus *b;
226 PCIDevice *d;
Andreas Färber8558d942012-08-20 19:08:08 +0200227 PCIHostState *s;
Gerd Hoffmann7cd9eee2009-09-16 22:25:33 +0200228 PIIX3State *piix3;
Avi Kivityae0a5462011-08-15 17:17:38 +0300229 PCII440FXState *f;
Avi Kivity2725aec2012-10-17 17:10:04 +0200230 unsigned i;
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200231
232 dev = qdev_create(NULL, "i440FX-pcihost");
Andreas Färber8558d942012-08-20 19:08:08 +0200233 s = PCI_HOST_BRIDGE(dev);
Avi Kivityaee97b82011-08-08 16:09:04 +0300234 s->address_space = address_space_mem;
Andreas Färber67c332f2012-08-20 19:08:09 +0200235 b = pci_bus_new(dev, NULL, pci_address_space,
Avi Kivityaee97b82011-08-08 16:09:04 +0300236 address_space_io, 0);
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200237 s->bus = b;
Paolo Bonzinif05f6b42012-03-28 16:34:12 +0200238 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
Paolo Bonzinif424d5c2012-03-27 18:38:46 +0200239 qdev_init_nofail(dev);
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200240
Anthony PERARD41445302010-07-16 14:55:39 +0100241 d = pci_create_simple(b, 0, device_name);
Juan Quintela0a3bacf2009-08-28 15:28:15 +0200242 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
Avi Kivityae0a5462011-08-15 17:17:38 +0300243 f = *pi440fx_state;
244 f->system_memory = address_space_mem;
245 f->pci_address_space = pci_address_space;
246 f->ram_memory = ram_memory;
247 memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
248 pci_hole_start, pci_hole_size);
249 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
250 memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
251 f->pci_address_space,
252 pci_hole64_start, pci_hole64_size);
253 if (pci_hole64_size) {
254 memory_region_add_subregion(f->system_memory, pci_hole64_start,
255 &f->pci_hole_64bit);
256 }
257 memory_region_init_alias(&f->smram_region, "smram-region",
258 f->pci_address_space, 0xa0000, 0x20000);
Avi Kivityb41e1ed2011-12-04 20:06:16 +0200259 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
260 &f->smram_region, 1);
261 memory_region_set_enabled(&f->smram_region, false);
Isaku Yamahata410edd92012-11-14 15:54:02 -0500262 init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
263 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
Avi Kivity2725aec2012-10-17 17:10:04 +0200264 for (i = 0; i < 12; ++i) {
Isaku Yamahata410edd92012-11-14 15:54:02 -0500265 init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
266 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
267 PAM_EXPAN_SIZE);
Avi Kivity2725aec2012-10-17 17:10:04 +0200268 }
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200269
Stefano Stabellinibf095512011-06-15 17:36:56 +0100270 /* Xen supports additional interrupt routes from the PCI devices to
271 * the IOAPIC: the four pins of each PCI device on the bus are also
272 * connected to the IOAPIC directly.
273 * These additional routes can be discovered through ACPI. */
274 if (xen_enabled()) {
275 piix3 = DO_UPCAST(PIIX3State, dev,
276 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
277 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
278 piix3, XEN_PIIX_NUM_PIRQS);
279 } else {
280 piix3 = DO_UPCAST(PIIX3State, dev,
281 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
282 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
283 PIIX_NUM_PIRQS);
Michael S. Tsirkin3afa9bb2012-07-19 17:11:47 +0300284 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
Stefano Stabellinibf095512011-06-15 17:36:56 +0100285 }
Gerd Hoffmann7cd9eee2009-09-16 22:25:33 +0200286 piix3->pic = pic;
Hervé Poussineau60573072011-12-15 22:09:54 +0100287 *isa_bus = DO_UPCAST(ISABus, qbus,
288 qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
Anthony PERARD41445302010-07-16 14:55:39 +0100289
Gerd Hoffmann7cd9eee2009-09-16 22:25:33 +0200290 *piix3_devfn = piix3->dev.devfn;
Juan Quintela85a750c2009-08-28 15:28:20 +0200291
Bernhard M. Wiedemannec5f92c2010-04-20 20:48:06 +0200292 ram_size = ram_size / 8 / 1024 / 1024;
293 if (ram_size > 255)
294 ram_size = 255;
295 (*pi440fx_state)->dev.config[0x57]=ram_size;
296
Avi Kivityae0a5462011-08-15 17:17:38 +0300297 i440fx_update_memory_mappings(f);
298
pbrook502a5392006-05-13 16:11:23 +0000299 return b;
300}
301
Anthony PERARD41445302010-07-16 14:55:39 +0100302PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
Hervé Poussineau60573072011-12-15 22:09:54 +0100303 ISABus **isa_bus, qemu_irq *pic,
Avi Kivityaee97b82011-08-08 16:09:04 +0300304 MemoryRegion *address_space_mem,
305 MemoryRegion *address_space_io,
Avi Kivityae0a5462011-08-15 17:17:38 +0300306 ram_addr_t ram_size,
Avi Kivitya8170e52012-10-23 12:30:10 +0200307 hwaddr pci_hole_start,
308 hwaddr pci_hole_size,
309 hwaddr pci_hole64_start,
310 hwaddr pci_hole64_size,
Avi Kivityae0a5462011-08-15 17:17:38 +0300311 MemoryRegion *pci_memory, MemoryRegion *ram_memory)
312
Anthony PERARD41445302010-07-16 14:55:39 +0100313{
314 PCIBus *b;
315
Hervé Poussineau60573072011-12-15 22:09:54 +0100316 b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
Avi Kivityae0a5462011-08-15 17:17:38 +0300317 address_space_mem, address_space_io, ram_size,
318 pci_hole_start, pci_hole_size,
Alexey Korolevd50c6c82012-02-29 14:35:14 +1300319 pci_hole64_start, pci_hole64_size,
Avi Kivityae0a5462011-08-15 17:17:38 +0300320 pci_memory, ram_memory);
Anthony PERARD41445302010-07-16 14:55:39 +0100321 return b;
322}
323
pbrook502a5392006-05-13 16:11:23 +0000324/* PIIX3 PCI to ISA bridge */
Isaku Yamahataab431c22011-04-01 20:43:23 +0900325static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
pbrook502a5392006-05-13 16:11:23 +0000326{
Isaku Yamahataab431c22011-04-01 20:43:23 +0900327 qemu_set_irq(piix3->pic[pic_irq],
328 !!(piix3->pic_levels &
TeLeMan09de0f42011-05-16 19:50:55 +0800329 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
Isaku Yamahataab431c22011-04-01 20:43:23 +0900330 (pic_irq * PIIX_NUM_PIRQS))));
331}
pbrook502a5392006-05-13 16:11:23 +0000332
Isaku Yamahataafe3ef12011-04-01 20:43:24 +0900333static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
Isaku Yamahataab431c22011-04-01 20:43:23 +0900334{
335 int pic_irq;
336 uint64_t mask;
337
338 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
339 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
340 return;
341 }
342
343 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
344 piix3->pic_levels &= ~mask;
345 piix3->pic_levels |= mask * !!level;
346
Isaku Yamahataafe3ef12011-04-01 20:43:24 +0900347 piix3_set_irq_pic(piix3, pic_irq);
Isaku Yamahataab431c22011-04-01 20:43:23 +0900348}
349
350static void piix3_set_irq(void *opaque, int pirq, int level)
351{
352 PIIX3State *piix3 = opaque;
Isaku Yamahataafe3ef12011-04-01 20:43:24 +0900353 piix3_set_irq_level(piix3, pirq, level);
Isaku Yamahataab431c22011-04-01 20:43:23 +0900354}
355
Michael S. Tsirkin3afa9bb2012-07-19 17:11:47 +0300356static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
357{
358 PIIX3State *piix3 = opaque;
359 int irq = piix3->dev.config[PIIX_PIRQC + pin];
360 PCIINTxRoute route;
361
362 if (irq < PIIX_NUM_PIC_IRQS) {
363 route.mode = PCI_INTX_ENABLED;
364 route.irq = irq;
365 } else {
366 route.mode = PCI_INTX_DISABLED;
367 route.irq = -1;
368 }
369 return route;
370}
371
Isaku Yamahataab431c22011-04-01 20:43:23 +0900372/* irq routing is changed. so rebuild bitmap */
373static void piix3_update_irq_levels(PIIX3State *piix3)
374{
375 int pirq;
376
377 piix3->pic_levels = 0;
378 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
379 piix3_set_irq_level(piix3, pirq,
Isaku Yamahataafe3ef12011-04-01 20:43:24 +0900380 pci_bus_get_irq_level(piix3->dev.bus, pirq));
Isaku Yamahataab431c22011-04-01 20:43:23 +0900381 }
382}
383
384static void piix3_write_config(PCIDevice *dev,
385 uint32_t address, uint32_t val, int len)
386{
387 pci_default_write_config(dev, address, val, len);
388 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
389 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
390 int pic_irq;
Jan Kiszka0ae16252012-07-02 14:38:47 +0200391
392 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
Isaku Yamahataab431c22011-04-01 20:43:23 +0900393 piix3_update_irq_levels(piix3);
394 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
395 piix3_set_irq_pic(piix3, pic_irq);
pbrookd2b59312006-09-24 00:16:34 +0000396 }
pbrook502a5392006-05-13 16:11:23 +0000397 }
398}
399
Stefano Stabellinibf095512011-06-15 17:36:56 +0100400static void piix3_write_config_xen(PCIDevice *dev,
401 uint32_t address, uint32_t val, int len)
402{
403 xen_piix_pci_write_config_client(address, val, len);
404 piix3_write_config(dev, address, val, len);
405}
406
Gleb Natapov15a19562009-06-17 19:32:01 +0300407static void piix3_reset(void *opaque)
pbrook502a5392006-05-13 16:11:23 +0000408{
Juan Quintelafd37d882009-08-28 15:28:18 +0200409 PIIX3State *d = opaque;
410 uint8_t *pci_conf = d->dev.config;
pbrook502a5392006-05-13 16:11:23 +0000411
412 pci_conf[0x04] = 0x07; // master, memory and I/O
413 pci_conf[0x05] = 0x00;
414 pci_conf[0x06] = 0x00;
415 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
416 pci_conf[0x4c] = 0x4d;
417 pci_conf[0x4e] = 0x03;
418 pci_conf[0x4f] = 0x00;
419 pci_conf[0x60] = 0x80;
aurel32477afee2008-03-28 22:28:45 +0000420 pci_conf[0x61] = 0x80;
421 pci_conf[0x62] = 0x80;
422 pci_conf[0x63] = 0x80;
pbrook502a5392006-05-13 16:11:23 +0000423 pci_conf[0x69] = 0x02;
424 pci_conf[0x70] = 0x80;
425 pci_conf[0x76] = 0x0c;
426 pci_conf[0x77] = 0x0c;
427 pci_conf[0x78] = 0x02;
428 pci_conf[0x79] = 0x00;
429 pci_conf[0x80] = 0x00;
430 pci_conf[0x82] = 0x00;
431 pci_conf[0xa0] = 0x08;
pbrook502a5392006-05-13 16:11:23 +0000432 pci_conf[0xa2] = 0x00;
433 pci_conf[0xa3] = 0x00;
434 pci_conf[0xa4] = 0x00;
435 pci_conf[0xa5] = 0x00;
436 pci_conf[0xa6] = 0x00;
437 pci_conf[0xa7] = 0x00;
438 pci_conf[0xa8] = 0x0f;
439 pci_conf[0xaa] = 0x00;
440 pci_conf[0xab] = 0x00;
441 pci_conf[0xac] = 0x00;
442 pci_conf[0xae] = 0x00;
Isaku Yamahataab431c22011-04-01 20:43:23 +0900443
444 d->pic_levels = 0;
445}
446
447static int piix3_post_load(void *opaque, int version_id)
448{
449 PIIX3State *piix3 = opaque;
450 piix3_update_irq_levels(piix3);
451 return 0;
Isaku Yamahatae735b552011-04-01 20:43:22 +0900452}
Gleb Natapov15a19562009-06-17 19:32:01 +0300453
Isaku Yamahatae735b552011-04-01 20:43:22 +0900454static void piix3_pre_save(void *opaque)
455{
456 int i;
457 PIIX3State *piix3 = opaque;
458
459 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
460 piix3->pci_irq_levels_vmstate[i] =
461 pci_bus_get_irq_level(piix3->dev.bus, i);
462 }
pbrook502a5392006-05-13 16:11:23 +0000463}
464
Juan Quintelad1f171b2009-08-28 15:28:27 +0200465static const VMStateDescription vmstate_piix3 = {
466 .name = "PIIX3",
467 .version_id = 3,
468 .minimum_version_id = 2,
469 .minimum_version_id_old = 2,
Isaku Yamahataab431c22011-04-01 20:43:23 +0900470 .post_load = piix3_post_load,
Isaku Yamahatae735b552011-04-01 20:43:22 +0900471 .pre_save = piix3_pre_save,
Juan Quintelad1f171b2009-08-28 15:28:27 +0200472 .fields = (VMStateField []) {
473 VMSTATE_PCI_DEVICE(dev, PIIX3State),
Isaku Yamahatae735b552011-04-01 20:43:22 +0900474 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
475 PIIX_NUM_PIRQS, 3),
Juan Quintelad1f171b2009-08-28 15:28:27 +0200476 VMSTATE_END_OF_LIST()
Juan Quintelada641822009-08-28 15:28:24 +0200477 }
Juan Quintelad1f171b2009-08-28 15:28:27 +0200478};
bellard1941d192006-08-17 10:46:34 +0000479
Juan Quintelafd37d882009-08-28 15:28:18 +0200480static int piix3_initfn(PCIDevice *dev)
pbrook502a5392006-05-13 16:11:23 +0000481{
Juan Quintelafd37d882009-08-28 15:28:18 +0200482 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
pbrook502a5392006-05-13 16:11:23 +0000483
Richard Hendersonc2d0d012011-08-10 15:28:11 -0700484 isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200485 qemu_register_reset(piix3_reset, d);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200486 return 0;
pbrook502a5392006-05-13 16:11:23 +0000487}
ths5c2b87e2007-01-15 17:08:08 +0000488
Anthony Liguori40021f02011-12-04 12:22:06 -0600489static void piix3_class_init(ObjectClass *klass, void *data)
490{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600491 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600492 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
493
Anthony Liguori39bffca2011-12-07 21:34:16 -0600494 dc->desc = "ISA bridge";
495 dc->vmsd = &vmstate_piix3;
496 dc->no_user = 1,
Anthony Liguori40021f02011-12-04 12:22:06 -0600497 k->no_hotplug = 1;
498 k->init = piix3_initfn;
499 k->config_write = piix3_write_config;
500 k->vendor_id = PCI_VENDOR_ID_INTEL;
501 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
502 k->class_id = PCI_CLASS_BRIDGE_ISA;
503}
504
Andreas Färber4240abf2012-08-20 19:07:56 +0200505static const TypeInfo piix3_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600506 .name = "PIIX3",
507 .parent = TYPE_PCI_DEVICE,
508 .instance_size = sizeof(PIIX3State),
509 .class_init = piix3_class_init,
Anthony Liguorie8557612011-12-06 19:32:44 -0600510};
511
Anthony Liguori40021f02011-12-04 12:22:06 -0600512static void piix3_xen_class_init(ObjectClass *klass, void *data)
513{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600514 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600515 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
516
Anthony Liguori39bffca2011-12-07 21:34:16 -0600517 dc->desc = "ISA bridge";
518 dc->vmsd = &vmstate_piix3;
519 dc->no_user = 1;
Anthony Liguori40021f02011-12-04 12:22:06 -0600520 k->no_hotplug = 1;
521 k->init = piix3_initfn;
522 k->config_write = piix3_write_config_xen;
523 k->vendor_id = PCI_VENDOR_ID_INTEL;
524 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
525 k->class_id = PCI_CLASS_BRIDGE_ISA;
Anthony Liguorie8557612011-12-06 19:32:44 -0600526};
527
Andreas Färber4240abf2012-08-20 19:07:56 +0200528static const TypeInfo piix3_xen_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600529 .name = "PIIX3-xen",
530 .parent = TYPE_PCI_DEVICE,
531 .instance_size = sizeof(PIIX3State),
532 .class_init = piix3_xen_class_init,
Anthony Liguori40021f02011-12-04 12:22:06 -0600533};
534
535static void i440fx_class_init(ObjectClass *klass, void *data)
536{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600537 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600538 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
539
540 k->no_hotplug = 1;
541 k->init = i440fx_initfn;
542 k->config_write = i440fx_write_config;
543 k->vendor_id = PCI_VENDOR_ID_INTEL;
544 k->device_id = PCI_DEVICE_ID_INTEL_82441;
545 k->revision = 0x02;
546 k->class_id = PCI_CLASS_BRIDGE_HOST;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600547 dc->desc = "Host bridge";
548 dc->no_user = 1;
549 dc->vmsd = &vmstate_i440fx;
Anthony Liguori40021f02011-12-04 12:22:06 -0600550}
551
Andreas Färber4240abf2012-08-20 19:07:56 +0200552static const TypeInfo i440fx_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600553 .name = "i440FX",
554 .parent = TYPE_PCI_DEVICE,
555 .instance_size = sizeof(PCII440FXState),
556 .class_init = i440fx_class_init,
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200557};
558
Anthony Liguori999e12b2012-01-24 13:12:29 -0600559static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
560{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600561 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600562 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
563
564 k->init = i440fx_pcihost_initfn;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600565 dc->fw_name = "pci";
566 dc->no_user = 1;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600567}
568
Andreas Färber4240abf2012-08-20 19:07:56 +0200569static const TypeInfo i440fx_pcihost_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600570 .name = "i440FX-pcihost",
Andreas Färber8558d942012-08-20 19:08:08 +0200571 .parent = TYPE_PCI_HOST_BRIDGE,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600572 .instance_size = sizeof(I440FXState),
573 .class_init = i440fx_pcihost_class_init,
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200574};
575
Andreas Färber83f7d432012-02-09 15:20:55 +0100576static void i440fx_register_types(void)
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200577{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600578 type_register_static(&i440fx_info);
579 type_register_static(&piix3_info);
580 type_register_static(&piix3_xen_info);
581 type_register_static(&i440fx_pcihost_info);
Gerd Hoffmann8a14daa2009-07-22 15:17:01 +0200582}
Andreas Färber83f7d432012-02-09 15:20:55 +0100583
584type_init(i440fx_register_types)