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Blue Swirl1bccec22011-08-01 07:37:45 +00001/*
2 * FPU op helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
Peter Maydelldb5ebe52016-01-26 18:16:59 +000020#include "qemu/osdep.h"
Blue Swirl1bccec22011-08-01 07:37:45 +000021#include "cpu.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070022#include "exec/helper-proto.h"
Blue Swirl1bccec22011-08-01 07:37:45 +000023
Blue Swirl1bccec22011-08-01 07:37:45 +000024#define QT0 (env->qt0)
25#define QT1 (env->qt1)
26
Andreas Färberc5f98642012-03-14 01:38:22 +010027static void check_ieee_exceptions(CPUSPARCState *env)
Richard Henderson44516772011-10-17 11:25:56 -070028{
29 target_ulong status;
30
31 status = get_float_exception_flags(&env->fp_status);
32 if (status) {
33 /* Copy IEEE 754 flags into FSR */
34 if (status & float_flag_invalid) {
35 env->fsr |= FSR_NVC;
36 }
37 if (status & float_flag_overflow) {
38 env->fsr |= FSR_OFC;
39 }
40 if (status & float_flag_underflow) {
41 env->fsr |= FSR_UFC;
42 }
43 if (status & float_flag_divbyzero) {
44 env->fsr |= FSR_DZC;
45 }
46 if (status & float_flag_inexact) {
47 env->fsr |= FSR_NXC;
48 }
49
50 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
51 /* Unmasked exception, generate a trap */
52 env->fsr |= FSR_FTT_IEEE_EXCP;
53 helper_raise_exception(env, TT_FP_EXCP);
54 } else {
55 /* Accumulate exceptions */
56 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
57 }
58 }
59}
60
Andreas Färberc5f98642012-03-14 01:38:22 +010061static inline void clear_float_exceptions(CPUSPARCState *env)
Richard Henderson44516772011-10-17 11:25:56 -070062{
63 set_float_exception_flags(0, &env->fp_status);
64}
65
Andreas Färberc5f98642012-03-14 01:38:22 +010066#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +000067
68#define F_BINOP(name) \
Andreas Färberc5f98642012-03-14 01:38:22 +010069 float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
Blue Swirl2e2f4ad2011-07-03 10:42:23 +000070 float32 src2) \
Blue Swirl1bccec22011-08-01 07:37:45 +000071 { \
Richard Henderson44516772011-10-17 11:25:56 -070072 float32 ret; \
73 clear_float_exceptions(env); \
74 ret = float32_ ## name (src1, src2, &env->fp_status); \
75 check_ieee_exceptions(env); \
76 return ret; \
Blue Swirl1bccec22011-08-01 07:37:45 +000077 } \
Andreas Färberc5f98642012-03-14 01:38:22 +010078 float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
Richard Henderson03fb8cf2011-10-15 10:20:20 -070079 float64 src2) \
Blue Swirl1bccec22011-08-01 07:37:45 +000080 { \
Richard Henderson44516772011-10-17 11:25:56 -070081 float64 ret; \
82 clear_float_exceptions(env); \
83 ret = float64_ ## name (src1, src2, &env->fp_status); \
84 check_ieee_exceptions(env); \
85 return ret; \
Blue Swirl1bccec22011-08-01 07:37:45 +000086 } \
87 F_HELPER(name, q) \
88 { \
Richard Henderson44516772011-10-17 11:25:56 -070089 clear_float_exceptions(env); \
Blue Swirl1bccec22011-08-01 07:37:45 +000090 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
Richard Henderson44516772011-10-17 11:25:56 -070091 check_ieee_exceptions(env); \
Blue Swirl1bccec22011-08-01 07:37:45 +000092 }
93
94F_BINOP(add);
95F_BINOP(sub);
96F_BINOP(mul);
97F_BINOP(div);
98#undef F_BINOP
99
Andreas Färberc5f98642012-03-14 01:38:22 +0100100float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
Blue Swirl1bccec22011-08-01 07:37:45 +0000101{
Richard Henderson44516772011-10-17 11:25:56 -0700102 float64 ret;
103 clear_float_exceptions(env);
104 ret = float64_mul(float32_to_float64(src1, &env->fp_status),
105 float32_to_float64(src2, &env->fp_status),
106 &env->fp_status);
107 check_ieee_exceptions(env);
108 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000109}
110
Andreas Färberc5f98642012-03-14 01:38:22 +0100111void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
Blue Swirl1bccec22011-08-01 07:37:45 +0000112{
Richard Henderson44516772011-10-17 11:25:56 -0700113 clear_float_exceptions(env);
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700114 QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
115 float64_to_float128(src2, &env->fp_status),
Blue Swirl1bccec22011-08-01 07:37:45 +0000116 &env->fp_status);
Richard Henderson44516772011-10-17 11:25:56 -0700117 check_ieee_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000118}
119
120float32 helper_fnegs(float32 src)
121{
122 return float32_chs(src);
123}
124
125#ifdef TARGET_SPARC64
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700126float64 helper_fnegd(float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000127{
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700128 return float64_chs(src);
Blue Swirl1bccec22011-08-01 07:37:45 +0000129}
130
131F_HELPER(neg, q)
132{
133 QT0 = float128_chs(QT1);
134}
135#endif
136
137/* Integer to float conversion. */
Andreas Färberc5f98642012-03-14 01:38:22 +0100138float32 helper_fitos(CPUSPARCState *env, int32_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000139{
Richard Henderson44516772011-10-17 11:25:56 -0700140 /* Inexact error possible converting int to float. */
141 float32 ret;
142 clear_float_exceptions(env);
143 ret = int32_to_float32(src, &env->fp_status);
144 check_ieee_exceptions(env);
145 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000146}
147
Andreas Färberc5f98642012-03-14 01:38:22 +0100148float64 helper_fitod(CPUSPARCState *env, int32_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000149{
Richard Henderson44516772011-10-17 11:25:56 -0700150 /* No possible exceptions converting int to double. */
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700151 return int32_to_float64(src, &env->fp_status);
Blue Swirl1bccec22011-08-01 07:37:45 +0000152}
153
Andreas Färberc5f98642012-03-14 01:38:22 +0100154void helper_fitoq(CPUSPARCState *env, int32_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000155{
Richard Henderson44516772011-10-17 11:25:56 -0700156 /* No possible exceptions converting int to long double. */
Blue Swirl1bccec22011-08-01 07:37:45 +0000157 QT0 = int32_to_float128(src, &env->fp_status);
158}
159
160#ifdef TARGET_SPARC64
Andreas Färberc5f98642012-03-14 01:38:22 +0100161float32 helper_fxtos(CPUSPARCState *env, int64_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000162{
Richard Henderson44516772011-10-17 11:25:56 -0700163 float32 ret;
164 clear_float_exceptions(env);
165 ret = int64_to_float32(src, &env->fp_status);
166 check_ieee_exceptions(env);
167 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000168}
169
Andreas Färberc5f98642012-03-14 01:38:22 +0100170float64 helper_fxtod(CPUSPARCState *env, int64_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000171{
Richard Henderson44516772011-10-17 11:25:56 -0700172 float64 ret;
173 clear_float_exceptions(env);
174 ret = int64_to_float64(src, &env->fp_status);
175 check_ieee_exceptions(env);
176 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000177}
178
Andreas Färberc5f98642012-03-14 01:38:22 +0100179void helper_fxtoq(CPUSPARCState *env, int64_t src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000180{
Richard Henderson44516772011-10-17 11:25:56 -0700181 /* No possible exceptions converting long long to long double. */
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700182 QT0 = int64_to_float128(src, &env->fp_status);
Blue Swirl1bccec22011-08-01 07:37:45 +0000183}
184#endif
185#undef F_HELPER
186
187/* floating point conversion */
Andreas Färberc5f98642012-03-14 01:38:22 +0100188float32 helper_fdtos(CPUSPARCState *env, float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000189{
Richard Henderson44516772011-10-17 11:25:56 -0700190 float32 ret;
191 clear_float_exceptions(env);
192 ret = float64_to_float32(src, &env->fp_status);
193 check_ieee_exceptions(env);
194 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000195}
196
Andreas Färberc5f98642012-03-14 01:38:22 +0100197float64 helper_fstod(CPUSPARCState *env, float32 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000198{
Richard Henderson44516772011-10-17 11:25:56 -0700199 float64 ret;
200 clear_float_exceptions(env);
201 ret = float32_to_float64(src, &env->fp_status);
202 check_ieee_exceptions(env);
203 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000204}
205
Andreas Färberc5f98642012-03-14 01:38:22 +0100206float32 helper_fqtos(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000207{
Richard Henderson44516772011-10-17 11:25:56 -0700208 float32 ret;
209 clear_float_exceptions(env);
210 ret = float128_to_float32(QT1, &env->fp_status);
211 check_ieee_exceptions(env);
212 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000213}
214
Andreas Färberc5f98642012-03-14 01:38:22 +0100215void helper_fstoq(CPUSPARCState *env, float32 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000216{
Richard Henderson44516772011-10-17 11:25:56 -0700217 clear_float_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000218 QT0 = float32_to_float128(src, &env->fp_status);
Richard Henderson44516772011-10-17 11:25:56 -0700219 check_ieee_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000220}
221
Andreas Färberc5f98642012-03-14 01:38:22 +0100222float64 helper_fqtod(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000223{
Richard Henderson44516772011-10-17 11:25:56 -0700224 float64 ret;
225 clear_float_exceptions(env);
226 ret = float128_to_float64(QT1, &env->fp_status);
227 check_ieee_exceptions(env);
228 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000229}
230
Andreas Färberc5f98642012-03-14 01:38:22 +0100231void helper_fdtoq(CPUSPARCState *env, float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000232{
Richard Henderson44516772011-10-17 11:25:56 -0700233 clear_float_exceptions(env);
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700234 QT0 = float64_to_float128(src, &env->fp_status);
Richard Henderson44516772011-10-17 11:25:56 -0700235 check_ieee_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000236}
237
238/* Float to integer conversion. */
Andreas Färberc5f98642012-03-14 01:38:22 +0100239int32_t helper_fstoi(CPUSPARCState *env, float32 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000240{
Richard Henderson44516772011-10-17 11:25:56 -0700241 int32_t ret;
242 clear_float_exceptions(env);
243 ret = float32_to_int32_round_to_zero(src, &env->fp_status);
244 check_ieee_exceptions(env);
245 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000246}
247
Andreas Färberc5f98642012-03-14 01:38:22 +0100248int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000249{
Richard Henderson44516772011-10-17 11:25:56 -0700250 int32_t ret;
251 clear_float_exceptions(env);
252 ret = float64_to_int32_round_to_zero(src, &env->fp_status);
253 check_ieee_exceptions(env);
254 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000255}
256
Andreas Färberc5f98642012-03-14 01:38:22 +0100257int32_t helper_fqtoi(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000258{
Richard Henderson44516772011-10-17 11:25:56 -0700259 int32_t ret;
260 clear_float_exceptions(env);
261 ret = float128_to_int32_round_to_zero(QT1, &env->fp_status);
262 check_ieee_exceptions(env);
263 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000264}
265
266#ifdef TARGET_SPARC64
Andreas Färberc5f98642012-03-14 01:38:22 +0100267int64_t helper_fstox(CPUSPARCState *env, float32 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000268{
Richard Henderson44516772011-10-17 11:25:56 -0700269 int64_t ret;
270 clear_float_exceptions(env);
271 ret = float32_to_int64_round_to_zero(src, &env->fp_status);
272 check_ieee_exceptions(env);
273 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000274}
275
Andreas Färberc5f98642012-03-14 01:38:22 +0100276int64_t helper_fdtox(CPUSPARCState *env, float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000277{
Richard Henderson44516772011-10-17 11:25:56 -0700278 int64_t ret;
279 clear_float_exceptions(env);
280 ret = float64_to_int64_round_to_zero(src, &env->fp_status);
281 check_ieee_exceptions(env);
282 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000283}
284
Andreas Färberc5f98642012-03-14 01:38:22 +0100285int64_t helper_fqtox(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000286{
Richard Henderson44516772011-10-17 11:25:56 -0700287 int64_t ret;
288 clear_float_exceptions(env);
289 ret = float128_to_int64_round_to_zero(QT1, &env->fp_status);
290 check_ieee_exceptions(env);
291 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000292}
293#endif
294
295float32 helper_fabss(float32 src)
296{
297 return float32_abs(src);
298}
299
300#ifdef TARGET_SPARC64
Richard Hendersonf027c3b2011-10-19 14:56:43 -0700301float64 helper_fabsd(float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000302{
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700303 return float64_abs(src);
Blue Swirl1bccec22011-08-01 07:37:45 +0000304}
305
Andreas Färberc5f98642012-03-14 01:38:22 +0100306void helper_fabsq(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000307{
308 QT0 = float128_abs(QT1);
309}
310#endif
311
Andreas Färberc5f98642012-03-14 01:38:22 +0100312float32 helper_fsqrts(CPUSPARCState *env, float32 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000313{
Richard Henderson44516772011-10-17 11:25:56 -0700314 float32 ret;
315 clear_float_exceptions(env);
316 ret = float32_sqrt(src, &env->fp_status);
317 check_ieee_exceptions(env);
318 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000319}
320
Andreas Färberc5f98642012-03-14 01:38:22 +0100321float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
Blue Swirl1bccec22011-08-01 07:37:45 +0000322{
Richard Henderson44516772011-10-17 11:25:56 -0700323 float64 ret;
324 clear_float_exceptions(env);
325 ret = float64_sqrt(src, &env->fp_status);
326 check_ieee_exceptions(env);
327 return ret;
Blue Swirl1bccec22011-08-01 07:37:45 +0000328}
329
Andreas Färberc5f98642012-03-14 01:38:22 +0100330void helper_fsqrtq(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000331{
Richard Henderson44516772011-10-17 11:25:56 -0700332 clear_float_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000333 QT0 = float128_sqrt(QT1, &env->fp_status);
Richard Henderson44516772011-10-17 11:25:56 -0700334 check_ieee_exceptions(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000335}
336
337#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200338 void glue(helper_, name) (CPUSPARCState *env) \
Blue Swirl1bccec22011-08-01 07:37:45 +0000339 { \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200340 int ret; \
341 clear_float_exceptions(env); \
342 if (E) { \
343 ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \
344 } else { \
345 ret = glue(size, _compare_quiet)(reg1, reg2, \
346 &env->fp_status); \
Blue Swirl1bccec22011-08-01 07:37:45 +0000347 } \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200348 check_ieee_exceptions(env); \
349 switch (ret) { \
Blue Swirl1bccec22011-08-01 07:37:45 +0000350 case float_relation_unordered: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200351 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
352 env->fsr |= FSR_NVA; \
Blue Swirl1bccec22011-08-01 07:37:45 +0000353 break; \
354 case float_relation_less: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200355 env->fsr &= ~(FSR_FCC1) << FS; \
Blue Swirl1bccec22011-08-01 07:37:45 +0000356 env->fsr |= FSR_FCC0 << FS; \
357 break; \
358 case float_relation_greater: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200359 env->fsr &= ~(FSR_FCC0) << FS; \
Blue Swirl1bccec22011-08-01 07:37:45 +0000360 env->fsr |= FSR_FCC1 << FS; \
361 break; \
362 default: \
363 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
364 break; \
365 } \
366 }
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700367#define GEN_FCMP_T(name, size, FS, E) \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200368 void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \
Blue Swirl1bccec22011-08-01 07:37:45 +0000369 { \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200370 int ret; \
371 clear_float_exceptions(env); \
372 if (E) { \
373 ret = glue(size, _compare)(src1, src2, &env->fp_status); \
374 } else { \
375 ret = glue(size, _compare_quiet)(src1, src2, \
376 &env->fp_status); \
Blue Swirl1bccec22011-08-01 07:37:45 +0000377 } \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200378 check_ieee_exceptions(env); \
379 switch (ret) { \
Blue Swirl1bccec22011-08-01 07:37:45 +0000380 case float_relation_unordered: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200381 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
Blue Swirl1bccec22011-08-01 07:37:45 +0000382 break; \
383 case float_relation_less: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200384 env->fsr &= ~(FSR_FCC1 << FS); \
Blue Swirl1bccec22011-08-01 07:37:45 +0000385 env->fsr |= FSR_FCC0 << FS; \
386 break; \
387 case float_relation_greater: \
Aurelien Jarno5acfc832012-09-07 17:13:28 +0200388 env->fsr &= ~(FSR_FCC0 << FS); \
Blue Swirl1bccec22011-08-01 07:37:45 +0000389 env->fsr |= FSR_FCC1 << FS; \
390 break; \
391 default: \
392 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
393 break; \
394 } \
395 }
396
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700397GEN_FCMP_T(fcmps, float32, 0, 0);
398GEN_FCMP_T(fcmpd, float64, 0, 0);
Blue Swirl1bccec22011-08-01 07:37:45 +0000399
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700400GEN_FCMP_T(fcmpes, float32, 0, 1);
401GEN_FCMP_T(fcmped, float64, 0, 1);
Blue Swirl1bccec22011-08-01 07:37:45 +0000402
403GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
404GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
405
406#ifdef TARGET_SPARC64
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700407GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
408GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
Blue Swirl1bccec22011-08-01 07:37:45 +0000409GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
410
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700411GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
412GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
Blue Swirl1bccec22011-08-01 07:37:45 +0000413GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
414
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700415GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
416GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
Blue Swirl1bccec22011-08-01 07:37:45 +0000417GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
418
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700419GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
420GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
Blue Swirl1bccec22011-08-01 07:37:45 +0000421GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
422
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700423GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
424GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
Blue Swirl1bccec22011-08-01 07:37:45 +0000425GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
426
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700427GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
428GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
Blue Swirl1bccec22011-08-01 07:37:45 +0000429GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
430#endif
Richard Henderson03fb8cf2011-10-15 10:20:20 -0700431#undef GEN_FCMP_T
432#undef GEN_FCMP
Blue Swirl1bccec22011-08-01 07:37:45 +0000433
Andreas Färberc5f98642012-03-14 01:38:22 +0100434static inline void set_fsr(CPUSPARCState *env)
Blue Swirl1bccec22011-08-01 07:37:45 +0000435{
436 int rnd_mode;
437
438 switch (env->fsr & FSR_RD_MASK) {
439 case FSR_RD_NEAREST:
440 rnd_mode = float_round_nearest_even;
441 break;
442 default:
443 case FSR_RD_ZERO:
444 rnd_mode = float_round_to_zero;
445 break;
446 case FSR_RD_POS:
447 rnd_mode = float_round_up;
448 break;
449 case FSR_RD_NEG:
450 rnd_mode = float_round_down;
451 break;
452 }
453 set_float_rounding_mode(rnd_mode, &env->fp_status);
454}
455
Andreas Färberc5f98642012-03-14 01:38:22 +0100456void helper_ldfsr(CPUSPARCState *env, uint32_t new_fsr)
Blue Swirl1bccec22011-08-01 07:37:45 +0000457{
458 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
Blue Swirl2e2f4ad2011-07-03 10:42:23 +0000459 set_fsr(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000460}
461
462#ifdef TARGET_SPARC64
Andreas Färberc5f98642012-03-14 01:38:22 +0100463void helper_ldxfsr(CPUSPARCState *env, uint64_t new_fsr)
Blue Swirl1bccec22011-08-01 07:37:45 +0000464{
465 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
Blue Swirl2e2f4ad2011-07-03 10:42:23 +0000466 set_fsr(env);
Blue Swirl1bccec22011-08-01 07:37:45 +0000467}
468#endif