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aliguori16b29ae2008-12-17 23:28:44 +00001/*
2 * High Precisition Event Timer emulation
3 *
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
6 *
7 * Authors: Beth Kon <bkon@us.ibm.com>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000020 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
aliguori16b29ae2008-12-17 23:28:44 +000021 *
22 * *****************************************************************
23 *
24 * This driver attempts to emulate an HPET device in software.
25 */
26
27#include "hw.h"
aurel32bf4f74c2008-12-18 22:42:34 +000028#include "pc.h"
aliguori16b29ae2008-12-17 23:28:44 +000029#include "console.h"
30#include "qemu-timer.h"
31#include "hpet_emul.h"
32
aliguori16b29ae2008-12-17 23:28:44 +000033//#define HPET_DEBUG
34#ifdef HPET_DEBUG
35#define dprintf printf
36#else
37#define dprintf(...)
38#endif
39
40static HPETState *hpet_statep;
41
42uint32_t hpet_in_legacy_mode(void)
43{
44 if (hpet_statep)
45 return hpet_statep->config & HPET_CFG_LEGACY;
46 else
47 return 0;
48}
49
aurel32c50c2d62008-12-18 22:42:43 +000050static uint32_t timer_int_route(struct HPETTimer *timer)
aliguori16b29ae2008-12-17 23:28:44 +000051{
52 uint32_t route;
53 route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
54 return route;
55}
56
57static uint32_t hpet_enabled(void)
58{
59 return hpet_statep->config & HPET_CFG_ENABLE;
60}
61
62static uint32_t timer_is_periodic(HPETTimer *t)
63{
64 return t->config & HPET_TN_PERIODIC;
65}
66
67static uint32_t timer_enabled(HPETTimer *t)
68{
69 return t->config & HPET_TN_ENABLE;
70}
71
72static uint32_t hpet_time_after(uint64_t a, uint64_t b)
73{
74 return ((int32_t)(b) - (int32_t)(a) < 0);
75}
76
77static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
78{
79 return ((int64_t)(b) - (int64_t)(a) < 0);
80}
81
aurel32c50c2d62008-12-18 22:42:43 +000082static uint64_t ticks_to_ns(uint64_t value)
aliguori16b29ae2008-12-17 23:28:44 +000083{
84 return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
85}
86
aurel32c50c2d62008-12-18 22:42:43 +000087static uint64_t ns_to_ticks(uint64_t value)
aliguori16b29ae2008-12-17 23:28:44 +000088{
89 return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
90}
91
92static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
93{
94 new &= mask;
95 new |= old & ~mask;
96 return new;
97}
98
99static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
100{
aurel32c50c2d62008-12-18 22:42:43 +0000101 return (!(old & mask) && (new & mask));
aliguori16b29ae2008-12-17 23:28:44 +0000102}
103
104static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
105{
aurel32c50c2d62008-12-18 22:42:43 +0000106 return ((old & mask) && !(new & mask));
aliguori16b29ae2008-12-17 23:28:44 +0000107}
108
aurel32c50c2d62008-12-18 22:42:43 +0000109static uint64_t hpet_get_ticks(void)
aliguori16b29ae2008-12-17 23:28:44 +0000110{
111 uint64_t ticks;
112 ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
113 return ticks;
114}
115
aurel32c50c2d62008-12-18 22:42:43 +0000116/*
117 * calculate diff between comparator value and current ticks
aliguori16b29ae2008-12-17 23:28:44 +0000118 */
119static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
120{
aurel32c50c2d62008-12-18 22:42:43 +0000121
aliguori16b29ae2008-12-17 23:28:44 +0000122 if (t->config & HPET_TN_32BIT) {
123 uint32_t diff, cmp;
124 cmp = (uint32_t)t->cmp;
125 diff = cmp - (uint32_t)current;
126 diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
127 return (uint64_t)diff;
128 } else {
129 uint64_t diff, cmp;
130 cmp = t->cmp;
131 diff = cmp - current;
132 diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
133 return diff;
134 }
135}
136
137static void update_irq(struct HPETTimer *timer)
138{
139 qemu_irq irq;
140 int route;
141
142 if (timer->tn <= 1 && hpet_in_legacy_mode()) {
143 /* if LegacyReplacementRoute bit is set, HPET specification requires
144 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
aurel32c50c2d62008-12-18 22:42:43 +0000145 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
aliguori16b29ae2008-12-17 23:28:44 +0000146 */
147 if (timer->tn == 0) {
148 irq=timer->state->irqs[0];
149 } else
150 irq=timer->state->irqs[8];
151 } else {
152 route=timer_int_route(timer);
153 irq=timer->state->irqs[route];
154 }
155 if (timer_enabled(timer) && hpet_enabled()) {
156 qemu_irq_pulse(irq);
157 }
158}
159
160static void hpet_save(QEMUFile *f, void *opaque)
161{
162 HPETState *s = opaque;
163 int i;
164 qemu_put_be64s(f, &s->config);
165 qemu_put_be64s(f, &s->isr);
166 /* save current counter value */
aurel32c50c2d62008-12-18 22:42:43 +0000167 s->hpet_counter = hpet_get_ticks();
aliguori16b29ae2008-12-17 23:28:44 +0000168 qemu_put_be64s(f, &s->hpet_counter);
169
170 for (i = 0; i < HPET_NUM_TIMERS; i++) {
171 qemu_put_8s(f, &s->timer[i].tn);
172 qemu_put_be64s(f, &s->timer[i].config);
173 qemu_put_be64s(f, &s->timer[i].cmp);
174 qemu_put_be64s(f, &s->timer[i].fsb);
175 qemu_put_be64s(f, &s->timer[i].period);
176 qemu_put_8s(f, &s->timer[i].wrap_flag);
177 if (s->timer[i].qemu_timer) {
178 qemu_put_timer(f, s->timer[i].qemu_timer);
179 }
180 }
181}
182
183static int hpet_load(QEMUFile *f, void *opaque, int version_id)
184{
185 HPETState *s = opaque;
186 int i;
aurel32c50c2d62008-12-18 22:42:43 +0000187
aliguori16b29ae2008-12-17 23:28:44 +0000188 if (version_id != 1)
189 return -EINVAL;
190
191 qemu_get_be64s(f, &s->config);
192 qemu_get_be64s(f, &s->isr);
193 qemu_get_be64s(f, &s->hpet_counter);
194 /* Recalculate the offset between the main counter and guest time */
195 s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
196
197 for (i = 0; i < HPET_NUM_TIMERS; i++) {
198 qemu_get_8s(f, &s->timer[i].tn);
199 qemu_get_be64s(f, &s->timer[i].config);
200 qemu_get_be64s(f, &s->timer[i].cmp);
201 qemu_get_be64s(f, &s->timer[i].fsb);
202 qemu_get_be64s(f, &s->timer[i].period);
203 qemu_get_8s(f, &s->timer[i].wrap_flag);
204 if (s->timer[i].qemu_timer) {
205 qemu_get_timer(f, s->timer[i].qemu_timer);
206 }
207 }
208 return 0;
209}
210
aurel32c50c2d62008-12-18 22:42:43 +0000211/*
aliguori16b29ae2008-12-17 23:28:44 +0000212 * timer expiration callback
213 */
214static void hpet_timer(void *opaque)
215{
216 HPETTimer *t = (HPETTimer*)opaque;
217 uint64_t diff;
218
219 uint64_t period = t->period;
220 uint64_t cur_tick = hpet_get_ticks();
221
222 if (timer_is_periodic(t) && period != 0) {
223 if (t->config & HPET_TN_32BIT) {
224 while (hpet_time_after(cur_tick, t->cmp))
225 t->cmp = (uint32_t)(t->cmp + t->period);
226 } else
227 while (hpet_time_after64(cur_tick, t->cmp))
228 t->cmp += period;
229
230 diff = hpet_calculate_diff(t, cur_tick);
aurel32c50c2d62008-12-18 22:42:43 +0000231 qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
aliguori16b29ae2008-12-17 23:28:44 +0000232 + (int64_t)ticks_to_ns(diff));
233 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
234 if (t->wrap_flag) {
235 diff = hpet_calculate_diff(t, cur_tick);
aurel32c50c2d62008-12-18 22:42:43 +0000236 qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
aliguori16b29ae2008-12-17 23:28:44 +0000237 + (int64_t)ticks_to_ns(diff));
238 t->wrap_flag = 0;
239 }
240 }
241 update_irq(t);
242}
243
244static void hpet_set_timer(HPETTimer *t)
245{
246 uint64_t diff;
247 uint32_t wrap_diff; /* how many ticks until we wrap? */
248 uint64_t cur_tick = hpet_get_ticks();
aurel32c50c2d62008-12-18 22:42:43 +0000249
aliguori16b29ae2008-12-17 23:28:44 +0000250 /* whenever new timer is being set up, make sure wrap_flag is 0 */
251 t->wrap_flag = 0;
252 diff = hpet_calculate_diff(t, cur_tick);
253
aurel32c50c2d62008-12-18 22:42:43 +0000254 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
aliguori16b29ae2008-12-17 23:28:44 +0000255 * counter wraps in addition to an interrupt with comparator match.
aurel32c50c2d62008-12-18 22:42:43 +0000256 */
aliguori16b29ae2008-12-17 23:28:44 +0000257 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
258 wrap_diff = 0xffffffff - (uint32_t)cur_tick;
259 if (wrap_diff < (uint32_t)diff) {
260 diff = wrap_diff;
aurel32c50c2d62008-12-18 22:42:43 +0000261 t->wrap_flag = 1;
aliguori16b29ae2008-12-17 23:28:44 +0000262 }
263 }
aurel32c50c2d62008-12-18 22:42:43 +0000264 qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
aliguori16b29ae2008-12-17 23:28:44 +0000265 + (int64_t)ticks_to_ns(diff));
266}
267
268static void hpet_del_timer(HPETTimer *t)
269{
270 qemu_del_timer(t->qemu_timer);
271}
272
273#ifdef HPET_DEBUG
274static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
275{
276 printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
277 return 0;
278}
279
280static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
281{
282 printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
283 return 0;
284}
285#endif
286
287static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
288{
289 HPETState *s = (HPETState *)opaque;
290 uint64_t cur_tick, index;
291
292 dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
293 index = addr;
294 /*address range of all TN regs*/
295 if (index >= 0x100 && index <= 0x3ff) {
296 uint8_t timer_id = (addr - 0x100) / 0x20;
297 if (timer_id > HPET_NUM_TIMERS - 1) {
298 printf("qemu: timer id out of range\n");
299 return 0;
300 }
301 HPETTimer *timer = &s->timer[timer_id];
302
303 switch ((addr - 0x100) % 0x20) {
304 case HPET_TN_CFG:
305 return timer->config;
306 case HPET_TN_CFG + 4: // Interrupt capabilities
307 return timer->config >> 32;
308 case HPET_TN_CMP: // comparator register
309 return timer->cmp;
310 case HPET_TN_CMP + 4:
311 return timer->cmp >> 32;
312 case HPET_TN_ROUTE:
313 return timer->fsb >> 32;
314 default:
315 dprintf("qemu: invalid hpet_ram_readl\n");
316 break;
317 }
318 } else {
319 switch (index) {
320 case HPET_ID:
321 return s->capability;
322 case HPET_PERIOD:
aurel32c50c2d62008-12-18 22:42:43 +0000323 return s->capability >> 32;
aliguori16b29ae2008-12-17 23:28:44 +0000324 case HPET_CFG:
325 return s->config;
326 case HPET_CFG + 4:
327 dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
328 return 0;
aurel32c50c2d62008-12-18 22:42:43 +0000329 case HPET_COUNTER:
aliguori16b29ae2008-12-17 23:28:44 +0000330 if (hpet_enabled())
331 cur_tick = hpet_get_ticks();
aurel32c50c2d62008-12-18 22:42:43 +0000332 else
aliguori16b29ae2008-12-17 23:28:44 +0000333 cur_tick = s->hpet_counter;
334 dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
335 return cur_tick;
336 case HPET_COUNTER + 4:
337 if (hpet_enabled())
338 cur_tick = hpet_get_ticks();
aurel32c50c2d62008-12-18 22:42:43 +0000339 else
aliguori16b29ae2008-12-17 23:28:44 +0000340 cur_tick = s->hpet_counter;
341 dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
342 return cur_tick >> 32;
343 case HPET_STATUS:
344 return s->isr;
345 default:
346 dprintf("qemu: invalid hpet_ram_readl\n");
347 break;
348 }
349 }
350 return 0;
351}
352
353#ifdef HPET_DEBUG
aurel32c50c2d62008-12-18 22:42:43 +0000354static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
aliguori16b29ae2008-12-17 23:28:44 +0000355 uint32_t value)
356{
aurel32c50c2d62008-12-18 22:42:43 +0000357 printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
aliguori16b29ae2008-12-17 23:28:44 +0000358 addr, value);
359}
360
aurel32c50c2d62008-12-18 22:42:43 +0000361static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
aliguori16b29ae2008-12-17 23:28:44 +0000362 uint32_t value)
363{
aurel32c50c2d62008-12-18 22:42:43 +0000364 printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
aliguori16b29ae2008-12-17 23:28:44 +0000365 addr, value);
366}
367#endif
368
369static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
370 uint32_t value)
371{
372 int i;
373 HPETState *s = (HPETState *)opaque;
Beth Konce536cf2009-07-24 12:26:59 -0400374 uint64_t old_val, new_val, val, index;
aliguori16b29ae2008-12-17 23:28:44 +0000375
376 dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
377 index = addr;
378 old_val = hpet_ram_readl(opaque, addr);
379 new_val = value;
380
381 /*address range of all TN regs*/
382 if (index >= 0x100 && index <= 0x3ff) {
383 uint8_t timer_id = (addr - 0x100) / 0x20;
384 dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
385 HPETTimer *timer = &s->timer[timer_id];
aurel32c50c2d62008-12-18 22:42:43 +0000386
aliguori16b29ae2008-12-17 23:28:44 +0000387 switch ((addr - 0x100) % 0x20) {
388 case HPET_TN_CFG:
389 dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
Beth Konce536cf2009-07-24 12:26:59 -0400390 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
391 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
aliguori16b29ae2008-12-17 23:28:44 +0000392 if (new_val & HPET_TN_32BIT) {
393 timer->cmp = (uint32_t)timer->cmp;
394 timer->period = (uint32_t)timer->period;
395 }
396 if (new_val & HPET_TIMER_TYPE_LEVEL) {
397 printf("qemu: level-triggered hpet not supported\n");
398 exit (-1);
399 }
400
401 break;
402 case HPET_TN_CFG + 4: // Interrupt capabilities
403 dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
404 break;
405 case HPET_TN_CMP: // comparator register
406 dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
407 if (timer->config & HPET_TN_32BIT)
408 new_val = (uint32_t)new_val;
409 if (!timer_is_periodic(timer) ||
410 (timer->config & HPET_TN_SETVAL))
411 timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
412 | new_val;
aliguori37873242009-04-17 20:50:58 +0000413 if (timer_is_periodic(timer)) {
aliguori16b29ae2008-12-17 23:28:44 +0000414 /*
415 * FIXME: Clamp period to reasonable min value?
416 * Clamp period to reasonable max value
417 */
418 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
419 timer->period = (timer->period & 0xffffffff00000000ULL)
420 | new_val;
421 }
422 timer->config &= ~HPET_TN_SETVAL;
423 if (hpet_enabled())
424 hpet_set_timer(timer);
425 break;
426 case HPET_TN_CMP + 4: // comparator register high order
427 dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
428 if (!timer_is_periodic(timer) ||
429 (timer->config & HPET_TN_SETVAL))
430 timer->cmp = (timer->cmp & 0xffffffffULL)
431 | new_val << 32;
432 else {
433 /*
434 * FIXME: Clamp period to reasonable min value?
435 * Clamp period to reasonable max value
436 */
aurel32c50c2d62008-12-18 22:42:43 +0000437 new_val &= (timer->config
aliguori16b29ae2008-12-17 23:28:44 +0000438 & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
439 timer->period = (timer->period & 0xffffffffULL)
440 | new_val << 32;
441 }
442 timer->config &= ~HPET_TN_SETVAL;
443 if (hpet_enabled())
444 hpet_set_timer(timer);
445 break;
446 case HPET_TN_ROUTE + 4:
447 dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
448 break;
449 default:
450 dprintf("qemu: invalid hpet_ram_writel\n");
451 break;
452 }
453 return;
454 } else {
455 switch (index) {
456 case HPET_ID:
457 return;
458 case HPET_CFG:
Beth Konce536cf2009-07-24 12:26:59 -0400459 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
460 s->config = (s->config & 0xffffffff00000000ULL) | val;
aliguori16b29ae2008-12-17 23:28:44 +0000461 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
462 /* Enable main counter and interrupt generation. */
463 s->hpet_offset = ticks_to_ns(s->hpet_counter)
464 - qemu_get_clock(vm_clock);
465 for (i = 0; i < HPET_NUM_TIMERS; i++)
466 if ((&s->timer[i])->cmp != ~0ULL)
467 hpet_set_timer(&s->timer[i]);
468 }
469 else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
470 /* Halt main counter and disable interrupt generation. */
aurel32c50c2d62008-12-18 22:42:43 +0000471 s->hpet_counter = hpet_get_ticks();
aliguori16b29ae2008-12-17 23:28:44 +0000472 for (i = 0; i < HPET_NUM_TIMERS; i++)
473 hpet_del_timer(&s->timer[i]);
474 }
475 /* i8254 and RTC are disabled when HPET is in legacy mode */
476 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
477 hpet_pit_disable();
478 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
479 hpet_pit_enable();
480 }
481 break;
aurel32c50c2d62008-12-18 22:42:43 +0000482 case HPET_CFG + 4:
aliguori16b29ae2008-12-17 23:28:44 +0000483 dprintf("qemu: invalid HPET_CFG+4 write \n");
484 break;
485 case HPET_STATUS:
486 /* FIXME: need to handle level-triggered interrupts */
487 break;
488 case HPET_COUNTER:
aurel32c50c2d62008-12-18 22:42:43 +0000489 if (hpet_enabled())
490 printf("qemu: Writing counter while HPET enabled!\n");
491 s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
aliguori16b29ae2008-12-17 23:28:44 +0000492 | value;
493 dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
494 value, s->hpet_counter);
495 break;
496 case HPET_COUNTER + 4:
aurel32c50c2d62008-12-18 22:42:43 +0000497 if (hpet_enabled())
498 printf("qemu: Writing counter while HPET enabled!\n");
499 s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
aliguori16b29ae2008-12-17 23:28:44 +0000500 | (((uint64_t)value) << 32);
501 dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
502 value, s->hpet_counter);
503 break;
504 default:
505 dprintf("qemu: invalid hpet_ram_writel\n");
506 break;
507 }
508 }
509}
510
Blue Swirld60efc62009-08-25 18:29:31 +0000511static CPUReadMemoryFunc * const hpet_ram_read[] = {
aliguori16b29ae2008-12-17 23:28:44 +0000512#ifdef HPET_DEBUG
513 hpet_ram_readb,
514 hpet_ram_readw,
515#else
516 NULL,
517 NULL,
518#endif
519 hpet_ram_readl,
520};
521
Blue Swirld60efc62009-08-25 18:29:31 +0000522static CPUWriteMemoryFunc * const hpet_ram_write[] = {
aliguori16b29ae2008-12-17 23:28:44 +0000523#ifdef HPET_DEBUG
524 hpet_ram_writeb,
525 hpet_ram_writew,
526#else
527 NULL,
528 NULL,
529#endif
530 hpet_ram_writel,
531};
532
533static void hpet_reset(void *opaque) {
534 HPETState *s = opaque;
535 int i;
536 static int count = 0;
537
538 for (i=0; i<HPET_NUM_TIMERS; i++) {
539 HPETTimer *timer = &s->timer[i];
540 hpet_del_timer(timer);
541 timer->tn = i;
542 timer->cmp = ~0ULL;
543 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
Beth Konce536cf2009-07-24 12:26:59 -0400544 /* advertise availability of ioapic inti2 */
545 timer->config |= 0x00000004ULL << 32;
aliguori16b29ae2008-12-17 23:28:44 +0000546 timer->state = s;
547 timer->period = 0ULL;
548 timer->wrap_flag = 0;
549 }
550
551 s->hpet_counter = 0ULL;
552 s->hpet_offset = 0ULL;
553 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
554 s->capability = 0x8086a201ULL;
555 s->capability |= ((HPET_CLK_PERIOD) << 32);
Beth Kon7d93b1f2009-07-13 19:43:13 -0400556 s->config = 0ULL;
aliguori16b29ae2008-12-17 23:28:44 +0000557 if (count > 0)
aurel32c50c2d62008-12-18 22:42:43 +0000558 /* we don't enable pit when hpet_reset is first called (by hpet_init)
aliguori16b29ae2008-12-17 23:28:44 +0000559 * because hpet is taking over for pit here. On subsequent invocations,
560 * hpet_reset is called due to system reset. At this point control must
aurel32c50c2d62008-12-18 22:42:43 +0000561 * be returned to pit until SW reenables hpet.
aliguori16b29ae2008-12-17 23:28:44 +0000562 */
563 hpet_pit_enable();
564 count = 1;
565}
566
567
568void hpet_init(qemu_irq *irq) {
569 int i, iomemtype;
570 HPETState *s;
aurel32c50c2d62008-12-18 22:42:43 +0000571
aliguori16b29ae2008-12-17 23:28:44 +0000572 dprintf ("hpet_init\n");
573
574 s = qemu_mallocz(sizeof(HPETState));
575 hpet_statep = s;
576 s->irqs = irq;
577 for (i=0; i<HPET_NUM_TIMERS; i++) {
578 HPETTimer *timer = &s->timer[i];
579 timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
580 }
581 hpet_reset(s);
582 register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200583 qemu_register_reset(hpet_reset, s);
aliguori16b29ae2008-12-17 23:28:44 +0000584 /* HPET Area */
Avi Kivity1eed09c2009-06-14 11:38:51 +0300585 iomemtype = cpu_register_io_memory(hpet_ram_read,
aliguori16b29ae2008-12-17 23:28:44 +0000586 hpet_ram_write, s);
587 cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
588}