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Richard Henderson80bb2ff2011-08-25 11:38:59 -10001/*
2 * QEMU Alpha PCI support functions.
3 *
4 * Some of this isn't very Alpha specific at all.
5 *
6 * ??? Sparse memory access not implemented.
7 */
8
Peter Maydelle2e5e112016-01-26 18:17:04 +00009#include "qemu/osdep.h"
Paolo Bonzini4771d752016-01-19 21:51:44 +010010#include "qemu-common.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010011#include "alpha_sys.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010012#include "qemu/log.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010013#include "sysemu/sysemu.h"
Paolo Bonzinic6ce9f12015-11-13 13:23:45 +010014#include "trace.h"
Richard Henderson80bb2ff2011-08-25 11:38:59 -100015
16
Richard Henderson36610492013-07-08 15:46:37 -070017/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
18
19static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
20{
21 return 0;
22}
23
24static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
25{
26}
27
28const MemoryRegionOps alpha_pci_ignore_ops = {
29 .read = ignore_read,
30 .write = ignore_write,
31 .endianness = DEVICE_LITTLE_ENDIAN,
32 .valid = {
33 .min_access_size = 1,
34 .max_access_size = 8,
35 },
36 .impl = {
37 .min_access_size = 1,
38 .max_access_size = 8,
39 },
40};
41
42
Richard Henderson80bb2ff2011-08-25 11:38:59 -100043/* PCI config space reads/writes, to byte-word addressable memory. */
Avi Kivitya8170e52012-10-23 12:30:10 +020044static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
Richard Henderson80bb2ff2011-08-25 11:38:59 -100045 unsigned size)
46{
47 PCIBus *b = opaque;
48 return pci_data_read(b, addr, size);
49}
50
Avi Kivitya8170e52012-10-23 12:30:10 +020051static void bw_conf1_write(void *opaque, hwaddr addr,
Richard Henderson80bb2ff2011-08-25 11:38:59 -100052 uint64_t val, unsigned size)
53{
54 PCIBus *b = opaque;
55 pci_data_write(b, addr, val, size);
56}
57
58const MemoryRegionOps alpha_pci_conf1_ops = {
59 .read = bw_conf1_read,
60 .write = bw_conf1_write,
61 .endianness = DEVICE_LITTLE_ENDIAN,
62 .impl = {
63 .min_access_size = 1,
64 .max_access_size = 4,
65 },
66};
67
68/* PCI/EISA Interrupt Acknowledge Cycle. */
69
Avi Kivitya8170e52012-10-23 12:30:10 +020070static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
Richard Henderson80bb2ff2011-08-25 11:38:59 -100071{
72 return pic_read_irq(isa_pic);
73}
74
Avi Kivitya8170e52012-10-23 12:30:10 +020075static void special_write(void *opaque, hwaddr addr,
Richard Henderson80bb2ff2011-08-25 11:38:59 -100076 uint64_t val, unsigned size)
77{
Paolo Bonzinic6ce9f12015-11-13 13:23:45 +010078 trace_alpha_pci_iack_write();
Richard Henderson80bb2ff2011-08-25 11:38:59 -100079}
80
81const MemoryRegionOps alpha_pci_iack_ops = {
82 .read = iack_read,
83 .write = special_write,
84 .endianness = DEVICE_LITTLE_ENDIAN,
85 .valid = {
86 .min_access_size = 4,
87 .max_access_size = 4,
88 },
89 .impl = {
90 .min_access_size = 4,
91 .max_access_size = 4,
92 },
93};