Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 1 | /* |
| 2 | * VT82C686B south bridge support |
| 3 | * |
| 4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) |
| 5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) |
| 6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) |
| 7 | * This code is licensed under the GNU GPL v2. |
| 8 | */ |
| 9 | |
| 10 | #include "hw.h" |
| 11 | #include "pc.h" |
| 12 | #include "vt82c686.h" |
| 13 | #include "i2c.h" |
| 14 | #include "smbus.h" |
| 15 | #include "pci.h" |
| 16 | #include "isa.h" |
| 17 | #include "sysbus.h" |
| 18 | #include "mips.h" |
| 19 | #include "apm.h" |
| 20 | #include "acpi.h" |
| 21 | #include "pm_smbus.h" |
| 22 | #include "sysemu.h" |
| 23 | #include "qemu-timer.h" |
| 24 | |
| 25 | typedef uint32_t pci_addr_t; |
| 26 | #include "pci_host.h" |
| 27 | //#define DEBUG_VT82C686B |
| 28 | |
| 29 | #ifdef DEBUG_VT82C686B |
| 30 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
| 31 | #else |
| 32 | #define DPRINTF(fmt, ...) |
| 33 | #endif |
| 34 | |
| 35 | typedef struct SuperIOConfig |
| 36 | { |
| 37 | uint8_t config[0xff]; |
| 38 | uint8_t index; |
| 39 | uint8_t data; |
| 40 | } SuperIOConfig; |
| 41 | |
| 42 | typedef struct VT82C686BState { |
| 43 | PCIDevice dev; |
| 44 | SuperIOConfig superio_conf; |
| 45 | } VT82C686BState; |
| 46 | |
| 47 | static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) |
| 48 | { |
| 49 | int can_write; |
| 50 | SuperIOConfig *superio_conf = opaque; |
| 51 | |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 52 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 53 | if (addr == 0x3f0) { |
| 54 | superio_conf->index = data & 0xff; |
| 55 | } else { |
| 56 | /* 0x3f1 */ |
| 57 | switch (superio_conf->index) { |
| 58 | case 0x00 ... 0xdf: |
| 59 | case 0xe4: |
| 60 | case 0xe5: |
| 61 | case 0xe9 ... 0xed: |
| 62 | case 0xf3: |
| 63 | case 0xf5: |
| 64 | case 0xf7: |
| 65 | case 0xf9 ... 0xfb: |
| 66 | case 0xfd ... 0xff: |
| 67 | can_write = 0; |
| 68 | break; |
| 69 | default: |
| 70 | can_write = 1; |
| 71 | |
| 72 | if (can_write) { |
| 73 | switch (superio_conf->index) { |
| 74 | case 0xe7: |
| 75 | if ((data & 0xff) != 0xfe) { |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 76 | DPRINTF("chage uart 1 base. unsupported yet\n"); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 77 | } |
| 78 | break; |
| 79 | case 0xe8: |
| 80 | if ((data & 0xff) != 0xbe) { |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 81 | DPRINTF("chage uart 2 base. unsupported yet\n"); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 82 | } |
| 83 | break; |
| 84 | |
| 85 | default: |
| 86 | superio_conf->config[superio_conf->index] = data & 0xff; |
| 87 | } |
| 88 | } |
| 89 | } |
| 90 | superio_conf->config[superio_conf->index] = data & 0xff; |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) |
| 95 | { |
| 96 | SuperIOConfig *superio_conf = opaque; |
| 97 | |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 98 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 99 | return (superio_conf->config[superio_conf->index]); |
| 100 | } |
| 101 | |
| 102 | static void vt82c686b_reset(void * opaque) |
| 103 | { |
| 104 | PCIDevice *d = opaque; |
| 105 | uint8_t *pci_conf = d->config; |
| 106 | VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); |
| 107 | |
| 108 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
| 109 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 110 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
| 111 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
| 112 | |
| 113 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ |
| 114 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ |
| 115 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ |
| 116 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ |
| 117 | pci_conf[0x59] = 0x04; |
| 118 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ |
| 119 | pci_conf[0x5f] = 0x04; |
| 120 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ |
| 121 | |
| 122 | vt82c->superio_conf.config[0xe0] = 0x3c; |
| 123 | vt82c->superio_conf.config[0xe2] = 0x03; |
| 124 | vt82c->superio_conf.config[0xe3] = 0xfc; |
| 125 | vt82c->superio_conf.config[0xe6] = 0xde; |
| 126 | vt82c->superio_conf.config[0xe7] = 0xfe; |
| 127 | vt82c->superio_conf.config[0xe8] = 0xbe; |
| 128 | } |
| 129 | |
| 130 | /* write config pci function0 registers. PCI-ISA bridge */ |
| 131 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, |
| 132 | uint32_t val, int len) |
| 133 | { |
| 134 | VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); |
| 135 | |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 136 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 137 | address, val, len); |
| 138 | |
| 139 | pci_default_write_config(d, address, val, len); |
| 140 | if (address == 0x85) { /* enable or disable super IO configure */ |
| 141 | if (val & 0x2) { |
| 142 | /* floppy also uses 0x3f0 and 0x3f1. |
| 143 | * But we do not emulate flopy,so just set it here. */ |
| 144 | isa_unassign_ioport(0x3f0, 2); |
| 145 | register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, |
| 146 | &vt686->superio_conf); |
| 147 | register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, |
| 148 | &vt686->superio_conf); |
| 149 | } else { |
| 150 | isa_unassign_ioport(0x3f0, 2); |
| 151 | } |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | #define ACPI_DBG_IO_ADDR 0xb044 |
| 156 | |
| 157 | typedef struct VT686PMState { |
| 158 | PCIDevice dev; |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 159 | ACPIPM1EVT pm1a; |
Isaku Yamahata | eaba51c | 2011-03-25 19:54:40 +0900 | [diff] [blame] | 160 | ACPIPM1CNT pm1_cnt; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 161 | APMState apm; |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 162 | ACPIPMTimer tmr; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 163 | PMSMBus smb; |
| 164 | uint32_t smb_io_base; |
| 165 | } VT686PMState; |
| 166 | |
| 167 | typedef struct VT686AC97State { |
| 168 | PCIDevice dev; |
| 169 | } VT686AC97State; |
| 170 | |
| 171 | typedef struct VT686MC97State { |
| 172 | PCIDevice dev; |
| 173 | } VT686MC97State; |
| 174 | |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 175 | static void pm_update_sci(VT686PMState *s) |
| 176 | { |
| 177 | int sci_level, pmsts; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 178 | |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 179 | pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
| 180 | sci_level = (((pmsts & s->pm1a.en) & |
| 181 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
| 182 | ACPI_BITMASK_POWER_BUTTON_ENABLE | |
| 183 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
| 184 | ACPI_BITMASK_TIMER_ENABLE)) != 0); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 185 | qemu_set_irq(s->dev.irq[0], sci_level); |
| 186 | /* schedule a timer interruption if needed */ |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 187 | acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) && |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 188 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 189 | } |
| 190 | |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 191 | static void pm_tmr_timer(ACPIPMTimer *tmr) |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 192 | { |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 193 | VT686PMState *s = container_of(tmr, VT686PMState, tmr); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 194 | pm_update_sci(s); |
| 195 | } |
| 196 | |
| 197 | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
| 198 | { |
| 199 | VT686PMState *s = opaque; |
| 200 | |
| 201 | addr &= 0x0f; |
| 202 | switch (addr) { |
| 203 | case 0x00: |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 204 | acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val); |
| 205 | pm_update_sci(s); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 206 | break; |
| 207 | case 0x02: |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 208 | s->pm1a.en = val; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 209 | pm_update_sci(s); |
| 210 | break; |
| 211 | case 0x04: |
Isaku Yamahata | eaba51c | 2011-03-25 19:54:40 +0900 | [diff] [blame] | 212 | acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 213 | break; |
| 214 | default: |
| 215 | break; |
| 216 | } |
| 217 | DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val); |
| 218 | } |
| 219 | |
| 220 | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
| 221 | { |
| 222 | VT686PMState *s = opaque; |
| 223 | uint32_t val; |
| 224 | |
| 225 | addr &= 0x0f; |
| 226 | switch (addr) { |
| 227 | case 0x00: |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 228 | val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 229 | break; |
| 230 | case 0x02: |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 231 | val = s->pm1a.en; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 232 | break; |
| 233 | case 0x04: |
Isaku Yamahata | eaba51c | 2011-03-25 19:54:40 +0900 | [diff] [blame] | 234 | val = s->pm1_cnt.cnt; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 235 | break; |
| 236 | default: |
| 237 | val = 0; |
| 238 | break; |
| 239 | } |
| 240 | DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val); |
| 241 | return val; |
| 242 | } |
| 243 | |
| 244 | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 245 | { |
| 246 | addr &= 0x0f; |
| 247 | DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val); |
| 248 | } |
| 249 | |
| 250 | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
| 251 | { |
| 252 | VT686PMState *s = opaque; |
| 253 | uint32_t val; |
| 254 | |
| 255 | addr &= 0x0f; |
| 256 | switch (addr) { |
| 257 | case 0x08: |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 258 | val = acpi_pm_tmr_get(&s->tmr); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 259 | break; |
| 260 | default: |
| 261 | val = 0; |
| 262 | break; |
| 263 | } |
| 264 | DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val); |
| 265 | return val; |
| 266 | } |
| 267 | |
| 268 | static void pm_io_space_update(VT686PMState *s) |
| 269 | { |
| 270 | uint32_t pm_io_base; |
| 271 | |
| 272 | if (s->dev.config[0x80] & 1) { |
| 273 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
| 274 | pm_io_base &= 0xffc0; |
| 275 | |
| 276 | /* XXX: need to improve memory and ioport allocation */ |
| 277 | DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
| 278 | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
| 279 | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
| 280 | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
| 281 | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | static void pm_write_config(PCIDevice *d, |
| 286 | uint32_t address, uint32_t val, int len) |
| 287 | { |
Stefan Weil | b2bedb2 | 2011-09-12 22:33:01 +0200 | [diff] [blame] | 288 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 289 | address, val, len); |
| 290 | pci_default_write_config(d, address, val, len); |
| 291 | } |
| 292 | |
| 293 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
| 294 | { |
| 295 | VT686PMState *s = opaque; |
| 296 | |
| 297 | pm_io_space_update(s); |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | static const VMStateDescription vmstate_acpi = { |
| 302 | .name = "vt82c686b_pm", |
| 303 | .version_id = 1, |
| 304 | .minimum_version_id = 1, |
| 305 | .minimum_version_id_old = 1, |
| 306 | .post_load = vmstate_acpi_post_load, |
| 307 | .fields = (VMStateField []) { |
| 308 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
Isaku Yamahata | 04dc308 | 2011-03-25 19:54:39 +0900 | [diff] [blame] | 309 | VMSTATE_UINT16(pm1a.sts, VT686PMState), |
| 310 | VMSTATE_UINT16(pm1a.en, VT686PMState), |
Isaku Yamahata | eaba51c | 2011-03-25 19:54:40 +0900 | [diff] [blame] | 311 | VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState), |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 312 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 313 | VMSTATE_TIMER(tmr.timer, VT686PMState), |
| 314 | VMSTATE_INT64(tmr.overflow_time, VT686PMState), |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 315 | VMSTATE_END_OF_LIST() |
| 316 | } |
| 317 | }; |
| 318 | |
| 319 | /* |
| 320 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() |
| 321 | * just register a PCI device now, functionalities will be implemented later. |
| 322 | */ |
| 323 | |
| 324 | static int vt82c686b_ac97_initfn(PCIDevice *dev) |
| 325 | { |
| 326 | VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); |
| 327 | uint8_t *pci_conf = s->dev.config; |
| 328 | |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 329 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
| 330 | PCI_COMMAND_PARITY); |
| 331 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | |
| 332 | PCI_STATUS_DEVSEL_MEDIUM); |
| 333 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) |
| 339 | { |
| 340 | PCIDevice *dev; |
| 341 | |
| 342 | dev = pci_create(bus, devfn, "VT82C686B_AC97"); |
| 343 | qdev_init_nofail(&dev->qdev); |
| 344 | } |
| 345 | |
| 346 | static PCIDeviceInfo via_ac97_info = { |
| 347 | .qdev.name = "VT82C686B_AC97", |
| 348 | .qdev.desc = "AC97", |
| 349 | .qdev.size = sizeof(VT686AC97State), |
| 350 | .init = vt82c686b_ac97_initfn, |
Isaku Yamahata | 1cf0d2b | 2011-05-25 10:58:32 +0900 | [diff] [blame] | 351 | .vendor_id = PCI_VENDOR_ID_VIA, |
| 352 | .device_id = PCI_DEVICE_ID_VIA_AC97, |
| 353 | .revision = 0x50, |
| 354 | .class_id = PCI_CLASS_MULTIMEDIA_AUDIO, |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 355 | }; |
| 356 | |
| 357 | static void vt82c686b_ac97_register(void) |
| 358 | { |
| 359 | pci_qdev_register(&via_ac97_info); |
| 360 | } |
| 361 | |
| 362 | device_init(vt82c686b_ac97_register); |
| 363 | |
| 364 | static int vt82c686b_mc97_initfn(PCIDevice *dev) |
| 365 | { |
| 366 | VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); |
| 367 | uint8_t *pci_conf = s->dev.config; |
| 368 | |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 369 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
| 370 | PCI_COMMAND_VGA_PALETTE); |
| 371 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
| 372 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) |
| 378 | { |
| 379 | PCIDevice *dev; |
| 380 | |
| 381 | dev = pci_create(bus, devfn, "VT82C686B_MC97"); |
| 382 | qdev_init_nofail(&dev->qdev); |
| 383 | } |
| 384 | |
| 385 | static PCIDeviceInfo via_mc97_info = { |
| 386 | .qdev.name = "VT82C686B_MC97", |
| 387 | .qdev.desc = "MC97", |
| 388 | .qdev.size = sizeof(VT686MC97State), |
| 389 | .init = vt82c686b_mc97_initfn, |
Isaku Yamahata | 1cf0d2b | 2011-05-25 10:58:32 +0900 | [diff] [blame] | 390 | .vendor_id = PCI_VENDOR_ID_VIA, |
| 391 | .device_id = PCI_DEVICE_ID_VIA_MC97, |
| 392 | .class_id = PCI_CLASS_COMMUNICATION_OTHER, |
| 393 | .revision = 0x30, |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | static void vt82c686b_mc97_register(void) |
| 397 | { |
| 398 | pci_qdev_register(&via_mc97_info); |
| 399 | } |
| 400 | |
| 401 | device_init(vt82c686b_mc97_register); |
| 402 | |
| 403 | /* vt82c686 pm init */ |
| 404 | static int vt82c686b_pm_initfn(PCIDevice *dev) |
| 405 | { |
| 406 | VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); |
| 407 | uint8_t *pci_conf; |
| 408 | |
| 409 | pci_conf = s->dev.config; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 410 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
| 411 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
| 412 | PCI_STATUS_DEVSEL_MEDIUM); |
| 413 | |
| 414 | /* 0x48-0x4B is Power Management I/O Base */ |
| 415 | pci_set_long(pci_conf + 0x48, 0x00000001); |
| 416 | |
| 417 | /* SMB ports:0xeee0~0xeeef */ |
| 418 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); |
| 419 | pci_conf[0x90] = s->smb_io_base | 1; |
| 420 | pci_conf[0x91] = s->smb_io_base >> 8; |
| 421 | pci_conf[0xd2] = 0x90; |
| 422 | register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); |
| 423 | register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); |
| 424 | |
| 425 | apm_init(&s->apm, NULL, s); |
| 426 | |
Isaku Yamahata | a54d41a | 2011-03-25 19:54:38 +0900 | [diff] [blame] | 427 | acpi_pm_tmr_init(&s->tmr, pm_tmr_timer); |
Isaku Yamahata | eaba51c | 2011-03-25 19:54:40 +0900 | [diff] [blame] | 428 | acpi_pm1_cnt_init(&s->pm1_cnt, NULL); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 429 | |
| 430 | pm_smbus_init(&s->dev.qdev, &s->smb); |
| 431 | |
| 432 | return 0; |
| 433 | } |
| 434 | |
| 435 | i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
| 436 | qemu_irq sci_irq) |
| 437 | { |
| 438 | PCIDevice *dev; |
| 439 | VT686PMState *s; |
| 440 | |
| 441 | dev = pci_create(bus, devfn, "VT82C686B_PM"); |
| 442 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); |
| 443 | |
| 444 | s = DO_UPCAST(VT686PMState, dev, dev); |
| 445 | |
| 446 | qdev_init_nofail(&dev->qdev); |
| 447 | |
| 448 | return s->smb.smbus; |
| 449 | } |
| 450 | |
| 451 | static PCIDeviceInfo via_pm_info = { |
| 452 | .qdev.name = "VT82C686B_PM", |
| 453 | .qdev.desc = "PM", |
| 454 | .qdev.size = sizeof(VT686PMState), |
| 455 | .qdev.vmsd = &vmstate_acpi, |
| 456 | .init = vt82c686b_pm_initfn, |
| 457 | .config_write = pm_write_config, |
Isaku Yamahata | 1cf0d2b | 2011-05-25 10:58:32 +0900 | [diff] [blame] | 458 | .vendor_id = PCI_VENDOR_ID_VIA, |
| 459 | .device_id = PCI_DEVICE_ID_VIA_ACPI, |
| 460 | .class_id = PCI_CLASS_BRIDGE_OTHER, |
| 461 | .revision = 0x40, |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 462 | .qdev.props = (Property[]) { |
| 463 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), |
| 464 | DEFINE_PROP_END_OF_LIST(), |
| 465 | } |
| 466 | }; |
| 467 | |
| 468 | static void vt82c686b_pm_register(void) |
| 469 | { |
| 470 | pci_qdev_register(&via_pm_info); |
| 471 | } |
| 472 | |
| 473 | device_init(vt82c686b_pm_register); |
| 474 | |
| 475 | static const VMStateDescription vmstate_via = { |
| 476 | .name = "vt82c686b", |
| 477 | .version_id = 1, |
| 478 | .minimum_version_id = 1, |
| 479 | .minimum_version_id_old = 1, |
| 480 | .fields = (VMStateField []) { |
| 481 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
| 482 | VMSTATE_END_OF_LIST() |
| 483 | } |
| 484 | }; |
| 485 | |
| 486 | /* init the PCI-to-ISA bridge */ |
| 487 | static int vt82c686b_initfn(PCIDevice *d) |
| 488 | { |
| 489 | uint8_t *pci_conf; |
| 490 | uint8_t *wmask; |
| 491 | int i; |
| 492 | |
Richard Henderson | c2d0d01 | 2011-08-10 15:28:11 -0700 | [diff] [blame] | 493 | isa_bus_new(&d->qdev, pci_address_space_io(d)); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 494 | |
| 495 | pci_conf = d->config; |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 496 | pci_config_set_prog_interface(pci_conf, 0x0); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 497 | |
| 498 | wmask = d->wmask; |
| 499 | for (i = 0x00; i < 0xff; i++) { |
| 500 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { |
| 501 | wmask[i] = 0x00; |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | qemu_register_reset(vt82c686b_reset, d); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | int vt82c686b_init(PCIBus *bus, int devfn) |
| 511 | { |
| 512 | PCIDevice *d; |
| 513 | |
Isaku Yamahata | aa5fb7b | 2010-07-12 20:53:57 +0900 | [diff] [blame] | 514 | d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 515 | |
| 516 | return d->devfn; |
| 517 | } |
| 518 | |
| 519 | static PCIDeviceInfo via_info = { |
| 520 | .qdev.name = "VT82C686B", |
| 521 | .qdev.desc = "ISA bridge", |
| 522 | .qdev.size = sizeof(VT82C686BState), |
| 523 | .qdev.vmsd = &vmstate_via, |
| 524 | .qdev.no_user = 1, |
| 525 | .init = vt82c686b_initfn, |
| 526 | .config_write = vt82c686b_write_config, |
Isaku Yamahata | 1cf0d2b | 2011-05-25 10:58:32 +0900 | [diff] [blame] | 527 | .vendor_id = PCI_VENDOR_ID_VIA, |
| 528 | .device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE, |
| 529 | .class_id = PCI_CLASS_BRIDGE_ISA, |
| 530 | .revision = 0x40, |
Huacai Chen | edf79e6 | 2010-06-29 10:49:29 +0800 | [diff] [blame] | 531 | }; |
| 532 | |
| 533 | static void vt82c686b_register(void) |
| 534 | { |
| 535 | pci_qdev_register(&via_info); |
| 536 | } |
| 537 | device_init(vt82c686b_register); |